JPS62262291A - Semiconductor read/write memory device - Google Patents

Abstract

PURPOSE:To enable the bit constitution of a read/write memory device to be changed at the actual use time of a semiconductor memory device, by sifting the output content of a specific bit to another bit output, at the inputting time of a shift input signal, supplying the same signal to both write input data, and writing the signal selectively. CONSTITUTION:When a shift control input Sc is '1', the bit output Y0 of a memory cell 1, or the bit output Y1 of a memory cell 2, according to the presence/absence of the signal of a shift input S, is outputted to a memory device output Z0. And when the shift control input Sc is '0', the bit outputs Y0 and Y1 of the memory cells 1 and 2 are outputted to memory device outputs Z0 and Z1, respectively. When the shift input Sc is '0', a device is operated as the read/write memory device constituting of four words by two bits, and when the shift in put Sc is '1', it is operated as the read/write memory device constituting of eight words by one bit, and having the memory device output Z0 as the output, by setting the signals of data input D0 and D1 at the same level.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor read/write device.

[Conventional technology]

Conventionally, different memory devices, especially semiconductor memory devices, with the same memory capacity but different memory bit configurations, such as 256 words x 4 bits and 128 words x 8 bits, have been manufactured by manufacturers and supplied to users. was.

[Problem that the invention seeks to solve]

The above-mentioned conventional memory devices have to be manufactured individually for each memory bit configuration, and when manufactured using recent semiconductor integrated circuit technology, they have the disadvantage that they rarely benefit from the manufacturing cost advantages of mass production. have.

Means for Solving Problem C] The read/write memory device of the present invention includes a plurality of memory cells, and has at least first and second bit outputs and a first bit output.
and a second bit input,
A write signal input terminal, a shift input terminal, a shift control input terminal, and a signal input to the shift control input terminal enable the signal input to the shift input terminal, and 1
) "an output logic circuit that shifts the first bit output of the bit outputs to the second bit output, and a signal to the shift control input terminal to enable the signal input to the shift input terminal, and It is characterized by including an input logic circuit that switches a signal to a signal input terminal to a first bit input or a second bit input and outputs the signal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the read/write memory device of the present invention.

This memory device has a configuration of 4 words x 1 bit and has a bit output Y0. Y,, bit input X. , Xl, word input terminals W1-W4, memory device output terminals Z, , Z, and valley memory cell 1.
．． Write data input terminal to 2. , D, write signal input terminal WI:, shift input terminal S, shift control input terminal 7-sc, and signal input to shift control input terminal Sc to enable signal input to shift input terminal S. ,
Bit output Y0. Of Y, bit output Y is bit output Y. An output logic circuit composed of gate circuits IO to 13 that shift the signal to the write signal input terminal W6 to the bit input
. Or gate circuit 3 to switch to bit x 1 and output
and an input logic circuit consisting of 9. Bit output Y of each memory cell 1.2. , YI, shift input S, shift control input Sc and memory device output Z. , the logic with zl is,
Z,=Sc-S-Yo+SC-S-Y.

Z,=Y.

It is indicated by. Table 1 is a truth table shown by this logical formula. When the shift control input SC is "1", the memory device cuff, depending on the presence or absence of the shift input S signal.

The bit output Yo of memory cell 1 and the bit output Y1 of memory cell 2 are output, and the shift control input SC is “0”.
, the bit outputs Y, , Y, of memory cells 1.2, or memory device outputs 2.2, respectively. , 2. is output to.

Table 1 i! ) write signal input WE, shift input S, shift control input Sc and final write input Xo to memory cells 1 and 2,
X+Which logic is shown as x0=(S+Sc)・W): X,=(S+Sc)・W6. Table 1 is the truth table shown by this logical formula.

When the shift control input Sc is "1", the write signal input W, depending on the presence or absence of the shift input S signal: b) The final JP write input X to the memory cells 1 and 2, or x.

When the shift control input is "0", the write signal input WIE is the final write input to memory cells 1 and 2. and x1 at the same time.

Table 2 As described above, when the shift control input SC is 0'', the memory device of this embodiment operates as a read 1 write memory device with a 4 word x 2 bit configuration, and the shift control input SC
When is "1", by making the signals of the data inputs D0 and Dl the same, the device operates as a read/write memory device having an 8 word x 1 bit configuration with the memory device output z0 as its output.

〔Effect of the invention〕

As explained above, the present invention includes a shift input terminal and a shift control input terminal, and when a shift input signal is input,
By shifting the output content of a specific bit to another bit output, giving the same signal to the double-occupation input data, and selectively writing that signal, the bit configuration of the read/write memory device can be changed to the actual use of the semiconductor memory device. In semiconductor memory manufacturing, memory devices with two types of bit configurations can be realized by one type of manufacturing process, which is suitable for mass production and has the effect of reducing manufacturing costs.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the read/write memory device of the present invention. S...Shift input terminal, Sc-...Shift control input terminal, Zo, L...Memory device output terminal, Y,, Y,...
...Memory cell bit output, X,, X, ---Final write input to memory cell, W, ~Stomach, ...Word input terminal, D,, D, ...Write data input terminal, W, −・
・Write signal input terminal.

Claims (1)

[Scope of Claims] A memory device including a plurality of memory cells and having at least first and second bit outputs and first and second bit inputs, comprising: a write signal input terminal, a shift input terminal, and a shift control. an output logic circuit that validates a signal input to the shift input terminal by inputting a signal to an input terminal and the shift control input terminal, and shifts a first bit output of the bit outputs to a second bit output; , an input logic that enables a signal input to the shift input terminal by a signal to the shift control input terminal, switches the signal to the write signal input terminal to a first bit input or a second bit input, and outputs the signal; A semiconductor read/write memory device comprising a circuit.