SU1631715A1 - Logic element - Google Patents

Abstract

The invention relates to the field of electronics and computer technology and can be used in the design of adders and arithmetic units of digital LSIs on CMOS transistors. The purpose of the invention is to increase reliability. The device contains n bits 1.1 -1 .p, each of which has four terminals 6-9 and two inputs 10 and 11, output bus 12 and the third input 15 of the first bit. The introduction of MOS transistors 13 and 14, as well as new design links, has increased the reliability. 1 il.

Description

The invention relates to electronics and computer technology and can be used in the design of adders and arithmetic units of digital LSIs on AHL transistors.

The purpose of the invention is to increase reliability.

The drawing shows a diagram of a logic element.

The circuit contains n bits 1-1 - 1-i, i 1, ...., n, each of which has two p-type MOSFETs 2-3, two n-type MOSFETs 4-5, four output 6 9 and two inputs Yu-i and 11-i, i 1n, and

The first p-type transistor 2 is connected between the first 6 and third 8 pins, the second p-type 3 transistor is connected between the first output 6 and the power line En, the first p-type transistor 4 is connected between the second output 7 and the common bus, the second transistor The n-type 5 is connected between the second 7 and fourth 9 pins of the discharge, the first and second pins of the n-th discharge are connected to the output bus 12

the element, the third and fourth pins of the (i + 1) -th bit are connected respectively to the first and second pins of the i-ro bit (i 1n - 1), between the third pin 8

the first bit and the power bus Ep is connected to the p-type transistor 13, and between the fourth terminal 9 and the common bus is connected to the n-type transistor 14, the gates of transistors 2 and 4 are connected to the first input of the Yu-i discharge, the gates of transistors 3 and 5 are connected with the second input 11-1 bit, the gates of the transistors 13 and 14 are connected to the bus of the third input 15 of the first bit.

The logical element works as follows.

The first inputs of the Yu-i of each of the bits are received respectively by the signals ..... The c-functions of generation of bitwise transfer, the second inputs 11-1 of each of the bits are given respectively PiPn signals - the functions of the distribution of bitwise transfer, to the input 15 The input carry signal, Co. On the bus 12

WITH

WITH

СЬ

with VJ ate

The n-bit device implements the function:

Cn - (-. (P1GO + G1) P2 G2) ... Pn-1 + Gn-1) Pn + Gn)

(D

In particular, for two bits of the device.

C2 {PiCo + Gi) P2 + G2 CiP2 + G2, (2) where Ci PiCo + 61 is the inter-bit transfer from the first bit to the second. The PI and GI functions are formed in the -th bit of an adder or an arithmetic logic unit. For the adder, their formulas are written as

 Pi Ai + Bi, n

Gi A | -Biw

The operation of one bit of the device is determined by the table. Functions:

where AI and 81 are the first bits of the operands supplied to the inputs of the adder or arithmetic unit;

Gi, Pi, Co is the value of the signals supplied to the first, second and third inputs of the first decal of the logic element;

A signal at the output of the first bit of the logic element, obtained by combining the first and second terminals of the first bit.

For example, with input values AI 0, Bi 1, Co 1, the values of PI 1 and Gi-0 are obtained in accordance with formulas (3). The arrival of these control signals at the inputs of the first bit of the device causes the transistors 2, 5

and 14 are in the open state, and the transistors 3, 4 and 13 are in the closed state. As a result, the logic level O is formed at the output 7, and the output 6 goes into the state with high impedance. When connected to one output bus, a logical zero level will be formed on the bus, which corresponds to the value in the selected row of the operation table.

Claims (1)

The invention is a logical element containing n bits, each of which has two MOSFET of p-type and n-type conductance and four terminals; the first p-type transistor is connected between the first and third discharge terminals; the second n-type transistor is connected between the second and fourth discharge terminals; the drain of the second p-type transistor and the first n-type transistors are connected respectively to the first and second discharge terminals, the gates of the first and second p-and n-type transistors are connected respectively, the first and second input buses of the discharge, the third and fourth outputs of each subsequent discharge, beginning with the second, are connected respectively to the first and second outputs of the previous discharge, characterized in that, in order to increase the reliability of the element, two MOS are inserted into it transistors of p- and p-type and new constructive connections, and the sources of the second p-type transistor and the first n-type transistor of each bit are connected respectively to the power bus and the common, first and second terminals of the last bit are connected to the output second bus element, a MOS transistor of p-type connected between the third output of the first discharge and the power supply line, and its gate is connected to the third input bus of the first discharge and the gate of the n-type MOS transistor. connected between the fourth pin of the first Spread and common bus. About FSO 11-1 10-1 11-2 10-2 11-p U-p