JPS62262140A - Microcomputer - Google Patents

Abstract

PURPOSE:To selectively execute different instructions according to the authenticity of conditions of conditional judgement instruction without executing branch instruction by providing a means that suppresses the execution of an instruction following the conditional judgement instruction according to the authenticity of the conditions. CONSTITUTION:A delay circuit 5 connected to two outputs 400 and 410 of an instruction decoder 4 is provided. Clock pulses are supplied from a reference clock generator 1 to the circuit 5, and inputted instruction is held for 1 instruction time and then an instruction prohibition signal is outputted. Accordingly, an instruction code outputted from output 410 of the decoder 4 is returned to the decoder 4 as an instruction prohibition signal through a signal line 500 after 2 instruction execution times. When the instruction is a conditional judgement instruction and the condition is true, a true judgement control signal 400 is outputted, and when the condition is false, a false judgement control signal 410 is outputted.

Description

[Detailed Description of the Invention] 11 ΩB Yoko! The present invention relates to a microcomputer, and more particularly to a novel microcomputer having a function of selectively executing processing following a condition judgment instruction without executing a branch instruction, depending on the truth or falsehood of a condition.

BACKGROUND OF THE INVENTION When a conventional general microcomputer executes a condition judgment instruction, it processes the condition by not executing only one instruction following the condition judgment instruction, depending on whether the condition is true or false. It met the conditions.

Below, a conditional judgment instruction that does not execute the next instruction following the conditional judgment instruction when the condition is false will be specifically explained using an example.

FIG. 2(a) shows condition judgment instructions existing in the program and the following ° instruction group.

In this case, as a result of executing the conditional judgment instruction, if the condition is true, the instruction IO1 instruction 11 follows the conditional judgment instruction.
Instructions 12 are executed in order, and when the condition is false, instruction IO is not executed, and instructions 11. Execute instruction 12.

If such instruction processing is represented in a flowchart, the execution flow will be as shown in Figure 2 (5), and depending on the truth or falsehood of the condition, the result of the condition judgment corresponds only to whether or not to execute the instruction IO. .

Problems to be Solved by the Invention However, as shown in FIG. 3(a), as a result of executing the condition judgment instruction, if the condition is true, instruction 20 is executed; if the condition is false, instruction 10 is executed; After that, it may be necessary to execute the instruction following instruction 11.

If such a process were to be executed by a conventional microcombination system, an extra branch instruction would necessarily need to be executed in the program.

That is, as shown in the program example shown in FIG. 3, a condition judgment instruction is executed, and when the condition is false, branch instruction 1 is not executed, and instructions 10 and 11 are executed in this order. When the condition is true, the program can execute branch instruction 1, move to another address, execute instruction 20, and then return to the original flow of the processing program with branch instruction 2 and execute instruction 11 for the first time. .

That is, if the condition is false, it is necessary to execute the branch instruction twice.

In this way, in conventional microcombiners, processing that requires different operations depending on the output of conditional judgment instructions increases the number of program steps, which not only reduces memory usage efficiency but also reduces the amount of memory used. This led to fragmentation and also made the program list very difficult to read. Furthermore, from the viewpoint of processing execution speed, it goes without saying that an increase in program steps is undesirable.

In addition, in recent years, a queue circuit method, that is, a method that substantially improves the processing execution speed of microcomputers by providing a circuit that preemptively stores a group of instructions to be executed next, has been widely used. ing. however,
Generally, when a branch instruction appears, this method temporarily abandons a group of instructions taken into the queue and empties the queue, which hinders improvement in execution speed in programs where branch instructions frequently appear.

Therefore, the present invention solves the problems of the prior art described above, and makes it possible to execute processing in which different instructions must be selectively executed depending on the result of a conditional judgment instruction, without using a branch instruction. The purpose is to provide microcomputers.

To solve the problem, according to the present invention, a microcomputer is provided with a conditional judgment instruction, and means for inhibiting the execution of one instruction following the conditional judgment instruction depending on the truth or falsehood of the condition; Provided is a microcomputer characterized in that the microcomputer is equipped with means for inhibiting execution of a second instruction following the judgment instruction, and selectively executes the instruction to be executed following the conditional judgment instruction depending on the truth or falsehood of the condition. .

When a microcomputer according to the present invention executes a conditional judgment instruction, it selectively executes two instructions inputted subsequent to the conditional judgment instruction depending on whether the condition is true or false. That is, for example, if a condition is found to be true by executing a conditional judgment instruction, execution of one instruction following the conditional judgment instruction is inhibited, the next instruction is executed, and subsequent instructions are sequentially executed. Also, if the conditional force is false, one instruction following the condition judgment instruction is executed, the execution of the next instruction is inhibited, and the following instructions are executed sequentially.

As described above, the microcomputer according to the present invention can respond to the result of a conditional judgment instruction with different processing without executing a branch instruction, and can eliminate various problems associated with execution of a branch instruction. can.

Hereinafter, the present invention will be described in more detail by citing one preferred embodiment of the present invention. However, what is shown below is only one example of the present invention, and does not exceed the technical scope of the present invention. There is no limit to the number of ships.

FIG. 1 is a block diagram showing the configuration of a microcomputer according to the present invention.

A reference clock generator 1 generates basic clock pulses for the operation of the microprocessor. Program counter 2
generates the address of the instruction that the microprocessor is to execute and outputs an address signal through the address bus 200. Instructions output from a memory connected to the microprocessor are held in an instruction register 3 that holds instructions through a data bus 300. The instruction decoder 4 analyzes instructions and provides operational support to each section within the microprocessor. Such operations are similar in configuration and operation to those of conventional microcomputers.

The microcomputer according to the invention further comprises a delay circuit 5 connected to the two outputs 400 and 410 of the instruction decoder 4. At this time, outputs 400 and 410 of the instruction decoder 4 are configured to selectively output instruction codes depending on whether the condition of the condition judgment instruction is true or false.

Each delay circuit 5 receives a clock pulse from the reference clock generator 1, and is configured to output an instruction execution prohibition signal after holding the input instruction for one instruction time. .

Therefore, the instruction code output from the output 410 of the instruction decoder 4 is returned to the instruction decoder 4 as an instruction execution prohibition signal through the signal line 500 after two instruction execution times.

The command is a condition judgment command, and when the condition is true, a truth judgment control signal 400 is output, and when the condition is false, a false judgment control signal 410 is output.

The truth judgment control signal 400 is passed through the delay circuit 5 and sent to the instruction decoder 4 as an instruction execution prohibition signal 500 after one instruction execution time.
to use human power.

When a condition judgment instruction is manually input to a microcomputer according to the present invention that can perform the above-mentioned configuration 111,
The states of the control signals are shown in FIGS. 4(a) and 4(5).

Figure 4(a) shows the control line 400.410 when the condition is true.
and 511 are shown. That is, since the condition judgment command is executed and the condition is true, the truth judgment control signal 400 is
is output. This signal is delayed by the execution time of one instruction by the delay circuit 5 and is returned to the instruction decoder 4 as an instruction execution prohibition signal. Therefore, following the conditional judgment instruction (instruction 20 is inhibited from execution, instruction 10 is executed following the conditional judgment instruction, and a series of instructions following instruction 11 are executed).

Figure 4 (5) shows the control line 400.410 when the condition is false.
and 500 states are shown. That is, the condition judgment command is executed, and since the condition is false, the false judgment control signal 410 is output. This signal is delayed by two instruction execution times by the two-stage delay circuit 5 and is returned to the instruction decoder 500 as an instruction execution prohibition instruction. Therefore, after the condition judgment instruction is executed, the following instruction 20 is executed, the next following instruction 10 cannot be executed even if it is taken into the instruction register 3, and then the instruction following the instruction 11 is executed.

As described above, when a condition judgment instruction is executed, the microcombination unit according to the present invention selectively executes one of the two instructions following the instruction depending on the truth or falsehood of the condition, and then executes the subsequent instruction. do. At this time, no branch instructions are executed.

Effects of the Invention As detailed above, the microcomputer according to the present invention can selectively execute different instructions depending on the truth or falsehood of the condition of the condition judgment instruction without executing a branch instruction. Therefore, it is possible to avoid many problems that occur when executing conditional branches, such as memory consumption, usage area dispersion, processing speed reduction, and program list complexity.
Substantially, the use of microcomputers can be expanded to be easier and more sophisticated.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a microcomputer according to the present invention, and FIG. An example is shown in FIG. 2(b), which is a flowchart of a process in which a conventional microcomputer selects whether or not to execute a certain instruction based on a conditional judgment instruction, and FIG. 3(a) is a FIG. 3(b) is a flowchart of a process in which a conventional microcomputer selectively executes a different instruction depending on the truth or falsehood of a condition as a result of executing a condition judgment instruction. This shows a program for executing the process, and FIG. 4 shows the operation of the microcomputer according to the present invention shown in FIG. 1 when executing the process shown in FIG. 3(a). FIG. 4(a) shows the state transition of the control signal when the condition of the conditional judgment instruction is true, and FIG. 4(b) shows the state transition of the control signal when the condition of the conditional judgment instruction is false. It indicates a transition. (Main reference numbers) 1.Reference clock generator, 2.Program counter, 3.Instruction register, 4.Instruction decoder, 5.Delay circuit, 100.Instruction clock, 200.Address. Bus, 300...Data bus, 400...True judgment control signal, 410...False judgment control signal, 500...Instruction execution prohibition signal.

Claims (1)

[Claims] A microcomputer equipped with conditional judgment instructions,
A means for inhibiting the execution of one instruction following the condition judgment instruction depending on the truth or falsity of the condition, and a means for suppressing the execution of a second instruction following the condition judgment instruction. A microcomputer is characterized in that it selectively executes instructions that follow one instruction.