JPS62261287A - Double speed reproducing circuit - Google Patents

Abstract

PURPOSE:To attain the double speed reproduction in which a horizontal synchronizing period is constant and a noise bar does not exist by storing a reproducing video signal without the noise bar into a field memory with a horizontal synchronizing signal as a counting input while a sub-head is reproduced and scanned. CONSTITUTION:A field memory 9 executes alternately a storing and a reading at the time of the double speed reproduction. A reading address executes the reading in the sequence of the memory information of the field memory 9 until an RF switching pulse is supplied. The output of both reading counters 21 and 22 is inputted to the first changing-over circuit 23 and alternately selected by a changing-over clock. Since the second writing counter 15 is reset by a vertical pulse and the reading counter 22 is reset by the RF switching pulse, a vertical synchronizing signal is read by the head output changing-over timing of the reproducing video signal. Thus, a reproducing picture is changed over at a frame period, a switching area is formed in the sequence of the time series from the top and an easy-to-see double speed reproducing picture is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Application in Childcare The present invention relates to a double-speed playback circuit for use in field memo 'Jt-1f in a video tape recorder in which a sub-field is placed close to one end only.

(b) Conventional technology A video tape recorder has a secondary head with an azimuth metal fitting close to the main head for double-speed playback. It is disclosed on pages 31-36 of the monthly issue.

In this prior art, the larger one of a pair of lid outputs that are simultaneously being scanned for reproduction is selected to form the entire double-speed reproduction screen without noise bars.

No. f Problems to be Solved by the Invention However, in the case of the conventional example described above, if the horizontal synchronizing signals are not correctly aligned in the six directions of the recording track, skew will occur on the reproduced screen. However, only one side can be used as a vice, but V
Noise bars cannot be eliminated even if this conventional technology is adopted for TR.

Therefore, in order to eliminate skew distortion and noise bars in a 6-head VTR, the present invention provides a method for inputting all counts of the reproduced horizontal synchronizing signal and setting the reproduced vertical synchronizing signal k IJ upper set force. a write address generation circuit that generates a write address signal as a write address signal; a read address generation circuit that uses a stable oscillation output as a counting input and a head switching signal as a reset input to generate a read address signal; a field memory that stores the reproduced video signal and reads out the reproduced video signal based on the successive address signals; and a write/read control that allows writing to the field memory only during the reproduction period of the sub-head. Therefore, according to the present invention, during writing, a reproduced video signal with no noise bar is generated during the period when the sub head performs reproduction scanning. The horizontal synchronization signal is stored in the field memory as a counting input, and the contents of the field memory are read out twice in sequence, making double-speed playback possible with a constant horizontal synchronization period and no noise bars. f) Example The present invention will be described below with reference to an illustrative example.

In this embodiment, there are 11 heads (Ml) for the first main head (Ml).
S) t-closely placed. The first main head (Ml)
The sub heads (S) and the sub heads (S) have different azimuths, and are separated by a total distance of 1H (370 μm), so that the entire scanning trace is almost the same. Therefore, the changes in the reproduction output levels of both heads have a complementary relationship. Figure 2 shows changes in the playback output level during 5x playback, and shows the playback output (solid line) of the first main head (Ml) and the sub head (S) in the first field.
) are obtained.

Therefore, as shown in Fig. 1, the first main head (Ml)
The reproduction outputs of the and sub-heads (S) are input to the first switching circuit +31, and are also input to the first and second detection circuits 12+ for envelope detection. Both detection outputs are input to the comparison circuit (41, and the comparison output is input to the first
It is used as a control input for the switching circuit 13. The second switching circuit (51 is input to the first switching output and the playback output of the @2 main head (M2) is connected to the second switching circuit (51) for RF switch, soching pulse, 1
i (used as a control input, and also outputs the first switching output during the low level period)・Second main head (M
2) are alternately selected and a continuous signal is supplied to the video processing circuit (6). This video processing circuit performs FM demodulation of the high-frequency components of the playback output using a well-known method. By converting the low frequency components to high frequency, NTSC
After forming a color video signal, it undergoes high frequency conversion and full demodulation of the modulated color signal to form an RY signal and a BY signal, which are derived together with a luminance signal (Y signal). These three signals are input to a multiplexer (71). This multiplexer 14 divides the Y component, R-Y component, and B-
All Y components are time-divisionally selected at a ratio of 4:1:1, and the selected outputs are converted into digital signals in the AD conversion circuit +8+. This digital signal is stored in the field memo 91 according to the write address signal. In this field memo, January 91, storage and reading are performed alternately during double-speed playback, and reading is performed while writing.

This is done in synchronization with the reproduction horizontal synchronization signal and the reproduction vertical synchronization signal when forming the write address signal. ) Therefore, the reproduced horizontal synchronizing signal is input to the horizontal pulse generating circuit σ11 to generate the reproduced horizontal pulse (HP), and the reproduced vertical synchronizing signal is input to the vertical pulse generating circuit '1z to generate the reproduced horizontal pulse (HP).
vp )i respectively. Both pulses (HP) (
VP) n, A fsc derived by the clock generation circuit σ
(fsc is the color subcarrier frequency) is used as a reset input for the 18-inclusive counter (2), which is used as a counting input for the clock pulse (CK) i. The count value of this first @include counter 011 indicates the address corresponding to the horizontal position on the screen.Horizontal pulse (HP)? Second write counter (+511C1 vertical pulse (VP) r
The count value of the second write counter 2, which is input as +J set, indicates all the addresses corresponding to the vertical position on the screen. Furthermore, when the first write counter reaches 0, counting is completely interrupted until it is reset after counting up, thereby preventing double writing. Therefore, the first write counter (14JI''!)
The horizontal address is specified by the above-mentioned section 2 write counter a9, and the vertical direction address is specified respectively.
+41 (151 output) is alternately selected by the switching clock (SL) which is input to the second switching circuit field and corresponds to twice the clock pulse frequency ARSC, and is input to the address selection circuit side as a write address signal. (See Figure 3) On the other hand, the write/read control circuit 9 receives all the input pulses (CK) and RF' switching pulses.
OR output of both inputs As a total control output, this control output cover of the field memory (inputted to 91 and address selection circuit 1181) is at low level, the field memory +91'! r Set the write state and selectively supply the write address signal to the field memory 91, and set the field memo 91 to the continuous state when the /% blank level is reached, and send the read address signal to the field memory ( 9) Selectively supply. 1
Therefore, when the field memory iRF switching pulse is at a low level, writing and reading are performed alternately, and when it is at a high level, only reading is performed.

On the other hand, the master clock and RF
The master clock generated by the switching pulse is divided in the clock generation circuit (171) and converted into a switching clock (SL) and a clock pulse (CK), as well as a horizontal synchronization/curse generation circuit. It is frequency-divided and converted into horizontal synchronization pulse (HP) for horizontal synchronization.All read addresses in the horizontal direction are specified as the first read counter 12DI'XRF sweep pulse and horizontal synchronization pulse (HP) i reset input. In addition, the second read counter uses the PIF switching pulse as a reset input to count the horizontal synchronizing pulse (HP) and specifies the vertical address.Therefore, the read address is the RF switching pulse. Field Memo January 9+ until supplied
The stored information is read out in order. Both read counters [211a
The output of z is input to the first switching circuit and the switching clock (S
L) are alternately selected. The selected read address signal is input to the address selection circuit 08+, and is input to the field memo 91 alternately with the write address signal. Therefore, the second write counter (1) is reset by the vertical pulse (vp), and the read counter Qz
Since the vertical synchronization signal is shifted by the FtF switching pulse, the vertical synchronization signal is read out at the head output switching timing of the reproduced video signal.
After converting into analog, it is input to the diplexer (IB) and transmitted separately into Y component, R-Y component and 8-Y component. In the circuit following each derived component, the original The original color video signal is derived by converting it to a color video signal and reinserting the synchronization.

In the above-mentioned embodiment, the vertical pulses and horizontal pulses obtained by the reproducing scan of the second main head (M2) are used as the counting inputs of both write counters 141α9, but when there is a lot of noise, the high level of the iRF switching pulse It goes without saying that counting of the write counter may be prohibited during level E. According to the present invention, the playback screen can be switched at frame intervals, and the switching area can be It will be formed in chronological order from

[Brief explanation of drawings]

Figure 1a is a circuit block diagram of an embodiment of the present invention, Figure 2i
An explanatory diagram showing the relationship between the RF switching pulse and the reproduction output level, and an explanatory diagram showing the relationship between the clock pulse and the switching clock are shown in FIG. 3, respectively) +9+...Field memory,! 21112'a...
・First ・Second read counter, q4I (151...First and second write counter, (Ml)(M2)...Shoulder 1・
2nd main head, (S)...Vice head 0

Claims (1)

[Claims] (1) In a video tape recorder in which a sub-head is placed close to only one of a pair of main heads, and the playback output with the higher level is selected between the playback output of the sub-head and the playback output of the main head, and double-speed playback is performed. , a write address generation circuit that uses the reproduced horizontal synchronization signal as a counting input and the reproduced vertical synchronization signal as a reset input to form a write address signal, and a stable oscillation output as a counting input and a head switching signal as a reset input to generate a read address signal. a field memory that stores the reproduced video signal based on the write address signal and reads out the stored reproduced video signal based on the read address signal; and a field memory that reads the stored reproduced video signal based on the read address signal; and a write/read control circuit that allows writing to the field memory only during the period.