JPS62261278A - Parallel interface circuit for printer - Google Patents

Abstract

PURPOSE:To attain the highly speedy execution by executing the binary processing by a dither method to image data having gradation with a hardware. CONSTITUTION:In order to handle gradation data, a CPU to control an interface part, first, sets an output A of a parallel input output IC12 to an H level. Thus, a three-state buffer 20 prohibits the input of character data and simultaneously, the input of 1 Bit data by a signal line 4 is permitted. When the data with the gradation are inputted to an 8-bit parallel data input port 1, the high order 4-bit appears at the R port of a magnitude comparator 15. By a strobe signal 16 to show the data input, one of the data of a ROM 10 is selected, inputted to the Q port of the magnitude comparator 15, and by the comparing with a P port, a binary output 4 can be obtained.

Description

[Detailed Description of the Invention] [Industrial Application Field] The great invention is that when image data expressed in gradation is input to a dot matrix printer, binarization processing is performed using a dither method in an automatic calculation. This relates to a parallel input circuit that generates and processes data.

[Conventional technology]

The conventional parallel interface for printers is 8bi.
It was devised for the purpose of receiving coded data that can be expressed as t and @. This interface makes no distinction whether the received data is character data or numeric data. Therefore, data with standard gradation is input as mere numerical data, and there is a lack of a method for handling the received data on the printer side. For this reason, it has been necessary for printers to process data in terms of software and hardware so that it is suitable for gradation processing depending on the printer's mechanism. Particularly for dot matrix printers that cannot express gradation based on the size of the dot diameter, binarization processing of image data with gradation is essential, but conventional hardware methods are expensive, and software methods are The drawback is that it requires a lot of processing time.

[Problem that the invention seeks to solve]

According to the present invention, when image data with gradation is input, it is binarized by the hardware of the interface circuit section, and the data is expressed in dot gradation without reducing the processing speed of the CPU for controlling the printer. The purpose of the present invention is to enable gradation expression even in dot matrix printers that cannot do so.

[Defined means of solving problems]

The interface circuit, which is a great invention, consists of a parallel input part, a data latch, a ROM, and a magnitude comparator. The 8 h 1 t@ data transferred from the host computer is judged by the printer side OPO as to whether it should be handled as character data or gradation data, and if handling as gradation data is specified, it is stored in the ROM. It is characterized in that it is treated as binarized data by comparing it with each element of the converted dither matrix.

Further, in the case of a color printer that handles multicolor data, a feature is that a different threshold value and a different dither matrix can be selected for each color.

[Effect]

The great invention is to binarize parallel 8-bit data with gradation and then apply it to the input XO. Several methods of this binarization are known, but the great invention is to perform binarization using a systematic dither method. If the systematic dithering method is realized and fc then Vc
If a method is implemented in which the dither matrix is applied by shifting it along the period of one foot in order to suppress the occurrence of a striped pattern with a certain percentage, each threshold value of the dither matrix will appear periodically. A binarized output is obtained by successively comparing this periodic value with the input data with gradation. In order to implement this, the present invention uses FIO
FIOM sequencer with M and latch, and magnitude comparator are used.

〔Example〕

W, Figure 1 is an embodiment of the present invention. 1 is an 8-bit parallel input signal line, and 2 is a strobe signal input indicating that data is fixed at 1.

8 indicates that the CPN that controls the water circuit is working.
f''B is the SY signal. 18 is a signal that is output by hardware in response to the rise of the negative logic strobe input 2, and 19 is a signal that is output in the progress state of the apt+ software. 9 is a signal from which the Kiguchi W8 side requests the host computer executing the data transfer to transfer the next data. 13 is a signal indicating an error during execution. 14 is a signal from the printer side to the post computer. 17 is a signal that initializes the circuit state.Signal @1, 2, 8, 9, 13゜44.171d Conventional 8-bit parallel interface for printers and Signal 3 is used to control whether the data handled by the interface section is character data or gradation data.

FIG. 2 shows an example of a dither pattern that is possible on the Kinomi style side. The threshold value of the dither pattern shown in FIG. 2 has periodicity, and one period thereof is as shown in Table 1.

In order to correspond to D7 to T)4 of the ROM 10, the numerical values in Table 1 are set as N, and the numerical values as a result of performing the operation of (N-1)X16 are shown in Table 2. As shown in Table 1, the 6th and 1st
Since the same numerical value appears in the 7th position, we simply distinguish them by 0 and 1 on Roylo's T13 line. The values in Table 2 are R
Table 3 shows the correspondence between addresses and data for implementation on OM.

Table 1 Table 2 Table 3 & describes the operation of this embodiment. The CPU that controls this interface section is first set to the output ht-m level of the parallel input/output crab C12 for handling gradation data. As a result, the three-state buffer 20 prohibits the input of character data 7, and at the same time, the signal line 4
Data entry is permitted.

When gradation data is input to the 8-bit parallel data input port 1, its upper 4 bits appear at the R port of the magnitude comparator 15. - One of the data in the ROM 10 is selected by the strobe signal 16 indicating sword data input, and is input to the Q port of the magnitude comparator 15, and by comparison with the P boat,
Binarized output 4 is obtained.

The output of the nine-step, 8-bit latch 11, which receives the strobe signal 16, will point to the address where the next dither data to be compared is stored.

RO by output ports 5, 6.7 of parallel input/output IC12
Access eight different address areas on M. This allows different dither matrices to be set for eight food types.

〔Effect of the invention〕

This circuit can perform faster execution than conventional software processing, which does not perform binarization processing using the dither method on gradation image data using hardware.

By selecting the R and 0M areas to be used, it is possible to use a different dither pattern for each color or for each print mode, and unlike the software method, there is no time difference in the processing.

As is clear from FIG. 11, by training the magnitude comparator 1.5, the free interval for the number of +1 is high in the gradation that can be processed, and the circuit configuration is easy.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram implementing one embodiment of the present invention. FIG. 2 is a dither matrix diagram showing one example of a dither pattern that can be implemented according to the present invention. -1 is a strobe signal indicating that abtt parallel input parallel line input data has been determined, 3 is a selection signal for character parallel input and image data input, 4
is binary output, 5.6, 7 is dither pattern selection, 8 is BU8Y signal, 9 is negative logic ACK, IQ is dither pattern ROM, 11 is data latch, 12 is parallel input/output IC
, 13 is the negative logic error signal, 14 is the paper out output signal, 1
s74sbtt mag 2000 need comparator, 16 is a dither pattern update signal, 17 is a dither pattern initialization signal, 18.19 is a BUSY signal, and 20 input switching three-state buffers. that's all

Claims (1)

[Claims] A parallel interface circuit for a printer, characterized in that a ROM, a latch, and a magnitude comparator are used in an 8-bit parallel input line, and a gradation expression circuit using a dither method is added.