JPS62261157A - Package for semiconductor device - Google Patents

Package for semiconductor device

Info

Publication number
JPS62261157A
JPS62261157A JP61105362A JP10536286A JPS62261157A JP S62261157 A JPS62261157 A JP S62261157A JP 61105362 A JP61105362 A JP 61105362A JP 10536286 A JP10536286 A JP 10536286A JP S62261157 A JPS62261157 A JP S62261157A
Authority
JP
Japan
Prior art keywords
point glass
low
sealing
melting
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61105362A
Other languages
Japanese (ja)
Inventor
Hitoshi Yokoyama
横山　均
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61105362A priority Critical patent/JPS62261157A/en
Publication of JPS62261157A publication Critical patent/JPS62261157A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/163—Connection portion, e.g. seal

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)

Abstract

PURPOSE:To prevent poor sealing, by chamfering the outer surface of a cap part or a base part on the side of one or both sealing parts. CONSTITUTION:The outer surface of a base part 2a on the side of a sealing part is chamfered. A cap part 4 is sealed with low-melting point glass 5a. The low-melting-point glass 5a spreads along the chamfered part. Therefore, even if the same amount of the low-melting-point glass as in the case the chamfering is not performed is used, the low-melting-point glass 5a does not protrude to the outside of a package. The bonding area between the low-melting- point glass 5a and the base part 2a is larger than the area, where the chamfering is not performed. Thus the sealing strength is rather improved.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 不発Ｌ！Ａは半導体表置用パッケージに関し、特に低融
点ガラスにより刺止する半導体装置用パッケージの形状
に胸する。[Detailed description of the invention] [Industrial application field] Misfire L! A relates to packages for mounting semiconductors, and is particularly concerned with the shape of packages for semiconductor devices that are pierced with low-melting glass.

し従来の技俯〕 従来、この種の半導体装置用パッケージは、第２図に示
す様に、半導体ダイｌをベース部２にマクントし、これ
ら半導体ダイ１とベース部２との間ｅホンディングワイ
ヤ３によりボンディングした後に、キャップ部４ｔ−低
融点ガラス５で接着していた。[Conventional Techniques] Conventionally, this type of semiconductor device package, as shown in FIG. After bonding with the wire 3, the cap portion 4t was bonded with the low melting point glass 5.

〔発明が解犬しようとする問題点〕[Problems that the invention attempts to solve]

上述した従来の半導体装置用パッケージは、刺止強度が
低融点カラスの量に依存し、低融点ガラスの倉が少ない
と封止強度が低くなる。−万、刺止強度を上げるために
低融点カラス量を多くすると、低融点ｊｊシスか第２図
に示す様にパッケージの外側にｔよ不出してしｌい、半
導体装置の選別工程中、特にオートへ／トノ−で選別全
行なう時などに、半導体装置用パッケージ外には不出し
た低融点カラスにｍ依胃撃が加わり、低融点カラスにク
ンツクが入り、封止不良になり易いといり欠点がある。In the conventional semiconductor device package described above, the puncture strength depends on the amount of low-melting glass, and the sealing strength decreases when there is a small amount of low-melting glass. - If the amount of low-melting point glass is increased to increase the puncture strength, the low-melting point glass will not stick out to the outside of the package as shown in Figure 2, and during the selection process of semiconductor devices, In particular, when all sorting is done automatically or with a tonneau, the low melting point glass that has not left the semiconductor device package is subject to stomach shock, and the low melting point glass is likely to get stuck, resulting in poor sealing. There are some drawbacks.

本発明の目的は、このような従来の欠点を除き、低融点
カンスによる封止時にのにみ出しがなく、封止不良をな
くすようにした半導体装置用パッケージ？ｉ−提供する
ことにある。It is an object of the present invention to provide a package for a semiconductor device that eliminates such conventional drawbacks, eliminates leakage during sealing with a low melting point can, and eliminates sealing defects. i- To provide.

〔問題点ｔ）ｌ＃決するための手段〕[Problem t) l# Means to resolve]

本発明の半導体装置用パッケージのｆＩｌ底は、半導体
素子を実装したベース部とこのベース部を覆うキャップ
部とを低融点ガラスにより封止する半導体装置用パッケ
ージにおいて、前記キャップ部あるいは前記ベース部の
一方またはこれらキャップ部とベース部の両方の封止部
分側の外周が面取りされたことを特徴とする。The fl bottom of the semiconductor device package of the present invention is a semiconductor device package in which a base portion on which a semiconductor element is mounted and a cap portion covering the base portion are sealed with low melting glass. It is characterized in that the outer periphery of one or both of the cap part and the base part on the side of the sealing part is chamfered.

〔実施例〕〔Example〕

次に本発明について図Ｉｆｉを参照して説明する。 Next, the present invention will be explained with reference to FIG. Ifi.

第１図（ａ）〜（ｄ）は本発明の４つの実施例の断面図
である。ます、第１図（ａ）においては、ベース部２ａ
の封止部側の外周を面取りして、キャップ部４を低融点
カラス５ａで封止している。この低融点ガラス５８は而
取りをした部分に沿って広がるため、面取りをしていな
い場合と同じ童の低融点ガラスを用いても、封止後に低
融点ガラス５ａがパッケージの外側にμはみ出δ丁、ま
た、低融点ガラス５ａとベース部２ａの接着面積は面取
シをしていないものより大きくなっているために封止強
度はむしろ向上する。FIGS. 1(a) to 1(d) are cross-sectional views of four embodiments of the present invention. In FIG. 1(a), the base portion 2a
The outer periphery of the sealing part side is chamfered, and the cap part 4 is sealed with a low melting point glass 5a. Since this low melting point glass 58 spreads along the chamfered part, even if the same low melting point glass as in the case where no chamfering is used, the low melting point glass 5a protrudes μ to the outside of the package after sealing. Moreover, since the bonding area between the low melting point glass 5a and the base portion 2a is larger than that without chamfering, the sealing strength is rather improved.

第１図（ｂ）は本発明の第２の実施例の断面図で、ベー
ス部２ｂの而取りの形状ｔ＃ｔＸするように変えて低融
点ガラス５ｂと接着したもので、同様の効果が得られる
。FIG. 1(b) is a cross-sectional view of a second embodiment of the present invention, in which the shape of the base portion 2b is changed to t#tX and the base portion 2b is bonded to a low melting point glass 5b, and the same effect can be obtained. can get.

第１図（Ｃ）、第１図（ｄ）は本発明の第３　、ｆＪＩ
Ｊ４の実施例の断面図である。面取りをキャップＮ４ａ
ｔ４ｂおよびベース部２ｃ、２ｄの両方共行って低融点
ガラス５ｃ、５ｄと接着したもので、これらの場合は効
果が更に増大する。FIG. 1(C) and FIG. 1(d) are the third embodiment of the present invention, fJI
It is a sectional view of the example of J4. Cap chamfer N4a
Both t4b and base portions 2c and 2d are bonded to low melting point glasses 5c and 5d, and in these cases the effect is further enhanced.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明は、キャップ部か、ベース
部または、キャップ部、ベース部両方の封止部側の外周
を面取りすることによシ、封止に用いる低融点ガラスが
半導体装置用パッケージの外側にはみ出ず、低融点ガラ
スに直接衝撃が加わることを防ぎ、かつ封止強度を向上
するという効果がある。As explained above, the present invention has the advantage that by chamfering the outer periphery of the cap portion, the base portion, or both the cap portion and the base portion on the side of the sealing portion, the low melting point glass used for sealing can be used for semiconductor devices. It does not protrude outside the package, prevents direct impact from being applied to the low melting point glass, and has the effect of improving sealing strength.

【図面の簡単な説明】[Brief explanation of drawings]

第１図（ａ）〜（ｄＪは本発明の４つの実施例を示す半
導体装置用パッケージの断面図、第２図μ従来の半導体
装置用パッケージの断面図である。 １・・・・・・半導体ダイ、２．２ａ〜２ｄ・・・・・
・ベース部、３・・・・・・ボンディングワイヤ、４，
４ａ、４ｂ・・・・・・キャップ部、５．５ａ〜５ｄ・
・・・・・を融点ガラス。 代理人　弁理士　　内　原　　　”パ 目。 午／　＠　（Ｃ）　　　牛ｌ盟（（１）へ′−ス遮） 尋　２　図FIGS. 1(a) to dJ are cross-sectional views of semiconductor device packages showing four embodiments of the present invention, and FIG. 2 μ is a cross-sectional view of a conventional semiconductor device package. 1... Semiconductor die, 2.2a to 2d...
・Base part, 3...Bonding wire, 4,
4a, 4b... Cap part, 5.5a to 5d.
...is a melting point glass. Agent Patent Attorney Uchihara ``Pame.　＠＠＠＠＠＠＠＠＠＠＠＠＠（C）

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を実装したベース部とこのベース部を覆うキ
ャップ部とを低融点ガラスにより封止する半導体装置用
パッケージにおいて、前記キャップ部あるいは前記ベー
ス部の一方またはこれらキャップ部とベース部の両方の
封止部分側の外周が面取りされたことを特徴とする半導
体装置用パッケージ。In a semiconductor device package in which a base portion on which a semiconductor element is mounted and a cap portion covering the base portion are sealed with low-melting glass, one of the cap portion, the base portion, or both the cap portion and the base portion may be sealed. A semiconductor device package characterized by having a chamfered outer periphery on the stop portion side.
JP61105362A 1986-05-07 1986-05-07 Package for semiconductor device Pending JPS62261157A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61105362A JPS62261157A (en) 1986-05-07 1986-05-07 Package for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61105362A JPS62261157A (en) 1986-05-07 1986-05-07 Package for semiconductor device

Publications (1)

Publication Number Publication Date
JPS62261157A true JPS62261157A (en) 1987-11-13

Family

ID=14405615

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61105362A Pending JPS62261157A (en) 1986-05-07 1986-05-07 Package for semiconductor device

Country Status (1)

Country Link
JP (1) JPS62261157A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614329A1 (en) * 1993-03-05 1994-09-07 Thomson-Csf Method for hermically sealing an enclosure particularly with microelectronic circuits and enclosure thus obtained
JP2000058692A (en) * 1998-08-14 2000-02-25 Toyo Commun Equip Co Ltd Package for electronic components
JP2022025834A (en) * 2020-07-30 2022-02-10 日本特殊陶業株式会社 Semiconductor package and semiconductor package manufacturing method

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0614329A1 (en) * 1993-03-05 1994-09-07 Thomson-Csf Method for hermically sealing an enclosure particularly with microelectronic circuits and enclosure thus obtained
FR2702329A1 (en) * 1993-03-05 1994-09-09 Thomson Csf A method of hermetically sealing an enclosure, in particular an enclosure containing microelectronic circuits, and an enclosure thus obtained.
JP2000058692A (en) * 1998-08-14 2000-02-25 Toyo Commun Equip Co Ltd Package for electronic components
JP2022025834A (en) * 2020-07-30 2022-02-10 日本特殊陶業株式会社 Semiconductor package and semiconductor package manufacturing method

Similar Documents

Publication Publication Date Title
KR950021296A (en) Chip Carrier Semiconductor Device Assembly and Formation Method
JPS62261157A (en) Package for semiconductor device
JPS62142341A (en) Semiconductor device and manufacture thereof
JPS5917271A (en) Ceramic package semiconductor device
US6137160A (en) Lead frame for semiconductor devices
JPS63151053A (en) Semiconductor device
JPH0348446A (en) Semiconductor device
JPH0366152A (en) Semiconductor integrated circuit module
JPS638135Y2 (en)
JPS6079749A (en) Semiconductor device
EP1381084A1 (en) Semiconductor device and method of its fabrication
JPS60130851A (en) Resin seal type semiconductor device
JPS6040704B2 (en) Semiconductor device package
JPH0238831A (en) Stem for semiconductor
JPS6056297B2 (en) Airtight mounting structure for integrated circuit elements
JPH024510Y2 (en)
JPS614251A (en) Semiconductor package
JPH04121767U (en) semiconductor laser equipment
JPH0331083Y2 (en)
JPH036050A (en) Lead frame
JPH02257667A (en) Die pad for lead frame
JPS6035540A (en) Semiconductor device
JPH033354A (en) Semiconductor device
JPS624857B2 (en)
JPH01123442A (en) Ceramic package for semiconductor device