JPS62261142A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS62261142A
JPS62261142A JP10386986A JP10386986A JPS62261142A JP S62261142 A JPS62261142 A JP S62261142A JP 10386986 A JP10386986 A JP 10386986A JP 10386986 A JP10386986 A JP 10386986A JP S62261142 A JPS62261142 A JP S62261142A
Authority
JP
Japan
Prior art keywords
silicon nitride
silicon
nitride film
film
frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10386986A
Other languages
Japanese (ja)
Inventor
Hiroyuki Okada
裕幸 岡田
Isao Murakami
村上 勇雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP10386986A priority Critical patent/JPS62261142A/en
Publication of JPS62261142A publication Critical patent/JPS62261142A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent the yield of roughness in a silicon substrate in a process for removing a silicon nitride film, by isolating the frame of the silicon nitride and the silicon substrate by an silicon oxide film, which intrudes into a part beneath the frame of the silicon nitride film. CONSTITUTION:On the surface of a silicon substrate 1, a protecting silicon oxide film 2 and a first silicon nitride film 3 are sequentially laminated. Then a hole 4 for isolating an element region is formed. On the bottom and side surfaces of the hole 4 and the entire surface of the first silicon nitride film 3, a second silicon film 5 is formed. Thereafter, the second silicon nitride film 5 at the bottom surface of the hole 4 is removed. Then, a isolating silicon nitride film 6 is formed on the silicon substrate 1, which is exposed at the bottom surface of the hole 4. Thereafter, the first and second silicon nitride films 3 and 5 are removed. A frame 7 of the silicon nitride film is made to remain around the hole 4. At this time, the final point of plasma etching is detected by the change in intensity of the nitrogen spectrum. Then, a silicon oxide film is added on the entire surface of the silicon substrate by thermal oxidation. An isolating thermal silicon oxide film 8 is made to intrude into a part beneath the frame 7 of the silicon nitride film. Thereafter the frame of the silicon nitride film is removed.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は半導体装置の製造方法に関し、特に素子分離領
域を有する半導体装置の製造方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device having an element isolation region.

(従来の技術) 従来、半導体集積回路装置、特に、MO3型LSIの製
造工程には、i子分離技術としてLOCO8法が用いら
れている。しかしながら、通常のLOCO8法では、熱
酸化時に素子領域に分離用酸化膜の尖端が素子領域に侵
入し、素子領域が狭くなるという間層があった。この対
策として素子領域の周りに窒化シリコン膜の枠を形成す
ることによって分離用酸化膜の侵入を押える改良LOC
OS法が提案されている。
(Prior Art) Conventionally, the LOCO8 method has been used as an i-element isolation technique in the manufacturing process of semiconductor integrated circuit devices, particularly MO3 type LSIs. However, in the normal LOCO8 method, there is an interlayer in which the tip of the isolation oxide film invades the element region during thermal oxidation, resulting in the element region becoming narrower. As a countermeasure to this problem, improved LOC prevents the intrusion of the isolation oxide film by forming a frame of silicon nitride film around the element area.
The OS method has been proposed.

この改良LOCO8法について、第2図(a)ないしく
c)に示す工程断面図により説明する。第2図(a)に
示すように、まず、シリコン基板1の表面に保護用酸化
シリコン膜2と第1窒化シリコン膜3とを順次積層した
後、素子領域を分離する開孔4を形成し、さらに開孔4
の底面および側面と上記の第1窒化シリコン膜3の全面
に第2窒化シリコン膜5を形成した後、開孔4の底面の
第2窒化シリコン膜5を除去する。
This improved LOCO8 method will be explained with reference to process cross-sectional views shown in FIGS. 2(a) to 2(c). As shown in FIG. 2(a), first, a protective silicon oxide film 2 and a first silicon nitride film 3 are sequentially laminated on the surface of a silicon substrate 1, and then an opening 4 is formed to separate the device regions. , and further aperture 4
After forming the second silicon nitride film 5 on the bottom and side surfaces of the opening 4 and the entire surface of the first silicon nitride film 3, the second silicon nitride film 5 on the bottom of the opening 4 is removed.

次に、第2図(b)に示すように、熱酸化によって開孔
4に露呈したシリコン基板1に分離用酸化シリコン膜6
を形成する。
Next, as shown in FIG. 2(b), a silicon oxide film 6 for isolation is applied to the silicon substrate 1 exposed in the opening 4 by thermal oxidation.
form.

次に、第2図(c)に示すように、第1および第2窒化
シリコン膜3および5を除去する。
Next, as shown in FIG. 2(c), the first and second silicon nitride films 3 and 5 are removed.

(発明が解決しようとする問題点) しかしながら、上述のような改良LOCO3法では、第
2図(b)に示すように素子領域の枠部で第2窒化シリ
コン膜5がシリコン基板1に接しているため1分離用酸
化シリコン膜6を形成した後、第1および第2窒化シリ
コン膜3および5を除去する際に熱燐酸溶液エツチング
あるいはプラズマエツチングの何れの方法を用いてもシ
リコン基板1に荒れが生じ、素子に悪影響を与えるとい
う問題があった。
(Problems to be Solved by the Invention) However, in the improved LOCO3 method as described above, the second silicon nitride film 5 is in contact with the silicon substrate 1 in the frame of the element region, as shown in FIG. Therefore, after forming the silicon oxide film 6 for isolation, when removing the first and second silicon nitride films 3 and 5, whether hot phosphoric acid solution etching or plasma etching is used, the silicon substrate 1 will be roughened. There was a problem in that this caused a negative effect on the device.

本発明は上記の問題点を解決するもので、窒化シリコン
膜を除去する際にシリコン基板に荒れが発生しない半導
体装置の製造方法を提供するものである。
The present invention solves the above problems and provides a method for manufacturing a semiconductor device in which a silicon substrate is not roughened when a silicon nitride film is removed.

(問題点を解決するための手段) 上記の問題点を解決するために1本発明は、分離用酸化
シリコン膜を形成した後、第1および第2窒化シリコン
膜をプラズマエツチングにより除去する際に、窒素スペ
クトルの強度変化によって終点を検出して、素子領域の
周りに窒化シリコン膜の枠を残す。これは上記の窒素ス
ペクトルの強度変化によって高い精度で制御することが
できる。
(Means for Solving the Problems) In order to solve the above problems, one aspect of the present invention is to remove the first and second silicon nitride films by plasma etching after forming the isolation silicon oxide film. , the end point is detected by the intensity change of the nitrogen spectrum, and a frame of silicon nitride film is left around the device region. This can be controlled with high precision by changing the intensity of the nitrogen spectrum described above.

次に、熱酸化によってシリコン基板全面に厚さ500人
ないし2000人の酸化シリコン膜を追加形成し、窒化
シリコン膜の枠の下に保護用および分離用酸化シリコン
膜の尖端を侵入させることによって、窒化シリコン膜の
枠とシリコン基板の間に酸化シリコン膜を形成する。さ
らに、残った窒化シリコン膜の枠を除去する。
Next, a silicon oxide film with a thickness of 500 to 2000 thick is additionally formed on the entire surface of the silicon substrate by thermal oxidation, and the tip of the protective and isolation silicon oxide film is penetrated under the frame of the silicon nitride film. A silicon oxide film is formed between the silicon nitride film frame and the silicon substrate. Furthermore, the remaining silicon nitride film frame is removed.

(作 用) 上記の構成により、窒化シリコン膜の枠の下に侵入する
酸化シリコン膜によって、窒化シリコン膜の枠とシリコ
ン基板は隔離されるので、窒化シリコン膜を除去する工
程でシリコン基板の荒れが発生しない。また、分離用酸
化シリコン膜の尖端の侵入は、窒化シリコン膜の枠の下
に限られるので、素子領域の面積もあまり小さくならず
、またシリコン基板に与えるストレスも殆んど無視でき
る。
(Function) With the above configuration, the frame of the silicon nitride film and the silicon substrate are isolated by the silicon oxide film that penetrates under the frame of the silicon nitride film, so that the silicon substrate is not roughened during the process of removing the silicon nitride film. does not occur. Furthermore, since the tip of the isolation silicon oxide film can only penetrate under the frame of the silicon nitride film, the area of the element region does not become too small, and the stress applied to the silicon substrate can be almost ignored.

(実施例) 本発明の一実施例を第1図(a)ないしくe)により説
明する。
(Example) An example of the present invention will be described with reference to FIGS. 1(a) to e).

第1図(a)に示すように、まず、シリコン基板1の表
面に保護用酸化シリコン膜2と第1窒化シリコン膜3と
を順次積層した後、素子領域を分離する開孔4を形成し
、さらに開孔4の底面および側面と上記の第1窒化シリ
コン膜3の全面に第2窒化シリコン膜5を形成した後、
開孔4の底面の第2窒化シリコン膜5を除去する。
As shown in FIG. 1(a), first, a protective silicon oxide film 2 and a first silicon nitride film 3 are sequentially laminated on the surface of a silicon substrate 1, and then apertures 4 are formed to separate device regions. After further forming a second silicon nitride film 5 on the bottom and side surfaces of the opening 4 and the entire surface of the first silicon nitride film 3,
The second silicon nitride film 5 on the bottom of the opening 4 is removed.

次に、第1図(b)に示すように、開孔4の底面に露呈
したシリコン基板1に分離用酸化シリコン膜6を形成す
る。
Next, as shown in FIG. 1(b), a silicon oxide film 6 for isolation is formed on the silicon substrate 1 exposed at the bottom of the opening 4.

次に、第1図(c)に示すように、プラズマエツチング
によって上記の第1および第2窒化シリコン膜3および
5を除去し、開孔4の囲りに窒化シリコン膜の枠7を残
す。この際、窒素スペクトルの強度変化によってプラズ
マエツチングの終点を検出する。
Next, as shown in FIG. 1(c), the first and second silicon nitride films 3 and 5 are removed by plasma etching, leaving a frame 7 of the silicon nitride film around the opening 4. At this time, the end point of plasma etching is detected by the change in intensity of the nitrogen spectrum.

次に、第1図(d)に示すように、熱酸化によってシリ
コン基板1の全面に、膜厚500人ないし2000人の
酸化シリコン膜を追加し、窒化シリコン膜の枠7の下に
隔離用熱酸化シリコン膜8を侵入させる。
Next, as shown in FIG. 1(d), a silicon oxide film with a thickness of 500 to 2000 layers is added to the entire surface of the silicon substrate 1 by thermal oxidation, and an isolation layer is placed under the frame 7 of the silicon nitride film. A thermally oxidized silicon film 8 is introduced.

次に、第1図(e)に示すように、プラズマエツチング
あるいは熱燐酸エツチングにより、窒化シリコン膜の枠
7を除去する。
Next, as shown in FIG. 1(e), the frame 7 of the silicon nitride film is removed by plasma etching or hot phosphoric acid etching.

(発明の効果) 以上説明したように1本発明によれば、素子領域の周り
に形成した窒化シリコン膜の枠7を除去する際に、シリ
コン基板1は隔離用熱酸化シリコン膜8で保護されてい
るので、シリコン基板に荒れを生ずることがなく、また
、従来の改良LOGO8法と形状が変らない素子分離用
酸化シリコン膜が得られる。
(Effects of the Invention) As explained above, according to the present invention, when removing the frame 7 of the silicon nitride film formed around the element region, the silicon substrate 1 is protected by the thermally oxidized silicon film 8 for isolation. Therefore, it is possible to obtain a silicon oxide film for element isolation that does not cause roughness on the silicon substrate and has the same shape as the conventional improved LOGO8 method.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)ないしくe)は本発明による半導体装置の
製造方法の工程を示す模型断面図、第2図(a)ないし
くc)は従来の改良LOCO5法による工程を示す模型
断面図である。 1・・・シリコン基板、 2・・・保護用酸化シリコン
膜、 3・・・第1窒化シリコン膜、 4・・・開孔、
 5・・・第2窒化シリコン膜、 6・・・分離用酸化
シリコン膜、 7・・・窒化シリコン膜の枠、 8・・
・隔離用熱酸化シリコン膜。 特許出願人 松下電子工業株式会社 第2図
1(a) to e) are cross-sectional views of a model showing the steps of the method for manufacturing a semiconductor device according to the present invention, and FIGS. 2(a) to c) are cross-sectional views of a model showing the steps of the conventional improved LOCO5 method. It is. DESCRIPTION OF SYMBOLS 1... Silicon substrate, 2... Protective silicon oxide film, 3... First silicon nitride film, 4... Opening hole,
5... Second silicon nitride film, 6... Silicon oxide film for isolation, 7... Frame of silicon nitride film, 8...
・Thermal oxidation silicon film for isolation. Patent applicant: Matsushita Electronics Co., Ltd. Figure 2

Claims (1)

【特許請求の範囲】[Claims] シリコン基板の表面に酸化シリコン膜と第1窒化シリコ
ン膜とを順次積層する工程と、上記の酸化シリコン膜と
第1窒化シリコン膜の所定の領域を除去し開孔を形成す
る工程と、上記の開孔の底面および側面と上記の第1窒
化シリコン膜の上面に第2窒化シリコン膜を形成した後
、開孔の底面の第2窒化シリコン膜を除去する工程と、
上記の開孔の底面に露呈したシリコン基板に分離用酸化
シリコン膜を形成する工程と、上記の酸化シリコン膜の
開孔端に窒化シリコン膜の枠を残して上記の第1および
第2窒化シリコン膜をエッチング除去する工程と、上記
のシリコン基板の表面を熱酸化する工程と、上記の窒化
シリコン膜の枠を除去する工程とを含むことを特徴とす
る半導体装置の製造方法。
A step of sequentially laminating a silicon oxide film and a first silicon nitride film on the surface of a silicon substrate, a step of removing a predetermined region of the silicon oxide film and the first silicon nitride film to form an opening, and a step of forming an opening as described above. After forming a second silicon nitride film on the bottom and side surfaces of the opening and the top surface of the first silicon nitride film, removing the second silicon nitride film on the bottom of the opening;
forming a silicon oxide film for isolation on the silicon substrate exposed at the bottom of the opening; and leaving a frame of the silicon nitride film at the end of the opening of the silicon oxide film and forming the first and second silicon nitride films. A method for manufacturing a semiconductor device, comprising the steps of etching away the film, thermally oxidizing the surface of the silicon substrate, and removing the frame of the silicon nitride film.
JP10386986A 1986-05-08 1986-05-08 Manufacture of semiconductor device Pending JPS62261142A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10386986A JPS62261142A (en) 1986-05-08 1986-05-08 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10386986A JPS62261142A (en) 1986-05-08 1986-05-08 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS62261142A true JPS62261142A (en) 1987-11-13

Family

ID=14365443

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10386986A Pending JPS62261142A (en) 1986-05-08 1986-05-08 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS62261142A (en)

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