JPH01151244A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01151244A JPH01151244A JP31005587A JP31005587A JPH01151244A JP H01151244 A JPH01151244 A JP H01151244A JP 31005587 A JP31005587 A JP 31005587A JP 31005587 A JP31005587 A JP 31005587A JP H01151244 A JPH01151244 A JP H01151244A
- Authority
- JP
- Japan
- Prior art keywords
- groove
- polycrystalline silicon
- film
- side walls
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 16
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 9
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 8
- 230000003647 oxidation Effects 0.000 claims abstract description 6
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 6
- 238000002955 isolation Methods 0.000 abstract description 8
- 239000012212 insulator Substances 0.000 abstract description 3
- 238000001020 plasma etching Methods 0.000 abstract description 2
- 229920006254 polymer film Polymers 0.000 abstract 3
- 229920000620 organic polymer Polymers 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000000927 vapour-phase epitaxy Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置の製造方法に関するものであり、特
に素子分m領域の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming an m region for an element.
従来、素子分離法として用いられるLOCO3法は酸化
膜の横方向への広がりにより寸法変換差が大きいばかり
か1μm以下の分離中を実現する事は不可能である。そ
こで半導体基板に溝部を形成し、この溝内に多結晶シリ
コンを埋め込み酸化により絶縁物に変える「溝掘り素子
分離法Jが特開昭81−188241等にある。Conventionally, in the LOCO3 method used as an element isolation method, not only is there a large difference in dimension conversion due to the lateral spread of the oxide film, but it is also impossible to achieve isolation of 1 μm or less. Therefore, there is a ``grooving element isolation method J'' in which a groove is formed in a semiconductor substrate and polycrystalline silicon is buried in the groove and converted into an insulator by oxidation, as disclosed in Japanese Patent Laid-Open No. 188241/1981.
上述した溝掘り素子分離法は、多結晶シリコンを溝内に
平坦になる様に残すため、これを酸化した後の酸化膜は
溝側面上部に断差やくびれを残し易いという欠点があっ
た。本発明の目的は上記の欠点をな(した半導体装置を
提供する事にある。The trenching element isolation method described above leaves the polycrystalline silicon in a flat state within the trench, and therefore has the disadvantage that the oxide film after oxidizing this tends to leave gaps and constrictions on the upper side of the trench. An object of the present invention is to provide a semiconductor device that does not have the above-mentioned drawbacks.
本発明の半導体装置の製造方法は、
a)半導体基板上の任意の領域に溝を形成する工程と、
b)前記半導体基板上に熱酸化膜を形成する工程と、
(c)ついでシリコン窒化膜を形成する工程と、d)溝
の深さから前記シリコ/窒化膜の厚さを引いた値の約半
分の膜厚の多結晶・シリコン膜を順次形成する工程と、
e)前記多結晶シリコンは、前記溝の周囲側面にそって
、サイドコールを形成させながら、前記溝内部に残す様
に、他の部位を除去する工程と、f)前記溝内にのみ残
された多結晶シリコン膜を熱酸化により酸化膜とする工
程とからなる事を特徴とする。The method for manufacturing a semiconductor device of the present invention includes: a) forming a groove in an arbitrary region on a semiconductor substrate; b) forming a thermal oxide film on the semiconductor substrate; and (c) then forming a silicon nitride film. d) sequentially forming a polycrystalline/silicon film having a thickness approximately half of the depth of the groove minus the thickness of the silicon/nitride film; and e) the step of forming the polycrystalline silicon film. f) removing the polycrystalline silicon film left only within the groove while forming a side call along the peripheral side surface of the groove; It is characterized by comprising a step of forming an oxide film by thermal oxidation.
以下本発明の実施例に基づき詳細に説明する。 The present invention will be described in detail below based on examples.
第1図は本発明の一実施例を示す工程断面図である。FIG. 1 is a process sectional view showing an embodiment of the present invention.
まず、第1図(a)の如く、素子分離領域となるべきw
i域を、フォトエツチングによって、例えば、altガ
スにより5mtOrrで1w/cm鵞のRFパワーで、
半導体基板100を0.8μmエツチングし、溝部10
1を形成する。First, as shown in FIG. 1(a), w should be an element isolation region.
i region by photoetching, for example, using alt gas at 5 mtOrr and 1 w/cm RF power,
The semiconductor substrate 100 is etched by 0.8 μm to form the groove portion 10.
form 1.
ついで、第1図(b)の如く、前記半導体基板を熱酸化
、例えば1000°Co、雰囲気で400人酸化し、つ
いで、シリコン窒化膜103を1000人、多結晶シリ
コン(104)を、溝深さ0.8μmから、シリコ・ン
窒化膜0.1μmを引いた値の半分の3500人を例え
ば気相成長法により形成し、有機高分子膜105を回転
塗布する。例えば、フォトレジスト膜や、ポリイミド膜
、有機シリコン膜、等を用いる。Next, as shown in FIG. 1(b), the semiconductor substrate is thermally oxidized, for example, at 1000°C in an atmosphere of 400°C, and then the silicon nitride film 103 is formed by 1000°C, and the polycrystalline silicon (104) is formed into a deep groove. A film of 3,500 layers, which is half of the silicon nitride film of 0.8 μm minus 0.1 μm of the silicon nitride film, is formed by, for example, vapor phase epitaxy, and the organic polymer film 105 is spin-coated. For example, a photoresist film, a polyimide film, an organic silicon film, etc. are used.
ついで、第1図((c)の如く、表面を、o、プラズマ
雰囲気中で一様にエツチングし、溝内部にのみ有機高分
子膜106を残す。Then, as shown in FIG. 1(c), the surface is uniformly etched in a plasma atmosphere, leaving the organic polymer film 106 only inside the grooves.
ついで、第1図(d)の如く、前記「機高分子m10θ
をマスクに、多結晶シリコン104が溝側面にそってサ
イドコールをつ(す、溝内部に残る様に反応性イオンエ
ツチングにより加工する。Next, as shown in FIG. 1(d), the above-mentioned "machine polymer m10θ
Using this as a mask, the polycrystalline silicon 104 is etched by reactive ion etching so that side calls are made along the sides of the groove and it remains inside the groove.
ついで、第1図(e)の如(、前記有機高分子膜106
を除去した後、例えば950°Cの水蒸気中で溝内部に
残った多結晶シリコン104を酸化して、溝内部に絶縁
物層107を形成する。Then, as shown in FIG. 1(e), the organic polymer film 106 is
After removing the polycrystalline silicon 104 remaining inside the groove, the polycrystalline silicon 104 remaining inside the groove is oxidized, for example, in water vapor at 950° C. to form an insulating layer 107 inside the groove.
このとき、溝側面は、多結晶シリコンがサイドコールと
して残っているため、酸化後、溝側面に、くびれや断差
を残さず平滑な、分離領域を得られる。At this time, since the polycrystalline silicon remains as a side call on the side surfaces of the groove, a smooth separation region can be obtained after oxidation without leaving any constrictions or differences on the side surfaces of the groove.
C発明の効果〕
以上説明した様に、本発明によれば、分m領域と素子領
域のつなぎ目に断差やくびれのない平滑な素子分離層を
備えた、寸法変換差のほぼ0の半導体装置が得られる。C. Effects of the Invention] As explained above, according to the present invention, a semiconductor device with a dimensional conversion difference of almost 0, which is provided with a smooth element isolation layer without any difference or constriction at the joint between the minute region and the element region. is obtained.
第1図(a)〜(e)は本発明による半導体装置の製造
方法の一実施例を示す工程断面図である。
100・・・半導体基板
101・・・溝部
102・・・酸化膜
103・・・シリコン窒化膜
104・・・多結晶シリコン
105・・・有機高分子膜
10G・・・を機高分子膜
107・・・絶縁物層
以 上
t[人 セイコーエプソン株式会社FIGS. 1(a) to 1(e) are process cross-sectional views showing one embodiment of the method for manufacturing a semiconductor device according to the present invention. 100...Semiconductor substrate 101...Groove portion 102...Oxide film 103...Silicon nitride film 104...Polycrystalline silicon 105...Organic polymer film 10G...・・Insulator layer or more t [person Seiko Epson Corporation
Claims (1)
値の約半分の膜厚の多結晶シリコン膜を順次形成する工
程と、 (e)前記多結晶シリコンは、前記溝の周囲側面にそっ
て、サイドコールを形成させながら前記溝内部に残す様
に、他の部位を除去する工程と (f)前記溝内にのみ残された多結晶シリコン膜を熱酸
化により酸化膜とする工程とからなる事を特徴とする、
半導体装置の製造装置。[Claims] (a) Step of forming a groove in an arbitrary region on the semiconductor substrate; (b) Step of forming a thermal oxide film on the semiconductor substrate; and (c) Step of forming a silicon nitride film. (d) sequentially forming a polycrystalline silicon film having a thickness of approximately half the value obtained by subtracting the thickness of the silicon nitride film from the depth of the groove; (e) the polycrystalline silicon is (f) forming an oxide film by thermal oxidation of the polycrystalline silicon film left only in the groove; It is characterized by consisting of the process of
Manufacturing equipment for semiconductor devices.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31005587A JPH01151244A (en) | 1987-12-08 | 1987-12-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP31005587A JPH01151244A (en) | 1987-12-08 | 1987-12-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01151244A true JPH01151244A (en) | 1989-06-14 |
Family
ID=18000621
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP31005587A Pending JPH01151244A (en) | 1987-12-08 | 1987-12-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01151244A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5837596A (en) * | 1994-03-02 | 1998-11-17 | Micron Technology, Inc. | Field oxide formation by oxidation of polysilicon layer |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62186546A (en) * | 1986-02-13 | 1987-08-14 | Sony Corp | Manufacture of semiconductor device |
-
1987
- 1987-12-08 JP JP31005587A patent/JPH01151244A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62186546A (en) * | 1986-02-13 | 1987-08-14 | Sony Corp | Manufacture of semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5837596A (en) * | 1994-03-02 | 1998-11-17 | Micron Technology, Inc. | Field oxide formation by oxidation of polysilicon layer |
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