JPS62260369A - Manufacture of thin-film transistor - Google Patents
Manufacture of thin-film transistorInfo
- Publication number
- JPS62260369A JPS62260369A JP10320686A JP10320686A JPS62260369A JP S62260369 A JPS62260369 A JP S62260369A JP 10320686 A JP10320686 A JP 10320686A JP 10320686 A JP10320686 A JP 10320686A JP S62260369 A JPS62260369 A JP S62260369A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- thin film
- film
- thin
- heat
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 81
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 23
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229920001721 polyimide Polymers 0.000 claims abstract description 8
- 239000009719 polyimide resin Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 20
- 229910052751 metal Inorganic materials 0.000 claims description 20
- 239000011347 resin Substances 0.000 claims description 12
- 229920005989 resin Polymers 0.000 claims description 12
- 238000005530 etching Methods 0.000 claims description 11
- 239000010408 film Substances 0.000 abstract description 31
- VNNRSPGTAMTISX-UHFFFAOYSA-N chromium nickel Chemical compound [Cr].[Ni] VNNRSPGTAMTISX-UHFFFAOYSA-N 0.000 abstract description 12
- 229910001120 nichrome Inorganic materials 0.000 abstract description 12
- 229910021417 amorphous silicon Inorganic materials 0.000 abstract description 5
- 229910004205 SiNX Inorganic materials 0.000 abstract description 4
- 230000015572 biosynthetic process Effects 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 abstract description 2
- 238000007493 shaping process Methods 0.000 abstract 1
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 description 2
- 229910016006 MoSi Inorganic materials 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- DKPFZGUDAPQIHT-UHFFFAOYSA-N butyl acetate Chemical compound CCCCOC(C)=O DKPFZGUDAPQIHT-UHFFFAOYSA-N 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- KVBCYCWRDBDGBG-UHFFFAOYSA-N azane;dihydrofluoride Chemical compound [NH4+].F.[F-] KVBCYCWRDBDGBG-UHFFFAOYSA-N 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000009751 slip forming Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66765—Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
Abstract
Description
【発明の詳細な説明】
（産業上の利用分野）
本発明は電圧印加により電流制御を行なう自己整合型の
薄膜トランジスタの製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a self-aligned thin film transistor in which current is controlled by applying a voltage.
（従来の技術）
第４図は従来の薄膜トランジスタの製造方法を示す断面
図である。従来の薄膜トランジスタは透明基板（たとえ
ば、コーニング社製７０５９ガラス）１１上に、選択的
に膜厚０．２ｐｍのＮｉＣｒ膜のゲートとなる第１金属
薄膜１２を形成し、絶縁層１３としてＳｉｎ。(Prior Art) FIG. 4 is a cross-sectional view showing a conventional method for manufacturing a thin film transistor. In a conventional thin film transistor, a first metal thin film 12 is selectively formed on a transparent substrate (for example, 7059 glass manufactured by Corning Corporation) 11 to serve as a gate of a NiCr film with a film thickness of 0.2 pm, and an insulating layer 13 is made of Sin.
を０．４ｐｔｎ積層し、半導体層１４としてｉ −ａ
−３ｉ（アモルファスシリコン）を０．１μｍ積層し、
感光層１５として、たとえばポジ型レジストＡ Ｚ １
４００−３１（シブレイファーイースト社製）を塗布し
、透明基板１１側から紫外光Ｑ（波長０．３μｍ〜０．
４μｍ）を照射する〔第４図（ａ）〕。ＮｉＣｒ膜から
なる第１電極（第１金属薄膜）１２は遮光膜として働き
、未露光部１６が残り、第４図（ｂ）に示すようにパタ
ーン形成される。0.4ptn is laminated as the semiconductor layer 14 i - a
-3i (amorphous silicon) is laminated to a thickness of 0.1 μm,
As the photosensitive layer 15, for example, a positive resist A Z 1
400-31 (manufactured by Sible Far East Co., Ltd.) and exposed to ultraviolet light Q (wavelength 0.3 μm to 0.5 μm) from the transparent substrate 11 side.
4 μm) [Figure 4(a)]. The first electrode (first metal thin film) 12 made of a NiCr film functions as a light shielding film, and an unexposed portion 16 remains, which is patterned as shown in FIG. 4(b).
次にオーミック接合を得るために導体層１７としてｎ
” −ａ−３ｉ（５０ｎｍ）／ＮｉＣｒ（１００ｎｍ）
を順次積層して〔第４図（Ｃ）〕、いわゆるフォトオフ
法によりフォトレジストを除去し、ソースとなる第２金
属薄膜１８、ドレインとなる第２金属薄膜１９を形成し
〔第４図（ｄ）〕、薄膜トランジスタを製造していた。Next, in order to obtain an ohmic connection, the conductor layer 17 is
”-a-3i (50nm)/NiCr (100nm)
The photoresist is removed by a so-called photo-off method to form a second metal thin film 18 that will become a source and a second metal thin film 19 that will become a drain [Fig. 4 (C)]. d)], which manufactured thin film transistors.
［参考文献：信学技報Ｅ Ｄ８３−７０ （１９８３）
Ｐ ４７］（発明が解決しようとする問題点）
従来の薄膜トランジスタの製造方法では、第２゜第３電
極を構成する導体層の形成温度を１５０℃以下にする必
要がある。すなわち、１５０℃以上ではリフトオフ法に
係るポジ型レジストが硬化変質し。[Reference: IEICE Technical Report E D83-70 (1983)
P47] (Problems to be Solved by the Invention) In the conventional manufacturing method of a thin film transistor, the formation temperature of the conductor layer constituting the second and third electrodes needs to be 150° C. or lower. That is, at temperatures above 150° C., the positive resist used in the lift-off method hardens and changes in quality.
溶媒（たとえば、アセトン、発煙硝酸）に溶解せずパタ
ーニングができない。一方、１５０℃以下ではｎ′″−
ａ−５ｉの形成温度が低いのでｎ′″−ａ −５ｉの活
性度が低く、シート抵抗が大きくなる。したがって、薄
膜トランジスタのオン電流が充分得られず、特性を活か
し得ないという欠点を有していた。It does not dissolve in solvents (e.g., acetone, fuming nitric acid) and cannot be patterned. On the other hand, below 150℃, n'''-
Since the formation temperature of a-5i is low, the activity of n'''-a-5i is low and the sheet resistance is high.Therefore, it has the disadvantage that a sufficient on-current of the thin film transistor cannot be obtained and its characteristics cannot be utilized. was.
本発明の目的は、従来の欠点を解消し、薄膜トランジス
タを構成するｎ“−ａ −３ｉ層の形成温度を１５０℃
以上にし、オン電流不足が生ぜず、特性の優れた薄膜ト
ランジスタの製造方法を提供することである。An object of the present invention is to eliminate the conventional drawbacks and to reduce the formation temperature of the n"-a-3i layer constituting a thin film transistor to 150°C.
In view of the above, it is an object of the present invention to provide a method for manufacturing a thin film transistor that does not suffer from insufficient on-current and has excellent characteristics.
（問題点を解決するための手段）
本発明の薄膜トランジスタの製造方法は、透明基板上に
少なくとも第１金屓薄膜を設ける第１工程と、第１絶縁
層と半導体層を設ける第２工程と、耐熱薄膜層と感光層
を設ける第３工程と、この感光層を食刻し、さらに耐熱
薄膜層を食刻する第４工程と、第２金属薄膜を設ける第
５工程と、前記耐熱薄膜層を除去する第６工程とを有す
るものである。(Means for Solving the Problems) The method for manufacturing a thin film transistor of the present invention includes a first step of providing at least a first metal thin film on a transparent substrate, a second step of providing a first insulating layer and a semiconductor layer, A third step of providing a heat-resistant thin film layer and a photosensitive layer, a fourth step of etching this photosensitive layer and further etching the heat-resistant thin film layer, a fifth step of providing a second metal thin film, and a step of etching the heat-resistant thin film layer. and a sixth step of removing.
また、第２工程において、第２絶Ｉ＃層をさらに設ける
工程と、この第１絶縁層を第４工程により農作された耐
熱Ｖ膜層をマスクとして食刻する工程を有するものであ
る。Further, the second step includes a step of further providing a second insulating I# layer, and a step of etching this first insulating layer using the heat-resistant V film layer produced in the fourth step as a mask.
また、第１金属薄膜をゲート電極、第２金属薄膜をソー
ス電極ならびにドレイン電極とするものである。Further, the first metal thin film is used as a gate electrode, and the second metal thin film is used as a source electrode and a drain electrode.
また第６工程の最高基板温度が１５０℃以上であり耐熱
薄膜層を有機樹脂層とするものであり、さらに耐熱薄膜
層をポリミド樹脂層とするものである。Further, the maximum substrate temperature in the sixth step is 150° C. or higher, the heat-resistant thin film layer is an organic resin layer, and the heat-resistant thin film layer is a polymide resin layer.
（作 用）
本発明の製造方法によると、リフトオフ法用の除去する
パターンを感光層により形成すると共に耐熱薄膜層にも
形成している。したがって、オーミック接合を得るｎ”
−ａ−３ｉ層を１５０℃ないし３００℃の温度範囲で製
作できるためｎ”−ａ−３ｉ層の活性度が高く、シート
抵抗が低い。これにより薄膜トランジスタのオン電流を
充分にとることができ、特性の優れた薄膜トランジスタ
を製造できる。(Function) According to the manufacturing method of the present invention, the pattern to be removed for the lift-off method is formed not only by the photosensitive layer but also by the heat-resistant thin film layer. Therefore, we obtain an ohmic junction n”
Since the -a-3i layer can be manufactured in a temperature range of 150°C to 300°C, the n''-a-3i layer has high activity and low sheet resistance.This makes it possible to obtain a sufficient on-current of the thin film transistor. Thin film transistors with excellent characteristics can be manufactured.
（実施例）
本発明の実施例を第１図ないし第３図に基づいて説明す
る。(Example) An example of the present invention will be described based on FIGS. 1 to 3.
第１図は本発明の薄膜トランジスタの製造方法の工程図
である。FIG. 1 is a process diagram of a method for manufacturing a thin film transistor according to the present invention.
第１図（ａ）において、透明基板１上に第１金属薄膜２
を設ける第１工程と、同図（ｂ）に示す絶縁層３、半導
体層４を設ける第２工程と、同図（ｃ）に示す耐熱薄膜
層５と感光層６を設ける第３工程と、同図（ｄ）に示す
感光層６を食刻し、さらに耐熱薄膜層５を選択食刻する
第４工程と、同図（ｅ）に示す第２金属薄膜７を設ける
第５工程と、同図（ｆ）に示す耐熱薄膜層５を除去する
第６工程を経て薄膜トランジスタを製作する。In FIG. 1(a), a first metal thin film 2 is formed on a transparent substrate 1.
a second step of providing an insulating layer 3 and a semiconductor layer 4 as shown in FIG. 3(b), and a third step of providing a heat-resistant thin film layer 5 and a photosensitive layer 6 as shown in FIG. The fourth step of etching the photosensitive layer 6 and selectively etching the heat-resistant thin film layer 5 shown in FIG. A thin film transistor is manufactured through a sixth step of removing the heat-resistant thin film layer 5 shown in FIG. 5(f).
次に本実施例を具体的に説明する。第１図（ａ）に示す
ように透明基板１（たとえば、コーニング社製７０５９
ガラス）を使用し、ゲートとなる膜厚１１００ｎのＮｉ
Ｃｒ膜の第１電極（第１金属薄膜）２を形成し、絶縁層
３として膜厚４００止のＳｉＮ、膜、半導体層４として
膜厚１１００ｎのｉ −ａ−３ｉ膜をプラズマＣＶＤ法
により連続堆積させた１次に耐熱薄膜層５としてポリミ
ド樹脂溶液（たとえば、東し社＠５ｐ９１０）を１ 、
０ｐｍ膜厚でスピナ塗布し、キュア温度１４０°Ｃない
し１６０℃で乾燥硬化させた耐熱薄膜層である。ポリミ
ド樹脂５上に感光層６としてポジ型レジスト（たとえば
、シブレイファーイースト社製Ａ Ｚ １４００−２７
）を膜厚１．４μｍでスピナ塗布し、透明基板１側より
紫外線（波長０．３ｐｔｓ〜０．５μｍ）で照射し露光
させた。ＮｉＣｒ膜からなる第１電極２は遮光マスクと
して働くので、現像、定着により、ポリミド樹脂５とポ
ジ型レジストは同図（ｄ）のように食刻され、リフトオ
フ用のパターンが製作できた。Next, this example will be explained in detail. As shown in FIG. 1(a), a transparent substrate 1 (for example, Corning 7059
glass) with a thickness of 1100 nm to form the gate.
A first electrode (first metal thin film) 2 of Cr film is formed, an SiN film with a thickness of 400 nm is formed as an insulating layer 3, and an i-a-3i film with a thickness of 1100 nm is continuously formed as a semiconductor layer 4 by plasma CVD. As the deposited primary heat-resistant thin film layer 5, a polyimide resin solution (for example, Toshisha @ 5p910) is added to
It is a heat-resistant thin film layer coated with a spinner to a thickness of 0 pm and dried and cured at a curing temperature of 140°C to 160°C. A positive resist (for example, AZ 1400-27 manufactured by Sible Far East Co., Ltd.) is applied as a photosensitive layer 6 on the polyimide resin 5.
) was spin-coated to a film thickness of 1.4 μm, and exposed to ultraviolet light (wavelength: 0.3 pts to 0.5 μm) from the transparent substrate 1 side. Since the first electrode 2 made of the NiCr film acts as a light-shielding mask, the polyimide resin 5 and the positive resist were etched by development and fixation as shown in FIG.
ポリミド樹脂５のキュア温度を１４０℃ないし１６０℃
で乾燥硬化させた場合、ポジ型レジストの現像液でレジ
ストと同時に食刻することができる。Cure temperature of polymide resin 5 from 140℃ to 160℃
If the resist is dried and hardened, it can be etched with a positive resist developer at the same time as the resist.
次にポストベークとして、１５０℃、３０分間乾燥硬化
させたのち、同図（ｅ）に示すように第２金属薄膜７と
して、１５０℃ないし３００℃の温度範囲でｎ”−ａ−
Ｓｉ層を５０ｎｍ、室温でＮｉＣｒを２００止ｍ堆積さ
せた。かかるのちに、発煙硝酸によりポリミド樹脂５を
除去することにより薄膜トランジスタを製造した。Next, as a post-bake, after drying and curing at 150°C for 30 minutes, as shown in the figure (e), the n"-a-
A Si layer was deposited to a thickness of 50 nm, and a NiCr layer was deposited to a thickness of 200 nm at room temperature. Thereafter, the polyimide resin 5 was removed using fuming nitric acid to produce a thin film transistor.
第１実施例において、第５工程の最高基板温度が１５０
℃以下ではｎ”−ａ−３ｉｌｉの活性度が低く、本発明
の目的ではない。ポリミド樹脂からなる耐熱簿膜層を用
いているので、１５０℃以上の温度でｎ″″−ａ −５
ｉ膜の製作できる本発明の効果が現われる。また、ポリ
ミド樹脂からなる有機樹脂層の耐熱絶縁層を用いている
ので、溶液状態で塗布できるので製作が容易であるとい
う利点を有している。In the first embodiment, the maximum substrate temperature in the fifth step is 150
At temperatures below 150°C, the activity of n''-a-3 is low, and this is not the purpose of the present invention.Since a heat-resistant film layer made of polyimide resin is used, at temperatures above 150°C, n''-a-5
The effect of the present invention, which allows the production of i-films, appears. Furthermore, since the heat-resistant insulating layer is an organic resin layer made of polymide resin, it has the advantage of being easy to manufacture because it can be applied in a solution state.
第２図は第２実施例の薄膜トランジスタの製造方法の工
程図である。FIG. 2 is a process diagram of a method for manufacturing a thin film transistor according to a second embodiment.
同図（ａ）において、第１実施例に示した第２工程のＳ
ｉＮ、膜からなる第１絶縁層３とｉ −ａ −５ｉ膜か
らなる半導体層４に加えてＳｉＮｘ膜からなる第２絶縁
層８を設ける第２８工程とした。同図（ｂ）に示すよう
に、ポリミド樹脂５、ポジ型レジスト層６を積層し、ゲ
ートとなる第１電極（第１金属薄膜）２をマスクとして
透明基板１側より紫外線を照射し、ポジ型レジスト層を
露光、現像することにより、ポリミド樹脂５をパターニ
ングした。次にＢＨＦ（フッ酸−フッ化アンモニウム）
溶液によりＳｉＮｘ膜８を食刻する第４工程を行なった
ｓ ５ＩＮ１１膜８はｉ −ａ−３ｉ膜からなる半導体
層４のパッシベーションとして用いた。続いて同図（Ｃ
）に示すように、ｎ” −ａ−５ｉ／ＮｉＣｒ膜をおの
おの１５０℃ないし３００℃、室温の温度範囲で堆積さ
せたのち、発煙硝酸により、ポリミド樹脂５を除去し、
同図（ｄ）に示すように薄膜トランジスタを製造した。In the same figure (a), S of the second step shown in the first embodiment is shown.
In addition to the first insulating layer 3 made of an iN film and the semiconductor layer 4 made of an i-a-5i film, a second insulating layer 8 made of an SiNx film was provided in the 28th step. As shown in the same figure (b), a polymide resin 5 and a positive resist layer 6 are laminated, and ultraviolet rays are irradiated from the transparent substrate 1 side using the first electrode (first metal thin film) 2 serving as a gate as a mask. The polymide resin 5 was patterned by exposing and developing the mold resist layer. Next, BHF (hydrofluoric acid-ammonium fluoride)
The s5IN11 film 8 subjected to the fourth step of etching the SiNx film 8 with a solution was used as passivation for the semiconductor layer 4 made of the i-a-3i film. Next, the same figure (C
), after each n''-a-5i/NiCr film was deposited at a temperature range of 150°C to 300°C and room temperature, the polymide resin 5 was removed using fuming nitric acid.
A thin film transistor was manufactured as shown in FIG. 4(d).
第３図は第３実施例の薄膜トランジスタの製造方法の工
程図である。本実施例では第４工程においてポリミド樹
脂を食刻したのち、ポジ型レジスト層を除去し、ポリミ
ド樹脂だけでリフトオフ法を用いるものである。すなわ
ち、同図（ａ）はポジ型レジスト層６を酢酸ｎブチルに
より除去した状態を示す。次にｎ ” −ａ −Ｓｉ／
ＮｉＣｒ膜（第２金属薄膜）７をおのおの１５０℃ない
し３００℃、室温の温度範囲で同図（ｂ）に示すように
形成した。ポリミド樹脂５を発煙硝酸により除去し、同
図（ｃ）に示すように薄膜トランジスタが製作できた。FIG. 3 is a process diagram of a method for manufacturing a thin film transistor according to a third embodiment. In this embodiment, after etching the polymide resin in the fourth step, the positive resist layer is removed, and a lift-off method is used only with the polymide resin. That is, FIG. 3A shows a state in which the positive resist layer 6 has been removed with n-butyl acetate. Then n ” −a −Si/
A NiCr film (second metal thin film) 7 was formed in the temperature range of 150° C. to 300° C. and room temperature, as shown in FIG. 2(b). The polymide resin 5 was removed using fuming nitric acid, and a thin film transistor was fabricated as shown in FIG. 2(c).
以上の実施例において、 Ｗ／Ｌ＝５０（ゲート幅／ゲ
ート長）で製作した場合いずれも、ゲート・ドレイン間
容量Ｃｄｇ＜ＩＰＦ以下、オン電流Ｉ。Ｎ＝６０ｐＡ（
ゲート電圧Ｖｇ＝２０Ｖ、ソース・ドレイン間電圧Ｖｄ
ｓ ＝１２Ｖ）と自己整合型でなくｎ”−ａ−３ｉ層を
２５０℃で形成した薄膜トランジスタと同等の特性が得
られた。In the above embodiments, when manufactured with W/L=50 (gate width/gate length), the gate-drain capacitance Cdg<IPF or less and the on-current I. N=60pA(
Gate voltage Vg=20V, source-drain voltage Vd
s = 12 V), and characteristics equivalent to those of a non-self-aligned thin film transistor in which an n''-a-3i layer was formed at 250° C. were obtained.
以上の実施例の説明において、第１金属薄膜は紫外光を
遮光できる導体層であればよ（、ＮｉＣｒ膜に限定され
るものではない。すなわち、Ｃｒ’、 Ｃｒ／ＭｏＳｉ
、 Ｃｒ／Ｔｉ、 Ｃｒ／Ａｕ、 ＡＱ、 Ａｌｌ／Ｍ
ｏ５ｉｔ ＡｌｌＴｉｎ ＴｉＮ＋Ｔａ＋Ｍｏ膜などの
材料も本発明に含まれる。In the description of the above embodiments, the first metal thin film may be any conductive layer that can block ultraviolet light (and is not limited to a NiCr film; that is, Cr', Cr/MoSi, etc.).
, Cr/Ti, Cr/Au, AQ, All/M
Materials such as o5it AllTin TiN+Ta+Mo films are also included in the invention.
第１．第２絶縁層もＳｉＮｘ膜に限定されない。たとえ
ば、Ｓｉｎ□、 Ｔａｍｅ、 、 Ａ（１２０ｓ ＊
ｙ２ｏ、 ｌ ＺｒＯ２等の絶縁体も本発明に含まれる
。また第２金属薄膜は導体層であればよ＜ 、 ａ −
３ｉ／ＮｉＣｒ膜に限定されるもノテはない。すなわち
、ＡＱ、 Ａｌｌ／Ｔｉ、 Ａｉｌ／ＭｏＳｉ、。1st. The second insulating layer is also not limited to the SiNx film. For example, Sin□, Tame, , A (120s *
Insulators such as y2o, lZrO2 are also included in the present invention. Further, the second metal thin film may be a conductive layer < , a −
Although it is limited to 3i/NiCr film, there is no note. That is, AQ, All/Ti, Ail/MoSi.
ｉＴｏ、 Ｔａ、 Ｍｏ、 ＴｉＮ膜などの材料も本発
明に含まれる。Materials such as iTo, Ta, Mo, and TiN films are also included in the present invention.
（発明の効果）
本発明によれば、耐熱薄膜層を用いることにより、薄膜
トランジスタのオーミック接合用のｎ”−ａ−３ｉ膜を
１５０℃以上の温度で形成できる。(Effects of the Invention) According to the present invention, by using a heat-resistant thin film layer, an n''-a-3i film for ohmic junction of a thin film transistor can be formed at a temperature of 150° C. or higher.
したがって、ｎ”−ａ−５ｉ膜の活性度が高くシー１−
抵抗が低いので、オーミック接合でしかも低コンタクト
抵抗が得られる。このため、従来コンタクト抵抗のため
不足した薄膜トランジスタのオン電流工。８を特性どう
り得ることができ、実用上きわめて効果が大である。Therefore, the activity of the n''-a-5i film is high and the
Since the resistance is low, it is possible to obtain an ohmic contact with low contact resistance. For this reason, the on-state current of thin film transistors was insufficient due to conventional contact resistance. 8 can be obtained, and it is extremely effective in practice.
【図面の簡単な説明】
第１図は本発明の実施例による薄膜トランジスタの製造
方法の工程断面図、第２図は同第２実施例の工程断面図
、第３図は同第３実施例の工程断面図、第４図は、従来
の薄膜トランジスタの製造方法を示す工程断面図である
。
１・・・透明基板、 ２・・・ゲートとなる第１電極（
第１金属薄膜）、 ３・・・絶縁層、 ４・・・半導
体層、 ５・・・耐熱薄膜層、 ６・・・感光層、
７− ｎ ” −ａ −Ｓｉ／ＮｉＣｒ膜（第２金属薄
膜）、 ８・・・第２絶縁層。
特許出願人 松下電器産業株式会社
第１図
第１図
７−−−乃’ｌ’ｌＬ属博牒
第２図
第３図
第４図
１日
第４図[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a cross-sectional view of a method for manufacturing a thin film transistor according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of a process of a second embodiment of the present invention, and FIG. FIG. 4 is a process cross-sectional view showing a conventional thin film transistor manufacturing method. 1... Transparent substrate, 2... First electrode serving as a gate (
(first metal thin film), 3... insulating layer, 4... semiconductor layer, 5... heat-resistant thin film layer, 6... photosensitive layer,
7-n''-a-Si/NiCr film (second metal thin film), 8... second insulating layer. Patent applicant: Matsushita Electric Industrial Co., Ltd. Figure 2 Figure 3 Figure 4 Figure 1 Day Figure 4
Claims (6)
１工程と、第１絶縁層と半導体層を設ける第２工程と、
耐熱薄膜層と感光層を設ける第３工程と、前記感光層を
食刻し、さらに前記耐熱薄膜層を食刻する第４工程と、
第２金属薄膜を設ける第５工程と、前記耐熱薄膜層を除
去する第６工程とを有することを特徴とする薄膜トラン
ジスタの製造方法。(1) a first step of providing at least a first metal thin film on a transparent substrate; a second step of providing a first insulating layer and a semiconductor layer;
a third step of providing a heat-resistant thin film layer and a photosensitive layer; a fourth step of etching the photosensitive layer; and further etching the heat-resistant thin film layer;
A method for manufacturing a thin film transistor, comprising: a fifth step of providing a second metal thin film; and a sixth step of removing the heat-resistant thin film layer.
程と、該第２絶縁層を、前記第４工程により製作された
耐熱薄膜層をマスクとして食刻する工程を有することを
特徴とする特許請求の範囲第（１）項記載の薄膜トラン
ジスタの製造方法。(2) The second step is characterized by comprising the steps of further providing a second insulating layer and etching the second insulating layer using the heat-resistant thin film layer produced in the fourth step as a mask. A method for manufacturing a thin film transistor according to claim (1).
ス電極ならびにドレイン電極とすることを特徴とする特
許請求の範囲第（１）項記載の薄膜トランジスタの製造
方法。(3) The method for manufacturing a thin film transistor according to claim (1), characterized in that the first metal thin film is used as a gate electrode, and the second metal thin film is used as a source electrode and a drain electrode.
とを特徴とする特許請求の範囲第（１）項記載の薄膜ト
ランジスタの製造方法。(4) The method for manufacturing a thin film transistor according to claim (1), wherein the maximum substrate temperature in the sixth step is 150° C. or higher.
特許請求の範囲第（１）項記載の薄膜トランジスタの製
造方法。(5) The method for manufacturing a thin film transistor according to claim (1), wherein the heat-resistant thin film layer is an organic resin layer.
する特許請求の範囲第（５）項記載の薄膜トランジスタ
の製造方法。(6) The method for manufacturing a thin film transistor according to claim (5), wherein the heat-resistant thin film layer is a polyimide resin layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10320686A JPS62260369A (en) | 1986-05-07 | 1986-05-07 | Manufacture of thin-film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10320686A JPS62260369A (en) | 1986-05-07 | 1986-05-07 | Manufacture of thin-film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62260369A true JPS62260369A (en) | 1987-11-12 |
Family
ID=14348040
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10320686A Pending JPS62260369A (en) | 1986-05-07 | 1986-05-07 | Manufacture of thin-film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62260369A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994020982A1 (en) * | 1993-03-01 | 1994-09-15 | General Electric Company | Self-aligned thin-film transistor constructed using lift-off technique |
| EP0643420A2 (en) * | 1993-09-03 | 1995-03-15 | General Electric Company | Lift-off fabrication method for self-aligned thin film transistors |
| US5541128A (en) * | 1993-04-05 | 1996-07-30 | General Electric Company | Self-aligned thin-film transistor constructed using lift-off technique |
| EP0766296A2 (en) * | 1995-09-29 | 1997-04-02 | Sony Corporation | Method of manufacturing a thin film transistor |
-
1986
- 1986-05-07 JP JP10320686A patent/JPS62260369A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1994020982A1 (en) * | 1993-03-01 | 1994-09-15 | General Electric Company | Self-aligned thin-film transistor constructed using lift-off technique |
| US5527726A (en) * | 1993-03-01 | 1996-06-18 | General Electric Company | Self-aligned thin-film transistor constructed using lift-off technique |
| US5541128A (en) * | 1993-04-05 | 1996-07-30 | General Electric Company | Self-aligned thin-film transistor constructed using lift-off technique |
| EP0643420A2 (en) * | 1993-09-03 | 1995-03-15 | General Electric Company | Lift-off fabrication method for self-aligned thin film transistors |
| EP0643420A3 (en) * | 1993-09-03 | 1997-04-02 | Gen Electric | Lift-off fabrication method for self-aligned thin film transistors. |
| EP0766296A2 (en) * | 1995-09-29 | 1997-04-02 | Sony Corporation | Method of manufacturing a thin film transistor |
| EP0766296A3 (en) * | 1995-09-29 | 1998-05-13 | Sony Corporation | Method of manufacturing a thin film transistor |
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