JPS62260279A - High-speed image processing circuit - Google Patents

Abstract

PURPOSE:To process image data at a high speed by reading image data and border data, word by word, and performing arithmetic processes such as noise removal and contour extraction in parallel. CONSTITUTION:A shift register 2 is stored with image data read out of an image memory in word units at right angles to a line direction. Shift registers 3 and 4 are stored with the border data as an object of image processes. The data in the registers 2, 3, and 4 are processed by an arithmetic processing part 5 by noise removal, contour extraction, direction code detection, histogram generation, etc., in parallel, thus performing the processes at a high speed.

Description

Detailed Description of the Invention [Summary] The image data of the area to be processed in the image memory is read out in word units, and the boundary data of the area is also read out in word units to perform noise removal 2 contour extraction.

Processing such as direction code detection and histogram creation is performed in parallel, and enables high-speed processing of image data in character recognition, figure recognition, etc.

[Industrial application field]

The present invention relates to a high-speed image processing circuit that processes image data at high speed in character recognition, figure recognition, etc.

In processing devices such as character recognition and figure recognition, two-dimensional image data is stored in the image memory, subjected to preprocessing such as noise removal, and then characterized by contour extraction, direction code detection, histogram creation, etc. Characters or figures are recognized based on the characteristic amounts obtained. Therefore, there is a demand for faster processing for determining feature amounts.

[Conventional technology]

Image memory in conventional processing devices that perform character recognition, figure recognition, etc. is accessed in accordance with the rask scan method, and image data is processed in units of pixels or words with multiple pixels as one word. A configuration in which writing and reading were performed was common. In a configuration that writes and reads image data in units of words, serial image data obtained by reading scanning is converted into parallel image data in units of words and written, and image data read out in units of words is converted into parallel image data in units of words. It was converted into serial image data and processed.

In addition, processing such as noise removal 1 contour extraction, direction code detection, etc.
A shift register with a number of lines corresponding to the size of the processing area is provided, image data read from the image memory is stored in the shift register, and output data of the shift register corresponding to the processing area is subjected to arithmetic processing. For example, 3
When performing noise removal by processing ×3 pixels, a shift register for 3 lines is provided, and 3 × 3 pixels are used by the output of three successive stages of the shift register of each line, and the center pixel is an isolated black spot. If so, it is treated as noise and processed to be a white point, and such processing is performed sequentially for 3×3 pixels.

When performing contour extraction, it is determined whether the center pixel of 3×3 pixels is a conversion point from a white pixel to a black pixel or from a black pixel to a white pixel. Each 3×3 pixel is identified and the contour is determined by a continuous line of conversion points.

[Problem that the invention seeks to solve]

In conventional processing devices for character recognition, figure recognition, etc., even if image data is written to and read from the image memory in word units, processes such as noise removal and outline extraction are performed in pixel units. Therefore, as the number of pixels increases, the processing time becomes extremely long.

Also, when performing local processing of image data stored in the image memory, it is necessary to change the length of the shift register compared to when processing the entire screen; cannot be done easily, so
It has been difficult to realize a configuration that performs local processing.

The present invention improves the above-mentioned conventional drawbacks, and aims to process image data at high speed by handling image data in word units and performing parallel arithmetic processing.

[Means for solving problems]

The high-speed image processing circuit of the present invention reads the image data of the processing area and the boundary data of the boundary of the processing area from the image memory in word units, and performs parallel calculation processing. explain. The image data read by scanning a character 1 figure, etc. is stored in the image memory 1, and the image data read from the image memory 1 in units of words is shifted in units of words by a shift register 2, and written into the shift register 2. Shift registers 3 and 4 read out and shift boundary data adjacent to the image data area from the image memory 1 in word units, and the output data of each stage of these shift registers 2 and 3.4 is processed in parallel. It includes an arithmetic processing section 5 and a register 6 that stores output data processed by the arithmetic processing section 5.

[Effect]

The shift register 2 stores image data read from the image memory word by word in the direction perpendicular to the line direction, and the image data of the processing area is read out and processed by the arithmetic processing section 5 for noise removal, contour extraction, Processing such as direction code detection and histogram creation is performed. In that case, it may be necessary to perform arithmetic processing using image data adjacent to the area of image data stored in shift register 2, so this is stored in shift registers 3 and 4 as boundary data. . Thereby, image data can be accumulated in the shift register 2 in units of words, and processing of a predetermined area can be continued. Furthermore, since the arithmetic processing unit 5 performs arithmetic processing in parallel, high-speed processing is possible.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention.
22 is a register, and CKT1 to CKT8 are circuits for performing logical filter processing such as noise removal, contour extraction, and direction code detection. Also, registers 11, 12, and 13 constitute shift register 2, registers 14, 15, and 16 constitute shift register 3, and registers 17, 18, and 19.
The shift register 4 is configured by the above. Also circuit CKT
1 to CKT8 constitute an arithmetic processing unit 5 in which 8 pixels correspond to 1 word. Note that the image memory l in FIG. 1 is omitted from illustration.

FIG. 3 is an explanatory diagram of successive output control of the image memory, in which 8 pixels of each line constitute one word, word W1 of line 1 is read out first and written to register 11, and then word W1 of line 2 is read out and written to register 11. Word Wl is read and applied to register 11, and the contents of register 11 are shifted into register 12. Word Wl on line 3 is then read and added to register 11, and the contents of register 12 are read out and added to register 13.
Also, the contents of register 11 are shifted into register 12, respectively. That is, the image data is read word by word in the vertical direction of the image memory, and the words Wl of lines 1 to 3 are stored in the shift register.

As boundary data adjacent to the left side of the area of word W1 of lines 1 to 3, pixel 0 of lines 1 to 8 (LWl)
One word worth of image data is written into the register 14. In this case, the image data is selected to be all black image data in accordance with the initial conditions. Also, according to the word-by-word shift operations in registers 11 to 13,
Image data for one pixel is sequentially shifted from register 14 to registers 15 and 16.

Also, as boundary data adjacent to the right side of the area, line 1 to
8 (LWI), one word worth of image data of pixel 9 is written to register 17, and the above-mentioned registers 14, 15.1
6, 1 from register 17 to register 18.19
Image data for pixels is shifted. Here, the memory is divided into an area for storing the image data for one word and an area for storing the boundary data, and each time the image data for eight words is read, the boundary data is stored once. is controlled to read out.

For example, the word W1 of line 4 is stored in register 11, the read W1 of line 3 is stored in register 12, and so on. With word W1 of line 2 shifted into register 13, circuit CK
The 3×3 data consisting of the output data of registers 14 to 16 and the output data of each two stages of registers 11 to 13 is input to TI, and the circuit CKT2 receives the output data of three stages of registers 11 to 13. Similarly, 3x3 data is input to each circuit CKT3 to CKT7, and registers 11 to 1 are input to circuit CKT8.
The output data of the lower two stages of 3 and the output data of registers 17 to 19, 3×3 data, are input.

Therefore, the image data of pixels 1 to 3 of lines 2 to 4 surrounded by dotted lines in FIG. Image data from 7 to 9 is .

is input. If the registers 17 to 19 are not provided, the area including pixels 7 to 9 cannot be processed.

Processing for 3×3 pixels is performed in parallel by each circuit CKT1 to CKT8, and the 8 processing results are stored in register 2.
0 is written, and the circuit CKT is written to registers 21 and 22.
Boundary output data of the output of I, CKT8 is written. Each circuit CKTI to CKT8 is configured to perform logical operations such as addition and 2 multiplication corresponding to logical filter processing, or it uses 3×3 image data as an address and outputs a logical filter corresponding to the address input. This can be configured using the obtained read-only memory.

When the processing for word W1 of lines 6-8 is completed, the image data of pixel O of lines 9-17 (LW2) is written to the register 14, and at that point, the image data of pixel O of lines 9-17 (LW2) is written to the register 14;
This means that the image data of pixel 0 of 8 remains in registers 15 and 16. Also, the image data of pixel 9 of lines 9 to 17 (LW2) is written to register 17, and at that point, the image data of pixel 9 of line 7.8 is written to register 18.
It remains at ゜19. Also, the image data of word W1 of line 9 is written to register 11, and the image data of line 7 at that time is written to register 11.
．． The image data of word W1 of 8 is stored in register 12.13.
remains. Therefore, it becomes possible to process word W1 on lines 7-9.

When the processing for word W1 on the last line is completed,
Word W2 of lines 1-8 is processed, in which case register 14 is filled with lines 1-8 (LWI
) is written as boundary data,
Pixel 17 of lines 1 to 8 (LWI) is stored in register 17.
image data is written as boundary data.

Through the above-mentioned processing, nine pieces of image data are sold out from the image memory in word units, and logical filter processing such as noise removal, contour extraction, direction code detection, etc. is performed by parallel processing, and the processing results are transferred to the register 20 in word units. Output.

FIG. 4 is a block diagram of main parts of another embodiment of the present invention,
This example shows the case of histogram creation, and CKT9
CKTI is a circuit consisting of an adder circuit or an encoder that calculates the sum of "1" (black pixels) of one word of image data.
0 is a circuit consisting of an adder circuit or an encoder corresponding to pixels of one word of image data, 23 is a register, and the same reference numerals as in other FIG. 2 indicate the same parts.

FIG. 5 is an explanatory diagram of a histogram, showing vertical and horizontal histograms for "mountains" of characters. The sum of "1" (black pixels) of one word of image data shifted to the register 12 in FIG.
A horizontal histogram is created by adding the contents of lines correspondingly.

In addition, the image data shifted to the register 13 is transferred to the circuit CK.
By adding bitwise by T10, outputting the addition result via the register 23, and accumulating bitwise, a vertical histogram is created. Therefore, it is possible to simultaneously obtain histograms in the vertical and horizontal directions by word-by-word processing.

Note that the circuit CKT9. CKTIO has registers 11~
Any of the outputs of 13 may be added, and it is also possible to create a histogram in parallel with the above-mentioned logical filter processing such as contour extraction. Also, this shows the case where one word is 8 bits, and the circuits CKTI to CKTI
Depending on the bit configuration of O, it is also possible to process 16 bits to 32 bits as one word. Also circuit CKTI
~CKTIO functionality can also be implemented by a processor.

Furthermore, it is possible to perform logical filter processing not only on binary image data but also on multi-valued image data using similar means.

〔Effect of the invention〕

As explained above, the present invention shifts the image data read from the image memory I in units of words to the shift register 2 in units of words, reads out the boundary data in units of words and shifts it to the shift register 3.4, The output data of each stage of each shift register 2, 3.4 is processed in parallel by the arithmetic processing unit 5, and logical filter processing such as noise removal 1 contour extraction, direction code detection, and histogram creation is performed on a word-by-word basis. Since parallel processing is possible in accordance with the bit configuration of the processing function, there is an advantage that high-speed image processing can be realized.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the principle of the present invention, Fig. 2 is a block diagram of main parts of an embodiment of the invention, Fig. 3 is an explanatory diagram of continuous control of the image memory, and Fig. 4 is another embodiment of the invention. FIG. 5 is a block diagram of a main part of the system, and FIG. 5 is an explanatory diagram of a histogram. 1 is an image memory, 2.3.4 is a shift register, 5 is an arithmetic processing unit, 6 is a register, 11 to 23 are registers, CK
TI to CKTIO are circuits.

Claims (1)

[Scope of Claims] A shift register (2) for shifting image data read in words from the image memory (1) in words; and a shift register (2) for shifting image data read in words from the image memory (1) in units of words; Shift registers (3) and (4) that read and shift data from the image memory (1) in word units, and output data of each stage of the shift registers (2), (3), and (4) are processed in parallel. an arithmetic processing unit (5) to perform the calculation, and a register (5) that stores the output data of the arithmetic processing unit (5).
6) A high-speed image processing circuit comprising: