JPS62259470A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62259470A
JPS62259470A JP10201286A JP10201286A JPS62259470A JP S62259470 A JPS62259470 A JP S62259470A JP 10201286 A JP10201286 A JP 10201286A JP 10201286 A JP10201286 A JP 10201286A JP S62259470 A JPS62259470 A JP S62259470A
Authority
JP
Japan
Prior art keywords
layer
wirings
layers
wiring
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10201286A
Other languages
Japanese (ja)
Inventor
Kenji Hinode
憲治 日野出
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP10201286A priority Critical patent/JPS62259470A/en
Publication of JPS62259470A publication Critical patent/JPS62259470A/en
Pending legal-status Critical Current

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  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE:To prevent a defect such as an electromigration or the like from occurring by providing aluminum alloy wirings which contain an element for forming a compound with a silicon as an additive, and interposing the nitride of a transition metal between the wirings and a silicon substrate. CONSTITUTION:An insulating film 11 is formed on an Si substrate 10 formed with a diffused layer 17, a hole is opened at electrode 15, sequentially covered with layers 16, 12-14, and the layers 14, 13, 12, 16 are successively etched. Here, the layers 12, 14 are Al2%-Si alloy layer, and TiN, ZrN of the layer 16 are formed by reactive sputtering method of Ti or Zr in mixture gas of N2 gas. Thus, it can effectively prevent a defect such as electromigration due to miniaturization of wirings, and also prevent the wirings from reacting with Si at the electrodes.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置に係り、特に高信頼度、高耐熱性の
電極配線を有する半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having highly reliable and highly heat-resistant electrode wiring.

〔従来の技術〕[Conventional technology]

近年、半導体装置の微細化が進むにともなって半導体装
置の配線幅も著しく小さくなり、その結果、エレクトロ
マイグレーションなど、多くの問題が発生するようにな
った。
In recent years, as the miniaturization of semiconductor devices has progressed, the wiring width of semiconductor devices has become significantly smaller, and as a result, many problems such as electromigration have started to occur.

このような問題を解決するため、たとえば特公昭55−
31619など、多くの方法が提案されている。
In order to solve such problems, for example,
Many methods have been proposed, such as No. 31619.

しかし、これら従来の方法は電極部不良などの発生を効
果的に防止するのが困難であった。
However, with these conventional methods, it is difficult to effectively prevent the occurrence of electrode defects.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

本発明の目的は、上記従来の聞届を解決し、断線、短絡
の恐れが少なく、高い信頼性を有する微細な電極配線を
有する半導体装置を提供することである。
SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a semiconductor device having fine electrode wiring that is less likely to be disconnected or short-circuited and has high reliability.

〔問題点を解決するための手段〕[Means for solving problems]

」−記[1的を達成するために、本発明は、/Ml中に
シリサイドを形成し得ろ金属を添刀口してエレクトロマ
イグレーションなどを防止したAQ系配線層を設けると
ともに、]−記Ap、系配線層と、81基板又はシリ(
iイド等の電極入りとの間に電極)トマからのSjの」
二昇を防止するλりを介在させて電極と配線の反応を防
止し、」−記金属の添加にともなって発生する障害を防
止するものである。
[In order to achieve the first objective, the present invention provides an AQ-based wiring layer in which electromigration is prevented by adding a metal capable of forming silicide in /Ml, and system wiring layer and 81 substrate or silicon (
Between the electrodes of i-id, etc.) Sj's from Thomas
A reaction between the electrode and the wiring is prevented by intervening a λ layer which prevents secondary rise, thereby preventing troubles that occur with the addition of metals.

〔作用〕[Effect]

AQ中に含まれる18等シリサイドを形成する金);A
元素は、特にAQ中の粒界を多く拡散するとともに、A
 Q、中に添加されているSiと化合してシリサイドを
形成し、粒界を通じたAQ原子の拡散移動を抑制する。
Gold that forms the 18th grade silicide contained in AQ); A
In particular, the elements diffuse a lot through the grain boundaries in AQ, and
Q combines with Si added therein to form silicide, suppressing the diffusion and movement of AQ atoms through grain boundaries.

このシリサイド形成時に、AQ配線がSi基板に直接接
触していると、基板からSiを吸上げてしまうが、配線
の下に設けた、TjN等熱的に安定な高隔点金属窒化物
層によって、基板からのSi吸い上げを防止するもので
ある。
If the AQ wiring is in direct contact with the Si substrate during this silicide formation, Si will be sucked up from the substrate, but due to the thermally stable high point metal nitride layer such as TjN provided under the wiring, Si will be drawn up from the substrate. , which prevents Si from being sucked up from the substrate.

第2図から明らかなように、層】6を設けない試料では
、400℃の熱処理でも性能を保ち得ない。一方層16
を設けた試料では少なくとも500℃までの熱処理に耐
えることができ、特に層16が、200 n rnと厚
い場合には、550℃の熱処理にも耐え得る。従って、
層16を設ければ半導体プロセスにおける熱処理温度(
高々500℃)では十分な信頼性があると判断できる。
As is clear from FIG. 2, the sample without layer 6 cannot maintain its performance even after heat treatment at 400°C. One layer 16
Samples provided with this can withstand heat treatment up to at least 500°C, and in particular, when layer 16 is as thick as 200 nm, they can also withstand heat treatment up to 550°C. Therefore,
By providing the layer 16, the heat treatment temperature (
500° C.), it can be judged that there is sufficient reliability.

層]6は加工の面からは薄いほど好都合であるが、薄い
ほど耐熱性が下がるため、実際は両者の兼ね合いで膜F
[を決めるのが望ましい。層16の材料としてTi、N
、ZrNを本実施例では示したが、]4N、TaN等他
の遷移金属窒化物も熱力学的に安定であるため、同様の
効果を持つ。また実用上、電極部の電気特性を望ましい
ものとするため、層16とSiとの間に、例えばシリサ
イド等を設けても良い。
The thinner the layer 6 is, the better it is from the processing point of view, but the thinner the layer, the lower the heat resistance, so in reality, the film F is
It is desirable to determine [. Ti, N as the material of layer 16
, ZrN are shown in this example, but other transition metal nitrides such as ]4N and TaN are also thermodynamically stable and therefore have similar effects. Moreover, in order to make the electrical characteristics of the electrode portion desirable in practice, for example, silicide or the like may be provided between the layer 16 and Si.

〔発明の実施例〕[Embodiments of the invention]

以下、実施例をもって本発明を説明する。 The present invention will be explained below with reference to Examples.

実施例1 第1図に示す構造の試料を作製し耐熱性を検討した。こ
の試料は拡散層17(深さ0.;3μm)を形成したS
j基板10上に絶縁膜ノヴ11を形成し、電極部15に
おいて、開口部を穿った後、層16゜1.2,13.1
4を順次、スパッタ法にて被着させ1通常のフォトエツ
チング工程によって1層14.13,12.16を順次
エツチングしたものである。層】2.及び】4は、共に
A 0.2%Sj合金層(厚さ各々500nm)である
。λ・116はTiN、ZrNの2種類1層13はT 
a 。
Example 1 A sample having the structure shown in FIG. 1 was prepared and its heat resistance was examined. This sample is an S layer with a diffusion layer 17 (depth 0.3 μm)
j After forming the insulating film knob 11 on the substrate 10 and drilling an opening in the electrode part 15, the layers 16°1.2, 13.1 are formed.
The layers 14, 13 and 12, 16 were sequentially deposited using a sputtering method, and layers 14, 13 and 12, 16 were sequentially etched using a normal photo-etching process. Layer】2. and ]4 are both A 0.2% Sj alloy layers (each 500 nm thick). λ・116 is of two types: TiN and ZrN, 1 layer 13 is T
a.

Tjの2種類を組合わせ、第1表に示すような、5種類
の試料を作製した。試料#3は、M416を設けなかっ
たものである。層]6のTiN。
Five types of samples as shown in Table 1 were prepared by combining two types of Tj. Sample #3 was not provided with M416. Layer] 6 TiN.

ZrNは、Arガス、N2ガスの混合気体中でのTiも
しくはZrの反応性スパッタ法により形成した。以上の
ようにして作製した試料を、水素雰囲気で熱処理し、拡
散層17上に形成されているダイオードの逆耐圧を約5
0ケの試料についてを調定し不良率を算出した。熱処理
は、温度400℃から50℃間隔で、試料を各温度に1
時間保持した。第2図に結果を示す。
ZrN was formed by reactive sputtering of Ti or Zr in a mixed gas of Ar gas and N2 gas. The sample prepared as described above is heat treated in a hydrogen atmosphere, and the reverse breakdown voltage of the diode formed on the diffusion layer 17 is approximately 5.
The defective rate was calculated for 0 samples. The heat treatment was performed at 50°C intervals starting from 400°C, and the sample was heated once at each temperature.
Holds time. Figure 2 shows the results.

第1表 実施例2 実施例1と同様の工程を経て製造した#1゜#2および
#3配線部分(長さ1圃1幅1.3μm)を用いて、通
電試験(250℃、電流密度1×106A/cd)を実
施した。第2表に、各試料の配線構造と、平均寿命(配
線20本のうち半数の10本が断線するまでの時間)と
を示す。#3の従来配線に比べ、#1,2の構造の配線
では、数10倍の長寿命化が達成されているのに対し窒
化物層16を有さない試料#3は、平均寿命がはるかに
短いことが確認された。
Table 1 Example 2 Using #1, #2 and #3 wiring parts (length 1 field 1 width 1.3 μm) manufactured through the same process as Example 1, current conduction test (250°C, current density 1×106 A/cd). Table 2 shows the wiring structure of each sample and the average lifespan (time until half of the 20 wirings, or 10 wirings, break). Compared to the conventional wiring #3, the wiring with the structure #1 and #2 has a lifespan several ten times longer than that of the conventional wiring #3, whereas the average lifespan of sample #3, which does not have the nitride layer 16, is much longer. was confirmed to be short.

第  2  表 〔発明の効果〕 上記のように、本発明によれば、配線の微細化にともな
うエレクトロマイグレーションなどの障害は効果的に防
止され、かつ配線と、Siとの電極部での反応も防止さ
れるので、高集積度を有する半導体装置として、極めて
有用である。
Table 2 [Effects of the Invention] As described above, according to the present invention, problems such as electromigration caused by miniaturization of wiring can be effectively prevented, and reactions between the wiring and Si at the electrode portion can also be prevented. This is extremely useful as a semiconductor device with a high degree of integration.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の断面図、第2図は、本発明
の効果を示す曲線図である。 10・・・Si基板、11・・・絶縁膜層、12・・・
AQ。 Si層、13−Ta、Ti等高融点金属層、14・・・
AQ、Si層、15・・・電極部、16・・・TjN。 ZrN等窒化物層、17・・・拡散層。
FIG. 1 is a sectional view of an embodiment of the present invention, and FIG. 2 is a curve diagram showing the effects of the present invention. 10... Si substrate, 11... Insulating film layer, 12...
AQ. Si layer, 13-High melting point metal layer such as Ta, Ti, 14...
AQ, Si layer, 15...electrode portion, 16...TjN. Nitride layer such as ZrN, 17...diffusion layer.

Claims (1)

【特許請求の範囲】[Claims] 1、シリコンとの化合物を形成する元素を添加元素とし
て含むアルミニウム合金配線をそなえ、少なくとも、上
記配線とシリコン基板の間に遷移金属の窒化物の層が介
在されていることを特徴とする半導体装置。
1. A semiconductor device comprising an aluminum alloy wiring containing as an additive element an element that forms a compound with silicon, and at least a layer of transition metal nitride is interposed between the wiring and the silicon substrate. .
JP10201286A 1986-05-06 1986-05-06 Semiconductor device Pending JPS62259470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10201286A JPS62259470A (en) 1986-05-06 1986-05-06 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10201286A JPS62259470A (en) 1986-05-06 1986-05-06 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62259470A true JPS62259470A (en) 1987-11-11

Family

ID=14315849

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10201286A Pending JPS62259470A (en) 1986-05-06 1986-05-06 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62259470A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0283978A (en) * 1988-09-20 1990-03-26 Nec Corp Semiconductor device
JPH02238621A (en) * 1989-03-10 1990-09-20 Oki Electric Ind Co Ltd Formation of alloy wiring
US5972786A (en) * 1992-01-21 1999-10-26 Sony Corporation Contact hole structure in a semiconductor and formation method therefor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0283978A (en) * 1988-09-20 1990-03-26 Nec Corp Semiconductor device
JPH02238621A (en) * 1989-03-10 1990-09-20 Oki Electric Ind Co Ltd Formation of alloy wiring
US5972786A (en) * 1992-01-21 1999-10-26 Sony Corporation Contact hole structure in a semiconductor and formation method therefor

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