JPS62256461A - Pin grid array - Google Patents

Abstract

PURPOSE:To expand the gap between inner leads of adjacent circuits by a method wherein multiple pins are projected from the surface of a substrate whereon semiconductor chips are mounted while multiple layers of circuit bodies electrically connecting semiconductor chips to pins are provided on the substrate simultaneously connecting respective pins to one circuit body. CONSTITUTION:Circuits connecting a semiconductor chip 1 to respective pins 3 to be mounted on a substrate 2 are made on the substrate 2 by laminatedly fixing multilayer circuit bodies 4a-4c on the substrate 2. The circuit bodies 4a-4c can be formed by e.g. insulators 13a-13c respectively provided with circuits 12a-12c in the radial state. In the respective circuit bodies 4a-4c, pin holes 10 are perforated at the positions of land parts of respective circuits 12a-12c. When the substrate 2 is molded out of a resin molding material, the multiple circuit bodies 4a-4c with respective circuits 12a-12c can be simultaneously assembled into the substrate 2.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a pin grid array in an IC packeno or the like.

"Background technology" Increasing the functionality of elements in semiconductor packages such as ICs,
To address issues such as an increase in the number of I10s due to higher density and shorter lead lengths due to higher speeds, a pin grid is installed on the back side of the board on which the chip is mounted to serve as pins for electrical connection to the outside. Arrays (abbreviated as PGA) have been put into practical use. This pin grid 7-ray uses the entire back surface of the board to protrude a large number of pins, and the pins can be inserted into sockets or through holes provided on the device's mounting board (motherboard). , it can be attached to the motherboard.

That is, as shown in FIG. 15, the substrate 2 has a thickness of, for example, 1.
A circuit 12 is provided on the surface of the substrate 2, and a pin hole 8 drilled in the substrate 2 has a diameter of 0 or 5. A large number of pins 3 are fixed in a protruding state from the substrate 2 by press-fitting the heads of the pins 3 having a size of about 11 ml, thereby creating a pin grid array A.

In order to electrically connect the semiconductor chip 1 and each pin 3 in the pin grid array 8 formed in this manner, circuits 12 are formed radially on the substrate 2 as shown in FIG. This is done by connecting each pin 3 to each circuit 12 and performing wire bonding between the inner lead portion 7, which is the end of each circuit 12 facing the semiconductor chip 1, and the semiconductor chip 1.

However, if the number of pins 3 increases with the increase in the number of I10, the number of circuits 12 will also increase.
As the number of circuits 12 increases in this way, the interval d between the inner lead portions 7, which are the ends to be connected to the semiconductor chip 1, becomes extremely narrow as shown in the f:tfJ7 diagram. Therefore, due to the limits of mechanical ability, forming the circuit 12 and processing such as wire bonding become extremely difficult, and problems arise in which the wires come into contact with each other. Therefore, in order to widen the interval between the inner lead parts 7, the inner lead parts 7 are set back relative to the semiconductor chip 1. This increases the distance between the two wires and requires the use of long wires, resulting in the problem of contact between the wires and a delay in the speed of electrical propagation.

[Object of the Invention] The present invention has been made in view of the above points, and provides a pin grid array that can ensure wide spacing between inner leads of a circuit without the need to set the circuit back relative to a semiconductor chip. The purpose is to provide the following.

[Disclosure of the Invention 1 The pin grid array according to the present invention has a large number of pins 3 protruding from the surface of the substrate 2 on which the semiconductor chip 1 is mounted, and the semiconductor chip 1 and the pins 3 are electrically connected. A plurality of circuit bodies 4 at 4 b, 4 c are provided on the substrate 2, and each pin 3 is connected to one circuit body 4 at A.
By forming a circuit by providing a plurality of layers of circuit bodies 4a, 4b, 4c, each circuit body 4a, 4b
, 4c, it is possible to ensure a large interval between the inner leads @7 formed in the inner leads 7, and the present invention will be described in detail below with reference to examples.

Fig. 3 (of course not to scale) shows one embodiment of the present invention, in which the substrate 2 is made as a molded product by molding a synthetic resin molding material by injection molding, transformer 7T molding, etc. be done. When molding the base 2 in this way, a large number of pins 3 are attached to the base 2 in parallel by insert molding so that the bases of the pins 3 are embedded in the base 2. Since the pin 3 can be attached by insert molding in this way,
The work of drilling holes in the substrate 2 and press-fitting the pins 3 into the holes becomes unnecessary. The synthetic resin constituting the substrate 2 may include thermosetting resins such as phenol, epoxy, silicone, and polyimide, polyphenylene sulfide,
Thermoplastic resins such as polysal-7one, polyether sulfone, and poly-7-lyl sulfone can be used.

It is preferable to use epoxy resin because of its proven reliability, and the latter thermoplastic resin from the viewpoint of flexibility, mechanical strength, and heat resistance. It is formed with a circular cross section, and at its base, which becomes the head, there are a pair of circular guards 24, 2ζ, C kan e + 10, 7. n
To dimension the pin 3, set the pin 3 in the mold, inject resin molding material into the mold by injection molding, transfer molding, etc., and insert the base of the pin 3 into the substrate 2. be able to. At this time, the lower flange 25 of the pin 3 functions to position the set of the pin 3 in the molding die, and is also embedded in the upper flange 241i of the pin 3 [2]. 25 is embedded with its lower surface exposed from the lower surface of the substrate 2. By embedding the pins 24 and 25, the base of the pin 3 is firmly held within the substrate 2, and the pull-out strength of the pin 3 is increased. If this can be increased, it is possible to prevent the pin 3 from wobbling.

Further, a circuit connecting the semiconductor chip 1 mounted on the substrate 2 and each pin 3 is formed on the substrate 2, but in the present invention, the circuit is formed by stacking and attaching a plurality of layers of circuit bodies 4a+4b14c to the substrate 2. will be carried out. Circuit body 4
Examples of a, 4b, and 4c include an insulator 13a provided with circuits 12a, 12b, and 12c radially, respectively.
, 13b, 13c, each circuit body 4 at 4 b, 4 c is provided with a pin hole 10 at the position of the land portion 9 of the circuit 12av1.2b, 12c, as shown in FIG. The pin holes 10 are provided in the respective circuit bodies 4 a, 4 b, and 4 c so as to be shifted in position, and corresponding pin holes 10 are provided in the respective circuit bodies 4 at 4 b-4 c. are pin through holes 11 each having a diameter larger than the pin hole 10.
is perforated. and each circuit body 4 at 4 b,
4c circuits 12a, 12b, 12c are pin through holes 11
In addition, an opening 15 is provided in the center of each circuit body 4a, 4b, 4c to accommodate the semiconductor chip 1, and the circuit 12
a, 1213, 12 (!) This opening 15 (1111
The inner leads ff1S7, which are the end portions of the circuit bodies 4a and 4b+4c, are arranged at shifted positions in the vertically adjacent circuit bodies 4a, 4b+4c. Circuit 12a+12b+1
When 2c is formed of a copper circuit, the surface of this inner lead portion 7 is plated with gold for wire bonding.

When attaching the plurality of circuit bodies 4a+4b+4c having the circuits 12a, 12b, and 12c to the substrate 2, they can be incorporated into the substrate 2 at the same time when the substrate 2 is molded with a resin molding material. That is, the pin holes 11 and 11 of the circuit bodies 4a and 4b are formed above the pin hole 10 of the circuit body 4c.
However, each circuit body 4 at
4b and 4c are overlapped, and in this state, pass the base of the pin 3 through the pin hole 10 of each circuit body 4a, 4b+4C, and insert each circuit body 4 & 4 into the upper collar 24 of each pin 3.
b* 4 Set in the mold with c locked and held. Then, by injecting a resin molding material into the molding die, the pins 3 are insert-molded when molding the board 2, and at the same time, the circuit body is formed with the upper ends of the pins 3 contacting and connected to the circuits 12m, 12b, and 12c. 4 a, 4
b, 4c can be integrated by insert molding to be included within the substrate 2 as shown in FIG. Here, in order to hold each circuit body 4a, 4b, 4c in an overlapping state, each circuit body 411.4b,
4 Crocodile 24, 2 of each pin 3 according to the set height position of c
It is preferable to make the vertical spacing of 5 different and to match the height of f824 with the height position of circuit bodies 4 m, 4 b, 4 e, but if circuit bodies 4 a = 4 b, 4 c are 7 lexical If there is, circuit body 4 at 4 b, 4
It is possible to match the height of the collar 24 by bending c. In this case, the vertical distance between the collars 24 and 25 is equal! Pin 3 of IfLg can be used. In this way, when attaching the multi-layer circuit bodies 4a, 4b, 4c to the board 2, each circuit 12g, 12&, 12c
the upper circuit body 4 so that the inner lead part 7 of the
By placing a and 4 b in sequentially retreating positions, the circuit body 4 at 4 b+ 4 is arranged in a stepped manner.
c is mounted inside the board 2, and as shown in FIG. 4, the circuit body 4 at 411 adjacent to the upper board is
．． The inner leads g7 of the circuits 12a, 12b, and 12c of 4c are arranged in a shifted manner.

Here, insulators 13a, 13 provided with circuits 128° 12b, 12c forming circuit bodies 4a, 4b, 4c
As b and 13c, a plus epoxy wiring board, a glass polyimide wiring board, a lath polyester wiring board, a lasterme, a polyimide wiring film or sheet can be used. In this case, pin 3 and circuits 12a, 12b,
12c.

For this reason, it is preferable that the pin holes 10 be plated with through-holes, and furthermore, the pin holes 10 and the circuits 12a, 12b, 12
A recess 14 is formed in the substrate 2 so that the connection point with c is exposed, and a conductive material such as a low melting point metal alloy such as solder, a conductive paint, a conductive face, a conductive adhesive, etc. is formed in the recess 14. Pin 3 and circuit 12a+12bl
It is desirable to further secure the connection with l2c. In addition to these, the circuit bodies 48t 4 b, 4 c include copper, aluminum, 42 alloy (Ni-F with 42% Ni) fixed with a polyimide plate or film, etc.
It is also possible to use a glue board 7 frame or the like. This lead frame also has circuits 12a, 12b, 12c+
: It can be attached to the substrate 2 in the same manner as the provided insulators 13a, 13b, and 13c.

A semiconductor chip 1 such as an IC chip is mounted in the center of the substrate 2, and the semiconductor chip 1 and the circuits 12a of each circuit body 4a, 4b, 4c
, 12b, 12c, the semiconductor chip 1 and each pin 3 are connected to the circuit body 4a, 4b by performing wire bonding or the like between the inner leads 7 at the ends of the semiconductor chip 1 and each pin 3.

4c to complete the pin grid array A. During these mounting and bonding steps, the circuit bodies 4a*4b-4c are embedded in the base@2, and the circuits 12a, 12b, 12c
Mounting and punching operations can be easily performed without fear of damaging the surface. At this time, as shown in FIG. 4, the inner lead portions 7 of the circuits 12a, 12b, and 12c are arranged at shifted positions in each circuit body 4a, 4b, and 4c, and the circuits 12a+12
Even if the number of circuits b, 12c increases, each circuit body 4a, 4
In b, 4c, the gap between the adjacent inner lead parts 7 is formed to be large, so that there is no fear that the wires of the adjacent inner leads s7 will come into contact with each other, and the distance between the semiconductor chip 1 and the inner lead part 7 can be increased. Wire bonding can be applied to. Furthermore, even if the number of circuits increases with the increase in the number of pins 3, the circuits are connected to each circuit body 4a.
, 4 c, 4 b, and in each circuit body 4 at 4 b, 4 c, the circuit 12 a
, 12b, 12c, there is no need to narrow the distance between them.
Circuits 12a, 12b, 12 to circuit bodies 4a+4b, 4c
c can be easily formed. Further, in the inner lead portion 7, each circuit body 4a, 4b,
The end portion of 4c is stepped, and wire bonding can be performed not only from the periphery of the semiconductor chip 1 but also from inside.

In the pin grid array A formed in this manner, devices can be attached to a mounting board (motherboard) by inserting each pin 3 into a socket or through hole provided on the motherboard.

In the illustrated embodiment, in order to dissipate the heat generated by the semiconductor chip 1 mounted on the substrate 2, a heat sink 19 made of copper, iron, aluminum, ceramic, or the like having excellent thermal conductivity is attached. By setting this heat radiator 19 in a molding die, it can be provided by insert molding at the same time as the substrate 2 is molded with a resin molding material. Therefore, there is no need for man-hours such as drilling a hole in the substrate 2 to attach the heat sink 19 or fitting the heat sink 19 into the hole. When the heat radiator 19 is provided in this way, when the heat radiator 19 is formed of a metal material, gold plating for grounding the semiconductor chip 1 can be easily applied by electroplating by applying electricity. In addition, in the illustrated embodiment, the semiconductor chip 1 is connected to a substrate 2, which is the surface opposite to that from which the pins 3 are protruded.
Although the semiconductor chip 1 is mounted on the top surface, it may be mounted face-down on the bottom surface of the substrate 2, especially when a single heat sink is provided to dissipate heat. In this case, the semiconductor chip 1 is connected to the substrate 2.
When mounted on the bottom surface, the heat sink 19 is exposed on the top surface of the board 2, and the heat radiated from the heat sink 19 can be effectively radiated without being trapped between the board 2 and the motherboard. It will become an island.

[Effects of the Invention] As described above, in the present invention, a large number of pins protrude from the surface of a substrate on which a semiconductor chip is mounted, and a plurality of circuit bodies for electrically connecting the semiconductor chip and the pins are mounted on the substrate. In addition to providing layers, each pin is connected to one circuit body, so by using multiple layers of circuit bodies, even if a large number of circuits are formed, the circuits can be divided into a small number of circuit bodies. It is possible to increase the distance between the inner lead parts of adjacent circuits in each circuit body, making it possible to easily create a circuit body and to perform wire bonding without fear of wires coming into contact. The semiconductor chip and the circuit body can be connected by performing the following steps.

[Brief explanation of drawings]

Fig. 1 is a cross-sectional view of a part of an embodiment of the present invention, Fig. 2 is an exploded perspective view of a part of the circuit body used in the same, Fig. fjS3 is a reduced sectional view of the entire same as the above, and Fig. 4 is the same as the above. A perspective view of a part of
tjS5 is a reduced sectional view of the conventional example, FIG. 6 is a reduced plan view of the same, and FIG. 7 is a partial perspective view of the same. 1 is a semiconductor chip, 2 is a substrate, 3 is a pin, and 4a. 4b and 4c are circuit bodies.

Claims (1)

[Claims] (1) A large number of pins protrude from the surface of the board on which the semiconductor chip is mounted, and multiple layers of circuit bodies are provided on the board to electrically connect the semiconductor chip and the pins, and each pin is connected to one circuit body. A pin grid array characterized by consisting of: