JPS6225302B2 - - Google Patents
Info
- Publication number
- JPS6225302B2 JPS6225302B2 JP5199481A JP5199481A JPS6225302B2 JP S6225302 B2 JPS6225302 B2 JP S6225302B2 JP 5199481 A JP5199481 A JP 5199481A JP 5199481 A JP5199481 A JP 5199481A JP S6225302 B2 JPS6225302 B2 JP S6225302B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- signal
- circuit
- level setting
- composite signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04H—BROADCAST COMMUNICATION
- H04H40/00—Arrangements specially adapted for receiving broadcast information
- H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
- H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
- H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving
- H04H40/45—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving for FM stereophonic broadcast systems receiving
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D1/00—Demodulation of amplitude-modulated oscillations
- H03D1/22—Homodyne or synchrodyne circuits
- H03D1/2209—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders
- H03D1/2236—Decoders for simultaneous demodulation and decoding of signals composed of a sum-signal and a suppressed carrier, amplitude modulated by a difference signal, e.g. stereocoders using a phase locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Power Engineering (AREA)
- Stereo-Broadcasting Methods (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199481A JPS57166752A (en) | 1981-04-07 | 1981-04-07 | Frequency modulation stereophonic demodulator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5199481A JPS57166752A (en) | 1981-04-07 | 1981-04-07 | Frequency modulation stereophonic demodulator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS57166752A JPS57166752A (en) | 1982-10-14 |
| JPS6225302B2 true JPS6225302B2 (cg-RX-API-DMAC10.html) | 1987-06-02 |
Family
ID=12902402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5199481A Granted JPS57166752A (en) | 1981-04-07 | 1981-04-07 | Frequency modulation stereophonic demodulator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS57166752A (cg-RX-API-DMAC10.html) |
-
1981
- 1981-04-07 JP JP5199481A patent/JPS57166752A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS57166752A (en) | 1982-10-14 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4404430A (en) | FM Stereo demodulation circuit with voltage dividing and multiplexing techniques | |
| EP0132885B1 (en) | Multiplying circuit comprising switched-capacitor circuits | |
| WO1991007823A1 (en) | A phase-locked loop having a variable bandwidth | |
| CA1210084A (en) | Phase comparing circuit | |
| US5039889A (en) | Phase comparison circuit | |
| US6249158B1 (en) | Circuit arrangement for generating an output signal | |
| US4468632A (en) | Phase locked loop frequency synthesizer including fractional digital frequency divider | |
| JPH0628337B2 (ja) | 位相制御回路を具える電気回路装置 | |
| EP0413473A2 (en) | Voltage controlled oscillator | |
| JPS6225302B2 (cg-RX-API-DMAC10.html) | ||
| GB2174855A (en) | Wide range digital phase/frequency detector | |
| JPS5920302B2 (ja) | パイロツト信号打消回路 | |
| US4631694A (en) | Sine wave synthesizer | |
| EP0665651A2 (en) | Phased locked loop synthesizer using a digital rate multiplier reference circuit | |
| JPH0787376B2 (ja) | デルタ変調符号の復号装置 | |
| US5180987A (en) | DC-to-AC symmetrical sine wave generator | |
| JPS60233935A (ja) | 位相同期ループ | |
| JPS5825737A (ja) | Fmステレオ復調回路 | |
| JPS5825738A (ja) | Fmステレオ復調回路 | |
| JPS634737B2 (cg-RX-API-DMAC10.html) | ||
| JPS62132406A (ja) | 正弦波発生器 | |
| JP3539121B2 (ja) | ドットクロック生成回路 | |
| JPH01261027A (ja) | 周波数シンセサイザ装置 | |
| JPS6074973A (ja) | 同期式pwmインバ−タの基準信号作成回路 | |
| SU1548871A1 (ru) | Генератор качающейс частоты |