JPS62252948A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62252948A
JPS62252948A JP61097273A JP9727386A JPS62252948A JP S62252948 A JPS62252948 A JP S62252948A JP 61097273 A JP61097273 A JP 61097273A JP 9727386 A JP9727386 A JP 9727386A JP S62252948 A JPS62252948 A JP S62252948A
Authority
JP
Japan
Prior art keywords
bonding
semiconductor element
semiconductor
gap
lumps
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61097273A
Other languages
Japanese (ja)
Inventor
Noboru Kikuchihara
菊地原　昇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61097273A priority Critical patent/JPS62252948A/en
Publication of JPS62252948A publication Critical patent/JPS62252948A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Abstract

PURPOSE:To prevent the contamination of a semiconductor element and the yield of breakdown of bonding wire, by blocking the scattered lumps of a mounting and bonding material in a die bonding process, and completely preventing the movement of the lumps. CONSTITUTION:A narrow gap is formed by the inner walls of a semiconductor package 1 and a semiconductor element 3. A mounting and bonding material 2 is made to remin in the gap in a lump shape. The gap is buried with a heat resisting resin material 6 (silicon or polyimide synthetic resin). Then, the mounting and bonding material 2, which is yielded in a die bonding process and remains in the gap in the lump shape, is completely sealed in the resin material 6. Therefore, the lumps are not moved and rolled in the package hereinafter. Thus, thin metal wire for bonding is not damaged, and the semiconductor element is not contaminated.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体装置に関し、籍に混成集積回路装置に関
する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a semiconductor device, and more particularly to a hybrid integrated circuit device.

（従来の技術） 従来、半導体素子はボンディングに先立って収納容器内
にまず固層される。この工程は通常グイボンディングと
呼ばれる摩擦熱による金属の共晶化現象を利用した接着
技術によシ行なわれる。このダイボンディング技術によ
ると収納容器の基板上の素子接着領域には厚さ約３μｍ
の金（Ａｕ）メッキまたは金−白金（Ａｕ−Ｐｔ）の厚
膜がまず施され且つ４００℃程度に予備加熱される。こ
こで、シリコン半導体素子の裏面をこの基板の接着面上
に乗せて振動させると摩擦により局部的に例えば金−シ
リコン（Ａｕ−８ｉ）の共晶が生じ合金の生成が半導体
素子の裏面全体にまで進行することによりて接層が完了
する。この際、半導体素子の裏面にも金を魚屑しておく
と作業性が良くなる傾向をもつの”で、特に素子が大形
の場合には金−シリコン（Ａｕ−８ｉ）、　　金−ゲル
マニウム（Ａｕ−Ｇｅ　）または金−チタン（Ａｕ　−
Ｔ　ｉ　）等の合金箔を間にはさむことが多い。(Prior Art) Conventionally, semiconductor devices are first solidified in a storage container prior to bonding. This process is usually carried out by an adhesive technique called guibonding, which utilizes the eutectic phenomenon of metal due to frictional heat. According to this die bonding technology, the device bonding area on the substrate of the storage container has a thickness of approximately 3 μm.
A thick film of gold (Au) plating or gold-platinum (Au-Pt) is first applied and preheated to about 400°C. When the back side of a silicon semiconductor element is placed on the adhesive surface of this substrate and vibrated, for example, a gold-silicon (Au-8i) eutectic occurs locally due to friction, and the formation of an alloy spreads over the entire back side of the semiconductor element. The contact is completed by progressing until the end. At this time, workability tends to improve if gold scraps are also placed on the back side of the semiconductor element, especially when the element is large, gold-silicon (Au-8i) or gold-germanium. (Au-Ge) or gold-titanium (Au-
An alloy foil such as T i ) is often sandwiched between the two.

（発明が解決しようとする問題点） しかしながら、このダイボンディング工程では共晶合金
が生成されるまでの単振作業によりこれらマウント接層
材が塊状となって周囲に飛散する現象がおこる。一般に
基板が平板の場合にはこれらの塊は容易に取除けるが基
板が階段状に形成されその底面に半導体素子がマクント
される場合には容器内壁と素子とで挾まれる狭い空隙内
に落込むので完全には除去しきれないで残る。従って、
このままの状態でボンディングが行なわれ史に上蓋の加
熱封止が行なわれる亥、その一部は半導体素子面に付着
してこれを汚染し、また他の一部は塊状のま″ｆ、８器
内を転動しボンディング用金属細線を機械的に切断せし
める事故をおこすに至るＱ（発明の目的） 本発明の目的は、上記の情況に鑑み、容器内壁と半導体
素子とで挾まれる狭い空隙内に残留する団塊状のマウン
ト接層材がおこす半導体素子の汚染またはボンディング
粗金ｊ／Ｉ４ａ線の機械的切断等の問題点を解決した信
頼性高き半導体装置を提供することである。(Problems to be Solved by the Invention) However, in this die bonding process, a phenomenon occurs in which the mount contact layer material becomes lumpy and scatters around due to the single vibration operation until the eutectic alloy is generated. Generally, if the substrate is a flat plate, these lumps can be easily removed, but if the substrate is formed in a step-like manner and semiconductor elements are mounted on the bottom surface, they may fall into the narrow gap between the inner wall of the container and the elements. Because of the amount of water that is trapped, it cannot be completely removed and remains. Therefore,
If bonding is performed in this state and the top cover is heat-sealed, some of it will adhere to the semiconductor element surface and contaminate it, and the other part will remain in the form of lumps. In view of the above circumstances, an object of the present invention is to prevent the narrow gap between the inner wall of the container and the semiconductor element from rolling inside the container and mechanically cutting the thin metal wire for bonding. It is an object of the present invention to provide a highly reliable semiconductor device which solves problems such as contamination of semiconductor elements caused by lump-shaped mounting contact layer material remaining in the semiconductor device and mechanical cutting of bonding coarse gold j/I4a wires.

（発明の構成） 本発明の半導体装置は、下部部材の内壁面が底面に向か
い少なくも一つの段差を備えて階段状に形成される半導
体収納容器と、前記半導体収納容器の内壁底面上に固層
される半導体素子と、前記半導体素子の外部引出電極と
段差上面の外部端千尋出用メタライズ層とをそれぞれ接
続するボンディング粗金属細−と、前記半導体素子と段
差側壁とで挾まれる空隙内を埋める耐熱性樹脂部材とを
備えることを含む。(Structure of the Invention) A semiconductor device of the present invention includes a semiconductor storage container in which an inner wall surface of a lower member is formed in a stepped shape with at least one step toward the bottom surface, and a semiconductor storage container that is fixed on the bottom surface of the inner wall of the semiconductor storage container. A semiconductor element to be layered, a bonding coarse metal thin film that connects the external lead electrode of the semiconductor element and a metallized layer for external end aperture on the upper surface of the step, and a gap sandwiched between the semiconductor element and the side wall of the step. and a heat-resistant resin member to fill the area.

（問題点を解決するだめの手段） すなわち、本発明によれば、半導体収納容器の内壁と半
導体素子とで挾まれマウント接着材を団塊状に残留せし
める狭い空隙は耐熱性樹脂材（例えばシリコン系または
ボリミイド系の各合成樹脂）によって埋められる。この
埋立てはボンディング作業の前または後の何れであって
もよくその高さは半導体素子を超えないことが望ましい
。(Another Means to Solve the Problem) That is, according to the present invention, the narrow gap between the inner wall of the semiconductor storage container and the semiconductor element and in which the mounting adhesive remains in the form of a lump is filled with a heat-resistant resin material (for example, a silicone-based material). or bolimide-based synthetic resins). This reclamation may be done either before or after the bonding operation, and it is desirable that its height does not exceed the semiconductor element.

（作用） かかる構造では、ダイボンディング工程で生じ狭い空隙
内に団塊状をなして残留するマウント接層材は全て耐熱
性樹脂材によシ空ｌ！ｓＶ′３に閉込められる。従って
、これ以後容器内を転動してボンディング用金属細線を
傷つけたりまたは半導体素子を汚染せしめたりすること
はない。以下図面を参照して本発明の詳細な説明する０ （実施例） 図は本発明の一実施例を示す断面構造図である。(Function) In this structure, all the mount contact material that remains in the form of nodules in the narrow gap during the die bonding process is replaced by the heat-resistant resin material! It is confined to sV'3. Therefore, there is no possibility that the wire will roll around inside the container and damage the thin metal wire for bonding or contaminate the semiconductor element. DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to the drawings.(Embodiment) The drawings are cross-sectional structural views showing one embodiment of the present invention.

本冥施例によれば、内壁面が一つの段差を備え底面に向
かって階段状に形成された半導体収納容器のセラミ、り
下部部材１と、共晶化されたマウント接着材２によって
下部部材１の底面に固層された半導体素子３と、半導体
素子３の外部引出電極と段差上面の外部端子導出用メタ
ライズ層４とをそれぞれ接続するボンディング用金属細
線５と、半導体素子３と段差側壁とで挾まれる空隙内を
埋めるシリコン系樹脂材６とセラミック蓋部材７とを含
む。このシリコン系樹脂材６にはポリミイド系その他の
耐熱性樹脂材を代わりに用いてもよい０ここで、半導体
素子３は公知のダイボンディング技術によって固層され
る。この接着工程では従来と１Ｉ＝Ｊじ（（Ａｕ−８ｉ
　）糸の共晶合金がマウント接層・材２として用いられ
、時としてＧｅまたはＴｉを加えた３金鴎の共晶合金が
用いられる。しかし、何れの場合でも共晶合金を形成す
るまでに飛散したマウント接層材の団塊（荷に図示しな
い）はシリコン系樹脂材６の埋込みと共に狭い空隙内に
固められ以後収納容器内における転動その他の振舞いが
封じ込められる。According to this embodiment, the ceramic lower member 1 of the semiconductor storage container whose inner wall surface has one step and is formed in a step-like manner toward the bottom, and the lower member 1 is formed by the eutectic mounting adhesive 2. 1, a thin metal wire 5 for bonding that connects the external lead electrode of the semiconductor element 3 and the external terminal lead-out metallized layer 4 on the top surface of the step, and the semiconductor element 3 and the step side wall. It includes a silicon-based resin material 6 and a ceramic lid member 7 that fill the space sandwiched between the two. Polymide-based or other heat-resistant resin materials may be used instead of the silicon-based resin material 6. Here, the semiconductor element 3 is fixed by a known die bonding technique. In this bonding process, 1I=Jji ((Au-8i
) A eutectic alloy of thread is used as the mount interface material 2, sometimes a eutectic alloy of 3-metal with the addition of Ge or Ti. However, in any case, the lumps (not shown in the package) of the mount contact material that have been scattered until the eutectic alloy is formed are solidified in a narrow gap as the silicone resin material 6 is embedded, and are then rolled in the storage container. Other behaviors are contained.

（発明の効果） 以上詳細に説明したように、本発明によれば、ダイボン
ディング工程において飛散したマウント接層材の団塊は
シリコン系その他の耐熱性樹脂材によって出口が塞がれ
動きが完全に射しられるので、従来のμ口き半導体素子
の汚れまたはボンディング物の切断事故の発生を見るこ
となく信頼性の向上に大ぎな効果を奏することができる
。(Effects of the Invention) As described above in detail, according to the present invention, the movement of the nodules of the mount adhesive material scattered during the die bonding process is completely blocked by blocking the outlet with silicone-based or other heat-resistant resin materials. Since it is irradiated with rays of light, it is possible to significantly improve reliability without contaminating conventional μ-type semiconductor elements or causing accidents of cutting bonding materials.

【図面の簡単な説明】[Brief explanation of drawings]

図は本発明の一実施例を示す断面構造図である０１・・
・・・・セラミ、り下部部材、２・・・・・共晶化され
たマウント接層材、３・・・・・・半碍体素子、４・・
・・・・外部端予感出用メタライズ層、５・・・・・・
ボンディング用金属細極、６・・・・・・シリコン系樹
脂材、７・・・・セラミック蓋部材。 ｆパ−セラミック千り糧圀て ２・・・味晶Ａ６さｎｆ＜マウンＨ弛隨しズ３・−ギ番
祷、４子 ろ・−シリコン祭＃ｆＲｆ；ばThe figure is a cross-sectional structural diagram showing one embodiment of the present invention.
... Ceramic lower member, 2 ... Eutectic mount contact layer material, 3 ... Semi-insulator element, 4 ...
...Metallized layer for external edge prediction, 5...
Fine metal electrode for bonding, 6... Silicon resin material, 7... Ceramic lid member. f par-ceramic thousand grains 2... taste crystal A6 sanf

Claims (1)

【特許請求の範囲】[Claims] 下部部材の内壁面が底面に向かい少くとも一つの段差を
備えて階段状に形成される半導体収納容器と、前記半導
体収納容器の内壁底面上に固着される半導体素子と、前
記半導体素子の外部引出電極と段差上面の外部端子導出
用メタライズ層とをそれぞれ接続するボンディング用金
属細線と、前記半導体素子と段差側壁とで挾まれる空隙
内を埋める耐熱性樹脂部材とを備えることを特徴とする
半導体装置。A semiconductor storage container in which an inner wall surface of a lower member is formed in a step-like manner with at least one step toward the bottom surface, a semiconductor device fixed on the bottom surface of the inner wall of the semiconductor storage container, and an external drawer for the semiconductor device. A semiconductor characterized by comprising thin metal wires for bonding that respectively connect the electrodes and a metallized layer for leading out external terminals on the top surface of the step, and a heat-resistant resin member that fills the gap between the semiconductor element and the side wall of the step. Device.
JP61097273A 1986-04-25 1986-04-25 Semiconductor device Pending JPS62252948A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61097273A JPS62252948A (en) 1986-04-25 1986-04-25 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61097273A JPS62252948A (en) 1986-04-25 1986-04-25 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS62252948A true JPS62252948A (en) 1987-11-04

Family

ID=14187917

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61097273A Pending JPS62252948A (en) 1986-04-25 1986-04-25 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62252948A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974052A (en) * 1988-10-14 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Plastic packaged semiconductor device
US5889654A (en) * 1997-04-09 1999-03-30 International Business Machines Corporation Advanced chip packaging structure for memory card applications

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4974052A (en) * 1988-10-14 1990-11-27 Mitsubishi Denki Kabushiki Kaisha Plastic packaged semiconductor device
US5889654A (en) * 1997-04-09 1999-03-30 International Business Machines Corporation Advanced chip packaging structure for memory card applications

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