JPS6225269B2 - - Google Patents
Info
- Publication number
- JPS6225269B2 JPS6225269B2 JP54062992A JP6299279A JPS6225269B2 JP S6225269 B2 JPS6225269 B2 JP S6225269B2 JP 54062992 A JP54062992 A JP 54062992A JP 6299279 A JP6299279 A JP 6299279A JP S6225269 B2 JPS6225269 B2 JP S6225269B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- collector
- region
- contact
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000004888 barrier function Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 5
- 238000000151 deposition Methods 0.000 claims 1
- 239000002184 metal Substances 0.000 claims 1
- 230000007423 decrease Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 230000003071 parasitic effect Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/07—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common
- H01L27/0744—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration the components having an active region in common without components of the field effect type
- H01L27/075—Bipolar transistors in combination with diodes, or capacitors, or resistors, e.g. lateral bipolar transistor, and vertical bipolar transistor and resistor
- H01L27/0755—Vertical bipolar transistor in combination with diodes, or capacitors, or resistors
- H01L27/0761—Vertical bipolar transistor in combination with diodes only
- H01L27/0766—Vertical bipolar transistor in combination with diodes only with Schottky diodes only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Bipolar Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
- Bipolar Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明はシヨツトキ障壁ダイオード（以下SBD
と記す）で飽和を抑制しているトランジスタを用
いたバイポーラ型半導体集積回路に関するもので
ある。[Detailed Description of the Invention] The present invention relates to a shot barrier diode (hereinafter referred to as SBD).
The present invention relates to a bipolar semiconductor integrated circuit using transistors that suppress saturation.
一般に論理回路を構成する集積回路は、その入
力インピーダンスが高いほど、１つの出力端子に
たくさんの入力端子をつなげるので使用に際して
都合がよい。入力インピーダンスを表わすパラメ
ータの１つに高レベル入力電流（以下ＩIHと記
す）がある。これは、入力電圧が高レベル時に入
力端子から流れ込む電流値で、小さいほどよい。 In general, the higher the input impedance of an integrated circuit constituting a logic circuit, the more convenient it is for use because a large number of input terminals can be connected to one output terminal. One of the parameters representing input impedance is high level input current (hereinafter referred to as I IH ). This is the current value that flows from the input terminal when the input voltage is at a high level, and the smaller the value, the better.
SBDを用いているトランジスタ・トランジスタ
論理回路（以下SBD―TTLと記す）では入力ト
ランジスタのベースとコレクタ間にSBDをつなぐ
事によりＩIHを小さく抑えている。 In a transistor-transistor logic circuit using SBD (hereinafter referred to as SBD-TTL), I IH is kept small by connecting the SBD between the base and collector of the input transistor.
トランジスタ・トランジスタ論理回路では、そ
の入力トランジスタは入力信号数に応じた数のエ
ミツタを持つが、エミツタ電極相互間や、それと
ベース電極間に何本かの信号線を通したり、エミ
ツタ電極に接続する信号線をそのまま通過させた
りするために、エミツタ及びベース電極を直線状
に並べ、全体としてほそ長い形状にするのが配線
構成上都合よい。SBD―TTLの場合も同様で、
ほそ長い形状にする場合が多いが、こうすると、
ベース電極から遠い部分ではSBDの直列抵抗（Ｒ
D）が高くなりＩIHが増加する。この事情を図で
説明する。 In a transistor/transistor logic circuit, the input transistor has a number of emitters corresponding to the number of input signals, but some signal lines are passed between the emitter electrodes or between them and the base electrode, or connected to the emitter electrodes. In order to allow the signal line to pass through as is, it is convenient for the wiring configuration to arrange the emitter and base electrodes in a straight line and to form a generally long shape. The same is true for SBD-TTL,
It is often made into a long shape, but if you do this,
At the part far from the base electrode, the series resistance (R
D ) becomes higher and I IH increases. This situation will be explained with a diagram.
第１図は半導体基板上に通常のプロセスで作ら
れた例で、エミツタが２つある場合である。第２
図にその断面図を示す。図中の数字は第１図、第
２図とも共通で、半導体基板１には電気的に分離
されたコレクタ領域２、ベース領域３、コレク
タ・コンタクト層４、コレクタ・コンタクト電極
５、ベース電極６、酸化膜７、エミツタ領域１１
〜１２、エミツタ電極２１〜２２、通過する信号
線３１〜３３が設けられている。ベース電極６は
ベース領域上ではオーム接触し、コレクタ領域上
ではシヨツトキ障壁を形成している。第２図に
は、あわせてトランジスタの各部の寄生抵抗も示
してある（R1〜R7）。第３図には、１つのエミツ
タに注目した時の等価回路を示してある。同図の
Ｅ点が入力信号線につながり、Ｂ点は片方を最高
電位に接続した抵抗（Rg）に、Ｃ点は次段のト
ランジスタのベースにつながる。Ｄはベース電極
のSBDを表わす。 FIG. 1 shows an example of a device made on a semiconductor substrate using a normal process, in which there are two emitters. Second
The cross-sectional view is shown in the figure. The numbers in the figure are common to both FIG. 1 and FIG. , oxide film 7, emitter region 11
12, emitter electrodes 21 and 22, and passing signal lines 31 and 33 are provided. The base electrode 6 is in ohmic contact on the base region and forms a shot barrier on the collector region. FIG. 2 also shows the parasitic resistances of each part of the transistor (R 1 to R 7 ). FIG. 3 shows an equivalent circuit when focusing on one emitter. Point E in the figure is connected to the input signal line, point B is connected to the resistor (Rg) with one end connected to the highest potential, and point C is connected to the base of the next stage transistor. D represents the SBD of the base electrode.
このトランジスタＱがエミツタ１１に対応する
ものとすれば第３図の各抵抗値は次のようにな
る。 If this transistor Q corresponds to the emitter 11, the respective resistance values in FIG. 3 will be as follows.
ＲD＝R1＋R2 ＲB≒０ ＲC＝R6
ＲO＝R3＋R4＋R5 ……(1)
Ｑがエミツタ１２に対応するものとし、エミツ
タ１１の入力信号も高レベルとすれば、
ＲD＝R1＋R2＋R3 ＲB＝R7
ＲC＝R6 ＲO＝R4＋R5 ……(2)
となる。 R D = R 1 + R 2 R B ≒ 0 R C = R 6 R O = R 3 + R 4 + R 5 ...(1) Assume that Q corresponds to emitter 12, and the input signal of emitter 11 is also at a high level. For example, R D = R 1 + R 2 + R 3 R B = R 7 R C = R 6 R O = R 4 + R 5 (2).
Ｂ点より電流Igが流れ、Ｃ点にぬけるとき、大
部分の電流はＤ及びＲDを流れ、Ｑのベース・コ
レクタ接合には、ＤとＲDの電圧の和とほぼ等し
い順方向電圧がかかる（ＲB，ＲCに流れる電流は
十分少さいのでこれによる電圧降下は無視でき
る）。この順バイアスにより、コレクタ側からベ
ースに少数担体が注入され、それがエミツタに達
する事によりＩIHが流れる。 When current Ig flows from point B and passes through point C, most of the current flows through D and R D , and a forward voltage approximately equal to the sum of the voltages of D and R D appears at the base-collector junction of Q. (The current flowing through R B and R C is sufficiently small, so the voltage drop caused by this can be ignored.) Due to this forward bias, minority carriers are injected from the collector side to the base, and when they reach the emitter, I IH flows.
Ｑが理想トランジスタで、IgがＩIHに比べ十分
少さいとみなせる場合にはＩIHは次式で表わせ
る。 If Q is an ideal transistor and Ig is considered to be sufficiently smaller than I IH , I IH can be expressed by the following equation.
ＩIH＝ＩIH0×exp｛ＲDIg×ｑ／kT｝ ……(3)
ここでＩIH0はＲB＝ＲC＝ＲD＝０のときのＩIH
である。IgはＢ点に流入する電流で、Ｂ点と最高
電位の間につながる抵抗（Rg）によつて定ま
る。ｑは電子の電荷、ｋはボルツマン定数、Ｔは
絶対温度である。 I IH = I IH0 × exp {R D Ig×q/kT} ...(3) Here, I IH0 is I IH when R B = R C = R D = 0
It is. Ig is the current flowing into point B, and is determined by the resistance (Rg) connected between point B and the highest potential. q is the electron charge, k is Boltzmann's constant, and T is the absolute temperature.
(1)，(2)式から分るように、エミツタがベース電
極から離れているとＲDが高くなり、(3)式から、
ＩIHが増加するのが分る。現実的な例として、
R3＝60Ω、Ig＝1.2mAとすれば、ベース電極から
離れた側のＩIHは、ベース電極に近い側のＩIHに
比べ17倍にもなる。 As can be seen from equations (1) and (2), R D increases when the emitter is far from the base electrode, and from equation (3),
It can be seen that I IH increases. As a practical example,
If R 3 =60Ω and Ig = 1.2 mA, I IH on the side away from the base electrode is 17 times as large as I IH on the side close to the base electrode.
本発明の目的はベース電極から離れているエミ
ツタのＩIHを、配線の構成に支障なく、小さく抑
える事にある。 An object of the present invention is to suppress the I IH of the emitter located away from the base electrode to a small value without causing any problems in the wiring configuration.
本発明では、エミツタに関してベース電極の反
対側にも、もう１つのベース補助電極を設ける。
このベース補助電極は、正規のベース電極と同様
にベース領域とコレクタ領域にまたがつており、
ベース領域上ではオーム接触し、コレクタ側では
シヨツトキ障壁を形成している。 In the present invention, another base auxiliary electrode is also provided on the opposite side of the base electrode with respect to the emitter.
This base auxiliary electrode straddles the base region and collector region like a regular base electrode,
There is ohmic contact on the base region, and a shot barrier is formed on the collector side.
本発明では、このベース補助電極が、正規ベー
ス電極とも、他のどことも接続せず弧立している
事を特徴とする。ベース補助電極から一切の配線
が出ないので、これを設けても、他の配線の構成
に影響しない。 The present invention is characterized in that the base auxiliary electrode is not connected to the regular base electrode or to any other part and stands upright. Since no wiring comes out from the base auxiliary electrode, even if it is provided, it does not affect the configuration of other wiring.
次に弧立したベース補助電極を設ける事によつ
てＩIHが小さくできる事を図を以つて説明する。 Next, the fact that I IH can be reduced by providing an erect base auxiliary electrode will be explained with reference to the drawings.
第４図に本発明による入力用トランジスタ（エ
ミツタは２つ）の例を示す。第５図はその断面図
で、両図中の数字は第１図、第２図の場合と同じ
内容を示すが、新たに８のベース補助電極および
寄生抵抗R8，R9が加わる。８のベース補助電極
は、ベース領域上ではオーム接触し、コレクタ領
域ではシヨツトキ障壁を形成している。第６図に
はエミツタ１２に対応するトランジスタに注目し
た場合の等価回路を示す。D1は従来のSBD、D2
はベース補助電極のSBDを示す。各部の抵抗値
は、
ＲD1＝R1＋R2＋R3 ＲD2＝R9 ＲB＝R7
ＲC＝R6 ＲS＝R8 ＲO＝R4＋R5｝ (4)
となる。この等価回路から分るようにIgはD1と
D2に分流するため、第１にD1に流れる電流が減
少するのでＢ点Ｈ点間の電圧が下り、第２にD2
を流れる電流ＩD2はＲBを流れるので、Ｇ点Ｈ点
間の電圧はさらにＲB×ＩD2だけ低くなる。しか
し、現実的にはＲB≫ＲD1であるからＩD2はIgに
比べ十分小さいので、上述の第２の効果が支配的
となる。すなわち、トランジスタＱのベース・コ
レクタ接合の順方向バイアスはベース補助電極が
無い場合に比べＲB×ＩD2だけ小さくなり、その
分だけＩIHを小さくする。 FIG. 4 shows an example of an input transistor (two emitters) according to the present invention. FIG. 5 is a sectional view thereof, and the numbers in both figures indicate the same content as in FIGS. 1 and 2, but a base auxiliary electrode of 8 and parasitic resistances R 8 and R 9 are newly added. The base auxiliary electrode of 8 is in ohmic contact on the base region and forms a shot barrier on the collector region. FIG. 6 shows an equivalent circuit focusing on the transistor corresponding to the emitter 12. D 1 is traditional SBD, D 2
indicates the SBD of the base auxiliary electrode. The resistance values of each part are R D1 = R 1 + R 2 + R 3 R D2 = R 9 R B = R 7 R C = R 6 R S = R 8 R O = R 4 + R 5 } (4). As you can see from this equivalent circuit, Ig is D 1 and
Since the current is shunted to D 2 , first, the current flowing to D 1 decreases, so the voltage between points B and H decreases, and second, the current flowing to D 2 decreases.
Since the current I D2 flowing through R B flows through R B, the voltage between the G point and the H point further decreases by R B ×I D2 . However, in reality, since R B >>R D1 , I D2 is sufficiently smaller than Ig, so the second effect described above becomes dominant. That is, the forward bias of the base-collector junction of the transistor Q is reduced by R B ×I D2 compared to the case without the base auxiliary electrode, and I IH is reduced by that amount.
Ｑが理想トランジスタであり、ＲB≫ＲD1の場
合には
ＩIH＝I′IH0 exp〔｛ＲD1×Ig
−（ＲB＋ＲD1）I2｝×ｑ／kT〕 …(5)
となる。I′IH0はＲB≫ＲD1の関係を保つたままＲD
１＝０となつた場合のＩIHで、D2への分流I2は、
次式を満すような値である。 If Q is an ideal transistor and R B ≫ R D1 , then I IH = I′ IH0 exp [{R D1 ×Ig − (R B +R D1 ) I 2 }×q/kT] …(5) . I′ IH0 is R D while maintaining the relationship R B ≫ R D1 .
At I IH when 1 = 0, the shunt I 2 to D 2 is:
It is a value that satisfies the following formula.
ＶD1（Ig−I2）＋（ＲD1＋ＲS）（Ig−I2）
＝ＶD2（I2）＋（ＲB＋ＲD2）I2 …(6)
ここでＶD1（Ig−I2）は電流がIg−I2のときのD1
の電圧、ＶD2（I2）は、電流がI2のときのD2の電圧
である。 V D1 (Ig-I 2 ) + (R D1 + R S ) (Ig-I 2 ) = V D2 (I 2 ) + (R B + R D2 ) I 2 ...(6) Here, V D1 (Ig-I 2 ) is D 1 when the current is Ig−I 2
The voltage V D2 (I 2 ) is the voltage across D 2 when the current is I 2 .
(5)式から、ベース補助電極が無い場合（I2＝
０）に比べ、有る場合にはＩIHは、
１／exp｛（ＲB＋ＲD1）I2×ｑ／kT｝ ……(7)
倍になる事が分る。試算のために、現実的な値と
してIg＝1.2mA ＲD1＝130Ω，ＲS＝10Ω，ＲB＝
1400Ω，ＲD2＝240Ω，D1とD2の逆方向飽和電流
を４×10-11Aと１×10-11Aとすれば(6)式よりI2＝
107μＡとなり(7)式より、ベース補助電極が無い
場合に比べ約700分の１へと激減することにな
る。この例では、D2の面積をD1の４分の１にし
てあるが、このようにベース補助電極は小さくて
も効果が大きい。 From equation (5), when there is no base auxiliary electrode (I 2 =
0), when it exists, I IH is 1/exp {( RB + R D1 ) I 2 ×q/kT} ...(7) It can be seen that it becomes twice as large. For trial calculation, realistic values are Ig = 1.2mA R D1 = 130Ω, R S = 10Ω, R B =
1400Ω, R D2 = 240Ω, and the reverse saturation currents of D 1 and D 2 are 4×10 -11 A and 1×10 -11 A, then from equation (6), I 2 =
It becomes 107μA, which is a sharp decrease to about 1/700 compared to the case without the base auxiliary electrode, according to equation (7). In this example, the area of D 2 is set to one quarter of D 1 , but even if the base auxiliary electrode is small, it has a large effect.
これまでエミツタが２つの場合について説明し
てきたが、３つ以上の場合には、両端だけにエミ
ツタがある場合のＩIHが共に一定値より小さくな
るようにしてあれば、その間に入れたエミツタの
ＩIHはその一定値より小さくなる。 So far, we have explained the case where there are two emitters, but if there are three or more emitters, if I and IH are both smaller than a certain value when there are emitters at both ends, then the emitters inserted between them can be I IH becomes smaller than its constant value.
以上の説明は、複数入力のすべてが高レベルに
なつている場合についてのものであるが、いくつ
かが低レベルになつた場合にも同様な効果が得ら
れる。 The above explanation is for the case where all of the multiple inputs are at high level, but similar effects can be obtained even when some of the inputs are at low level.
次に本発明の具体例を示す。第１図に示す従来
のものと、第４図のベース補助電極のついたパタ
ーンの両方を含むSBD―TTLを通常の半導体集
積回路プロセスで作成した。ベース補助電極のな
い従来のもののＩIHは室温で６μＡ〜20μＡであ
つたのに対しベース補助電極をつけたもののＩIH
は0.02μＡ〜0.06μＡで大幅に改善された。（各
部寄生抵抗値は、現実的な数値例として示した値
に近いはずであるが、ＩIHの減少比が(7)式のよう
に700分の１にならず約300分の１に留まつている
のは、トランジスタの特性のうち特にベース・コ
レクタ接合部の特性が理想トランジスタと異なつ
ているためと思われる。）
本発明には以上説明したように、エミツタに関
してベース電極の反対側に弧立したベース補助電
極を設ける事により、配線の構成に影響すること
なく、高レベル入力電流ＩIHを大幅に減少できる
という効果がある。 Next, specific examples of the present invention will be shown. An SBD-TTL including both the conventional pattern shown in FIG. 1 and the pattern with base auxiliary electrodes shown in FIG. 4 was created using a normal semiconductor integrated circuit process. The I IH of the conventional model without the base auxiliary electrode was 6 μA to 20 μA at room temperature, while the I IH of the conventional model with the base auxiliary electrode
was significantly improved by 0.02 μA to 0.06 μA. (The parasitic resistance values of each part should be close to the values shown as realistic numerical examples, but the reduction ratio of I (This is thought to be because the characteristics of the transistor, especially the characteristics of the base-collector junction, are different from those of an ideal transistor.) As explained above, the present invention has an emitter on the opposite side of the base electrode. Providing the raised base auxiliary electrode has the effect of significantly reducing the high level input current I IH without affecting the wiring configuration.
第１図は従来の２エミツタ・トランジスタを示
す平面図、第２図はその断面図、第３図はその等
価回路である。第４図は本発明の２エミツタ・ト
ランジスタを示す平面図、第５図はその断面図、
第６図はその等価回路である。
１……半導体基板、２……コレクタ領域、３…
…ベース領域、４……コレクタコンタクト層、６
……ベース電極。
FIG. 1 is a plan view showing a conventional two-emitter transistor, FIG. 2 is a cross-sectional view thereof, and FIG. 3 is its equivalent circuit. FIG. 4 is a plan view showing a two-emitter transistor of the present invention, and FIG. 5 is a cross-sectional view thereof.
FIG. 6 shows its equivalent circuit. 1...Semiconductor substrate, 2...Collector region, 3...
... Base region, 4 ... Collector contact layer, 6
...Base electrode.
Claims (1)
第１および第２のコレクタコンタクトが離間して
設けられ、ベース領域に該ベース領域と接続する
第１および第２のベースコンタクトが離間して設
けられ、該第１のベースコンタクトと第１のコレ
クタコンタクトは互いに近接しかつ絶縁膜の同一
の開口によつて露出されたベースおよびコレクタ
領域に、コレクタ領域とはシヨツトキ障壁を形成
し、ベース領域とはオーム接触する金属を被着す
ることによつて形成され、前記第２のベースコン
タクトと該第１のコレクタコンタクトも同様に互
いに近接しかつ絶縁膜の同一の開口によつて露出
されたベースおよびコレクタ領域に前記金属を被
着することによつて形成され、前記第２のベース
コンタクトおよび第２のコレクタコンタクトは孤
立していることを特徴とする半導体装置。1 first and second collector contacts connected to the collector region are provided spaced apart on the collector region; first and second base contacts connected to the base region are provided spaced apart on the base region; The first base contact and the first collector contact are close to each other and have base and collector regions exposed by the same opening in the insulating film, forming a shot barrier with the collector region and an ohmic contact with the base region. base and collector regions formed by depositing a contacting metal, said second base contact and said first collector contact also being close to each other and exposed by the same opening in the insulating film; A semiconductor device, characterized in that the second base contact and the second collector contact are isolated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299279A JPS55154760A (en) | 1979-05-22 | 1979-05-22 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP6299279A JPS55154760A (en) | 1979-05-22 | 1979-05-22 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55154760A JPS55154760A (en) | 1980-12-02 |
| JPS6225269B2 true JPS6225269B2 (en) | 1987-06-02 |
Family
ID=13216366
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP6299279A Granted JPS55154760A (en) | 1979-05-22 | 1979-05-22 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55154760A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6762094B2 (en) * | 2002-09-27 | 2004-07-13 | Hewlett-Packard Development Company, L.P. | Nanometer-scale semiconductor devices and method of making |
-
1979
- 1979-05-22 JP JP6299279A patent/JPS55154760A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS55154760A (en) | 1980-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPS63136712A (en) | Differential comparator | |
| JPS6225269B2 (en) | ||
| JP3145455B2 (en) | Semiconductor integrated circuit device | |
| US4160986A (en) | Bipolar transistors having fixed gain characteristics | |
| US4051443A (en) | Differential amplifier | |
| JPH0355875A (en) | Integrated circuit with current detection | |
| JPH0418459B2 (en) | ||
| JPH01171281A (en) | Voltage drop control diode | |
| JPS586310B2 (en) | Hand tie souchi | |
| JP2778076B2 (en) | Measuring method for transistor collector stake | |
| JPS5855454Y2 (en) | constant current circuit | |
| JPS5810860A (en) | Semiconductor integrated circuit | |
| JP2705301B2 (en) | Constant current circuit | |
| JPS6062149A (en) | Semiconductor device | |
| JPH0381325B2 (en) | ||
| JP2996551B2 (en) | Current mirror circuit device | |
| JPH0117170B2 (en) | ||
| JPS58159366A (en) | Current mirror circuit | |
| JPS6294974A (en) | Semiconductor integrated circuit device | |
| JPS6384157A (en) | Semlconductor device | |
| JPS58211395A (en) | Bipolar ram | |
| JPS639410B2 (en) | ||
| JPH01101665A (en) | Transistor circuit | |
| JPS6119169A (en) | Multi-emitter transistor | |
| JPH0550164B2 (en) |