JPS6225269B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a shot barrier diode (hereinafter referred to as SBD).
The present invention relates to a bipolar semiconductor integrated circuit using transistors that suppress saturation.

In general, the higher the input impedance of an integrated circuit constituting a logic circuit, the more convenient it is for use because a large number of input terminals can be connected to one output terminal. One of the parameters representing input impedance is high level input current (hereinafter referred to as I _IH ). This is the current value that flows from the input terminal when the input voltage is at a high level, and the smaller the value, the better.

In a transistor-transistor logic circuit using SBD (hereinafter referred to as SBD-TTL), I _IH is kept small by connecting the SBD between the base and collector of the input transistor.

In a transistor/transistor logic circuit, the input transistor has a number of emitters corresponding to the number of input signals, but some signal lines are passed between the emitter electrodes or between them and the base electrode, or connected to the emitter electrodes. In order to allow the signal line to pass through as is, it is convenient for the wiring configuration to arrange the emitter and base electrodes in a straight line and to form a generally long shape. The same is true for SBD-TTL,
It is often made into a long shape, but if you do this,
At the part far from the base electrode, the series resistance (R
_D ) becomes higher and I _IH increases. This situation will be explained with a diagram.

FIG. 1 shows an example of a device made on a semiconductor substrate using a normal process, in which there are two emitters. Second
The cross-sectional view is shown in the figure. The numbers in the figure are common to both FIG. 1 and FIG. , oxide film 7, emitter region 11
12, emitter electrodes 21 and 22, and passing signal lines 31 and 33 are provided. The base electrode 6 is in ohmic contact on the base region and forms a shot barrier on the collector region. FIG. 2 also shows the parasitic resistances of each part of the transistor (R ₁ to R ₇ ). FIG. 3 shows an equivalent circuit when focusing on one emitter. Point E in the figure is connected to the input signal line, point B is connected to the resistor (Rg) with one end connected to the highest potential, and point C is connected to the base of the next stage transistor. D represents the SBD of the base electrode.

If this transistor Q corresponds to the emitter 11, the respective resistance values in FIG. 3 will be as follows.

R _D = R ₁ + R ₂ R _B ≒ 0 R _C = R ₆ R _O = R ₃ + R ₄ + R ₅ ...(1) Assume that Q corresponds to emitter 12, and the input signal of emitter 11 is also at a high level. For example, R _D = R ₁ + R ₂ + R ₃ R _B = R ₇ R _C = R ₆ R _O = R ₄ + R ₅ (2).

When current Ig flows from point B and passes through point C, most of the current flows through D and R _D , and a forward voltage approximately equal to the sum of the voltages of D and R _D appears at the base-collector junction of Q. (The current flowing through R _B and R _C is sufficiently small, so the voltage drop caused by this can be ignored.) Due to this forward bias, minority carriers are injected from the collector side to the base, and when they reach the emitter, I _IH flows.

If Q is an ideal transistor and Ig is considered to be sufficiently smaller than I _IH , I _IH can be expressed by the following equation.

I _IH = I _IH0 × exp {R _D Ig×q/kT} ...(3) Here, I _IH0 is I _IH when R _B = R _C = R _D = 0
It is. Ig is the current flowing into point B, and is determined by the resistance (Rg) connected between point B and the highest potential. q is the electron charge, k is Boltzmann's constant, and T is the absolute temperature.

As can be seen from equations (1) and (2), R _D increases when the emitter is far from the base electrode, and from equation (3),
It can be seen that I _IH increases. As a practical example,
If R ₃ =60Ω and Ig = 1.2 mA, I _IH on the side away from the base electrode is 17 times as large as I _IH on the side close to the base electrode.

An object of the present invention is to suppress the I _IH of the emitter located away from the base electrode to a small value without causing any problems in the wiring configuration.

In the present invention, another base auxiliary electrode is also provided on the opposite side of the base electrode with respect to the emitter.
This base auxiliary electrode straddles the base region and collector region like a regular base electrode,
There is ohmic contact on the base region, and a shot barrier is formed on the collector side.

The present invention is characterized in that the base auxiliary electrode is not connected to the regular base electrode or to any other part and stands upright. Since no wiring comes out from the base auxiliary electrode, even if it is provided, it does not affect the configuration of other wiring.

Next, the fact that I _IH can be reduced by providing an erect base auxiliary electrode will be explained with reference to the drawings.

FIG. 4 shows an example of an input transistor (two emitters) according to the present invention. FIG. 5 is a sectional view thereof, and the numbers in both figures indicate the same content as in FIGS. 1 and 2, but a base auxiliary electrode of 8 and parasitic resistances R ₈ and R ₉ are newly added. The base auxiliary electrode of 8 is in ohmic contact on the base region and forms a shot barrier on the collector region. FIG. 6 shows an equivalent circuit focusing on the transistor corresponding to the emitter 12. D ₁ is traditional SBD, D ₂
indicates the SBD of the base auxiliary electrode. The resistance values of each part are R _D1 = R ₁ + R ₂ + R ₃ R _D2 = R ₉ R _B = R ₇ R _C = R ₆ R _S = R ₈ R _O = R ₄ + R ₅ } (4). As you can see from this equivalent circuit, Ig is D ₁ and
Since the current is shunted to D ₂ , first, the current flowing to D ₁ decreases, so the voltage between points B and H decreases, and second, the current flowing to D ₂ decreases.
Since the current I _D2 flowing through R _B flows through R B, the voltage between the G point and the H point further decreases by R _B ×I _D2 . However, in reality, since R _B >>R _D1 , I _D2 is sufficiently smaller than Ig, so the second effect described above becomes dominant. That is, the forward bias of the base-collector junction of the transistor Q is reduced by R _B ×I _D2 compared to the case without the base auxiliary electrode, and I _IH is reduced by that amount.

If Q is an ideal transistor and R _B ≫ R _D1 , then I _IH = I′ _IH0 exp [{R _D1 ×Ig − (R _B +R _D1 ) I ₂ }×q/kT] …(5) . I′ _IH0 is R _D while maintaining the relationship R _B ≫ R _D1 .
At I _IH when ₁ = 0, the shunt I ₂ to D ₂ is:
It is a value that satisfies the following formula.

V _D1 (Ig-I ₂ ) + (R _D1 + R _S ) (Ig-I ₂ ) = V _D2 (I ₂ ) + (R _B + R _D2 ) I ₂ ...(6) Here, V _D1 (Ig-I ₂ ) is D ₁ when the current is Ig−I ₂
The voltage V _D2 (I ₂ ) is the voltage across D ₂ when the current is I ₂ .

From equation (5), when there is no base auxiliary electrode (I ₂ =
0), when it exists, I _IH is 1/exp {( _RB + R _D1 ) I ₂ ×q/kT} ...(7) It can be seen that it becomes twice as large. For trial calculation, realistic values are Ig = 1.2mA R _D1 = 130Ω, R _S = 10Ω, R _B =
1400Ω, R _D2 = 240Ω, and the reverse saturation currents of D ₁ and D ₂ are 4×10 ^-11 A and 1×10 ^-11 A, then from equation (6), I ₂ =
It becomes 107μA, which is a sharp decrease to about 1/700 compared to the case without the base auxiliary electrode, according to equation (7). In this example, the area of D ₂ is set to one quarter of D ₁ , but even if the base auxiliary electrode is small, it has a large effect.

So far, we have explained the case where there are two emitters, but if there are three or more emitters, if I _{and IH} are both smaller than a certain value when there are emitters at both ends, then the emitters inserted between them can be I _IH becomes smaller than its constant value.

The above explanation is for the case where all of the multiple inputs are at high level, but similar effects can be obtained even when some of the inputs are at low level.

Next, specific examples of the present invention will be shown. An SBD-TTL including both the conventional pattern shown in FIG. 1 and the pattern with base auxiliary electrodes shown in FIG. 4 was created using a normal semiconductor integrated circuit process. The I _IH of the conventional model without the base auxiliary electrode was 6 μA to 20 μA at room temperature, while the I _IH of the conventional model with the base auxiliary electrode
was significantly improved by 0.02 μA to 0.06 μA. (The parasitic resistance values of each part should be close to the values shown as realistic numerical examples, but the reduction ratio of _I (This is thought to be because the characteristics of the transistor, especially the characteristics of the base-collector junction, are different from those of an ideal transistor.) As explained above, the present invention has an emitter on the opposite side of the base electrode. Providing the raised base auxiliary electrode has the effect of significantly reducing the high level input current I _IH without affecting the wiring configuration.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a conventional two-emitter transistor, FIG. 2 is a cross-sectional view thereof, and FIG. 3 is its equivalent circuit. FIG. 4 is a plan view showing a two-emitter transistor of the present invention, and FIG. 5 is a cross-sectional view thereof.
FIG. 6 shows its equivalent circuit. 1...Semiconductor substrate, 2...Collector region, 3...
... Base region, 4 ... Collector contact layer, 6
...Base electrode.

Claims (1)

[Claims] 1 first and second collector contacts connected to the collector region are provided spaced apart on the collector region; first and second base contacts connected to the base region are provided spaced apart on the base region; The first base contact and the first collector contact are close to each other and have base and collector regions exposed by the same opening in the insulating film, forming a shot barrier with the collector region and an ohmic contact with the base region. base and collector regions formed by depositing a contacting metal, said second base contact and said first collector contact also being close to each other and exposed by the same opening in the insulating film; A semiconductor device, characterized in that the second base contact and the second collector contact are isolated.