JPS6294974A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the saturation characteristics of a transistor without increasing its circuit area, by extending an aluminum wiring of the common collector of a pre-stage transistor and a post-stage transistor to the vicinity of the base region of the pre-stage transistor to make a current pass via the aluminum wiring of low resistance. CONSTITUTION:The electric resistance of N<+> type buried layer 14 from a post- stage transistor 2 to a pre-stage transistor 1 becomes apparently small, because the resistance of an extended aluminum wiring of a collector part is connected in parallel. Generally, the resistance of the aluminum wiring of the collector part is sufficiently small as compared with that of the buried layer, so that only the resistance R1 of the buried layer 14 is dominant. That is, the saturation voltage of transistor 2 V CE2' is given by the relation V CE2'=I3R1+I4R2+VBE 2. The aluminum wiring of collector is extended to the vicinity of base region of the pre-stage transistor 1, so I4R2-0 and V CE2>V CE2' where V CE2' is the saturation voltage. Saturation characteristics of the post-stage transistor 2 can be improved, thereby.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to an np n
, ) This relates to a Darlington circuit composed of transistors in which the saturation characteristics of the transistors are improved without increasing the circuit area.

[Conventional technology]

Conventionally, in electrical circuits, n is used to obtain high current gain.
A Darlington circuit consisting of transistor 2 (hard pn) is often used, an example of which is shown in Figure 2. In this circuit, the collectors of the front and rear transistors 1.2 are common, and the emitter of the front transistor 1 is is connected to the base of the rear stage l fungistar 2.

Due to area constraints in the pattern layout of such a circuit, two transistors are formed on the same isolated island. An example of the arrangement is shown in FIG. In the figure, 5 is a collector common to the front and rear transistors, 6 is the base of the front transistor 1, 7 is its emitter, 9 is the base of the rear transistor 2, 10 is its emitter, 8 is an aluminum wiring for drawing out the emitter IO, Reference numeral 11 indicates aluminum wiring at the collector portion common to the front nine rear-stage transistors 1.2, and 17 indicates a collector all.

In this circuit arrangement, the aluminum wire 8 drawn out from the emitter 10 of the subsequent transistor 2 needs to be made large in consideration of the current density of aluminum. Therefore, the aluminum wiring 8 in the collector portion is placed close to the base 9 side of the subsequent transistor 2 due to restrictions on the circuit layout area. In addition, FIG. 4 shows a cross section along the line IV-IV in FIG. 3,
In the figure, 14 is an n-shaped buried layer, 15 is an epitaxial resistor from the base 6 of the front-stage transistor 1 to the n-shaped buried layer 14, and 16 is an epitaxial resistor from the front-stage transistor 1 to the rear-stage transistor 2.
This is the resistance of the n-shaped buried layer 14 up to .

In such a circuit, the saturation voltage VCF2 of the subsequent transistor 2 is equal to the saturation voltage VCE of the preceding transistor 1.
It is the sum of I and the voltage VBF2 between the base 9 and the emitter 10 of the subsequent transistor 2. i.e. VCE2-VCE
I+VBE2-(1). Also,
As shown in FIG. 3, when the aluminum wiring 11 for extracting the collector is placed on the base 9 side of the rear-stage transistor 2,
The saturation voltage V CEI of the front transistor 1 is determined by the current I3 flowing through the epitaxial resistor R1 from the base 6 of the transistor 1 to the n-shaped buried layer 14 and the n-shaped buried layer from the front transistor 1 to the rear transistor 2. 1
Using the current I4 flowing through the resistor R2 of 4, VCEI −
It can be expressed as I3 R1+T4 R2...(2).

Therefore, from equations (1) and (2), the latter transistor 2
The saturation voltage V CF2 is VCE2 = 13 R1+ I4 R2+VBE2
...(3).

[Problem that the invention seeks to solve]

Since the conventional semiconductor integrated circuit device is configured as described above, the saturation voltage of the latter-stage transistor 2 is determined by the n-shaped buried layer 14. The disadvantage is that the collector current of the preceding stage transistor 1 increases as the collector current increases.

The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a semiconductor integrated circuit device that can improve the saturation characteristics of a transistor without increasing the circuit area.

[Means for solving problems]

In the semiconductor integrated circuit device according to the present invention, the base portion of the front-stage transistor is made small, the lead-out aluminum wiring for the emitter portion of the rear-stage transistor is placed in the base portion of the front-stage transistor, and the space created by this is utilized. The common collector aluminum wiring of the front and rear transistors is extended to near the base region of the front transistor.

[Effect]

In the present invention, since the aluminum wiring of the common collector of the front and rear transistors is extended to the vicinity of the base region of the front transistor, the current flowing through the buried layer from the front transistor to the rear transistor is reduced from the buried layer. The current flows through the aluminum wiring, which has a sufficiently low resistance.
The resistance of the buried layer is only R1.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a plan view of a semiconductor S integrated circuit device according to an embodiment of the present invention, and in the figure, 6, 7, 9° 10 are the same as those in FIG. 3. 8 is the emitter lead-out aluminum wiring of the rear stage transistor 2, and 5 is the front and rear stage transistor 1.
2, 17 is a collector all, 11 is an aluminum wiring provided to cover this, and extends to the vicinity of the base 6 of the front stage transistor 1.

Next, the effects will be explained.

In this embodiment, the resistance of the n-type buried layer 14 from the rear-stage transistor 2 to the front-stage transistor 1 is apparently small because the resistance of the elongated aluminum wiring in the collector part is entered in parallel with this, and generally the resistance of the aluminum wiring in the collector part is Since the resistance of the buried layer 14 is sufficiently smaller than the resistance of the buried layer 14, only the resistance R1 of the buried layer 14 exists.

That is, the saturation voltage VCE2' of the transistor 2 derived from equation (3) is V CE2' -13R1+ 14 R2+VBE2・
... (4), and by extending the aluminum wiring of the collector to the vicinity of the base region of the front-stage transistor 1, I4R2 becomes 0, and its saturation voltage V CE2'
According to equation (4), V CE2' -13R1+VBE2 river (
5).

Therefore, the base 9 and emitter 10 of the transistor 2 in the subsequent stage
The voltage between them does not change even in the layout according to this example,
Since the epitaxial resistance R1 is also the same, Equation (3),
From formula (5), VCE2 > V CE2'...
- (6) is obtained, and the saturation characteristics of the transistor 2 in the subsequent stage can be improved.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, the aluminum wiring of the common collector of the front and rear transistors is extended to the vicinity of the base region of the transistor at the front stage, so that the circuit layout area is not increased.
This has the effect of improving the saturation characteristics of the transistor.

[Brief explanation of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of a Darlington circuit, and FIG. 3 is a plan view showing the structure of a conventional device constituting the circuit. FIG. 4 is a diagram showing a cross section taken along the line It/-IV. DESCRIPTION OF SYMBOLS 1... Front stage transistor, 2... Back stage transistor, 5... Common collector of front and rear stage transistors, 6...
...Base of front stage transistor, 7...Emitter of front stage transistor, 8...Aluminum wiring of emitter of rear stage transistor, 9...Base of rear stage transistor, 1
0... Emitter of subsequent stage transistor, 11... Aluminum wiring of common collector, 17... Collector all.

Claims (1)

[Claims] (1) In a semiconductor integrated circuit device in which the collectors of the front and rear stage transistors are provided in common and the emitter of the front stage transistor is connected to the base of the rear stage transistor, the aluminum wiring of the common collector is connected to both the front and rear stage transistors. A semiconductor integrated circuit device characterized in that the device is arranged close to a base region of a transistor.