JPS62252596A - Sense amplifier circuit - Google Patents

Abstract

PURPOSE:To attain high speed action by connecting a load which comes to be a high resistance at the time of starting the sensing to a bit line and comes to be a low resistance after that. CONSTITUTION:After the latch of a sense amplifier part is completed and the data are determined, a control voltage PHIc supplied to NMOS transistors NMS1 and NMS2 is made into a high voltage VH, on the other hand, a control voltage PHIc supplied to PMOS transistors PMS1 and PMS2 is made into the voltage to make smaller the on resistance of the phase reverse to the control voltage PHIc and respective CMOS switches are made into a low impedance condition RL which is respectively a low resistance. Consequently, between the sense amplifying part and the first and second bit lines BL1 and BL2, the charge is quickly shifted and at a high speed, the voltage of the bit line is controlled. Thus, the voltage is controlled by the electric potential after determination is executed by a latch action, and a secure and high speed control is executed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a sense amplifier circuit used for reading out signals stored and held in a memory device, etc., and particularly to a sense amplifier circuit that realizes high-speed operation.

[Summary of the invention]

The present invention realizes high-speed launch operation in a sense amplifier circuit configured with CMOS and sensing signals appearing on a bit line by connecting a load to the bit line that has a high resistance at the start of sensing and then becomes a low resistance. It is something.

[Conventional technology]

First, the configuration and operation of a conventional sense amplifier circuit will be explained with reference to FIGS. 4 and 5.

As shown in FIG. 4, the conventional sense amplifier circuit has a first bit line BLI and a second bit line connected to a capacitor for storing an information signal through an access transistor (not shown) of each memory cell. It performs a latching operation between the bit line BL2 and its configuration is as follows: PMO3I - the drain of transistor PM, and NMO3)
+ is connected to the first bit line BLI, and the drain of the PMOS transistor PM2 and the NMOS
Transistor NM! The drain of the second bit line B
Connected to L2. The first bit line BLl further connects the transistor P M (PMO3) and NMO3).
The second transistor NM is connected to the gate of the transistor NM.
The bit line BL2 is connected to the gates of the PMOS transistor PM and the transistor NM1 (NMO3).

Then, the PMOS transistor PM1. PM! The w111 voltages Φ, P are supplied to the respective sources of the NMOS transistors NM, NMt, and the control voltage Φ3N is supplied to the respective sources of the NMOS transistors NM, NMt.

In the conventional sense amplifier having such a circuit configuration, as shown in FIG.
A voltage of c/2 is supplied to the first bit line B.
The access transistor of the 0th order memory cell, to which the voltage of Vcc/2 is also supplied to LI and the second bit line BL2, becomes conductive in response to the selection signal of the word line, and depending on the capacity of the memory cell, the First bit line BLI
The voltage becomes Vcc/2+ΔVs, and only the potential Δvs of the first bit line increases. Here, the above control voltage Φ3F
, Φ□ are changed to VCC and O, respectively, PMOS
Transistor PM+ and NMO3I- transistor NM
2 has a smaller on-resistance, and PMO3
) transistors PMz and NMO3) and transistors NM each have a large on-resistance and perform a launch operation.

[Problem that the invention seeks to solve]

A conventional sense amplifier circuit has the above-described configuration and reads out information signals stored in each memory cell by a latch operation.

Incidentally, in a sense amplifier circuit that performs such a latch operation, there are demands for high-speed operation and reduction in power consumption, and among these demands, there is a demand for faster rough and chi operations themselves.

However, in the middle of the latch operation, the gate of each inverter is at an intermediate potential between vcc and 0.
There is a through current that flows from the PMO3) transistor PM to the NMOS transistor NMI, and a through current that flows from the PMO3) transistor PM to the NMOS transistor NM2. Since the charge is not injected into or extracted from the bit line, the launch operation is delayed.

On the other hand, if the size of the elements constituting each memory device is reduced, it is possible to increase the speed to some extent.

However, if the size of the element is reduced and miniaturized simply to increase speed, variations in the manufacturing process of the element will lead to malfunctions due to deterioration of sensitivity, which is an essential problem. It cannot be a solution to the problem.

Therefore, in view of the above-mentioned technical requirements, the present invention aims to provide a sense amplifier circuit that realizes high-speed operation.

[Means for solving problems]

The present invention provides a sense amplifier circuit configured with CMOS and configured to sense a signal appearing on a bit line, characterized in that a load which has a high resistance at the start of sensing and then becomes a low resistance is connected to the bit line. Solving the above problems.

[Effect]

The present invention provides control voltage Φ3? , Φ30 are changed to VCC and O, respectively, at the start of sensing, the load connected to the bit line is made to have a high resistance. Therefore, the movement of current from or to the bit line is suppressed, and therefore the latch operation can be performed at high speed in the sense amplifier section composed of two inverters or the like.

Further, after the latching operation in the sense amplifier section is performed at high speed by the load, the load is subsequently made to have a low resistance, and the bit line is controlled. At this time, the potential of the bit line is controlled using the potential determined by the latch operation of the sense amplifier section, so that it is controlled reliably and at high speed.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

A first embodiment of the sense amplifier circuit of the present invention has a circuit configuration made of CMOS as shown in FIG. For example, a first bit line BLI and a second bit line BL2, which are connected via an access transistor to a capacitor for storing information signals of a memory cell of a memory device such as DRAM, SRAM, or EEFROM, and have an equivalent capacitance C3, Yes, this first bit line BLI includes an NMOS transistor N M S + controlled by a control voltage Φ, and a PMO transistor PMS1 controlled by a control voltage Φ0'.
A so-called CMOS switch in which these are connected in parallel is connected as a load, and the control voltage Φ is connected to the second pinpoint line BL2. NMO controlled by 3) transistor NMS
A so-called CMOS in which t and a PMO3I transistor pMsz controlled by the control voltage ΦC' are connected in parallel.
A switch is connected as a load.

And the above NMO3) transistor NMSI and PMO
At the other end of the CMOS switch consisting of the 3+- transistor PMSL, which is connected to the first bit line BLI,
A connection line bz1 is provided, and this connection line bnl connects the transistors PM+ and N which constitute the sense amplifier section.
MO3) is connected to the output terminal of an inverter consisting of a transistor NM, and is also connected to the gate of a PMOS transistor PM constituting another inverter, and a gate of a transistor NM2 (NMO3I). In addition, the above NMOS
Transistor NMS! and PMO3) transistor PMS
The second bit line BL of the CMOS switch consisting of
The connection line b12 connected to the other end of the side connected to 2 is
PMOS transistor PM is connected to the output terminal of an inverter consisting of PMO3I-transistor PMt and NMO3I-transistor NMX, which constitute the sense amplifier section.

and NMO3I-- are connected to the gates of NMI and NMO3I, respectively.

In addition, the above PMO3) transistor P M +1. P M
A control voltage Φ8.2 is connected to the source side of the control voltage Φ8. is supplied, and
Above NMO3) Transistor N M1. The structure is such that control voltages Φ and H are supplied to the source side of N M z.

Next, the operation of the sense amplifier circuit of this embodiment having such a configuration will be explained with reference to FIG.

First, PMO3) transistor PM of the sense amplifier section,
A voltage of VCC/2 is supplied as the control voltage ΦSF+ΦS,l supplied to PMt and the NMOS transistors NM, NM, and the first and second bit lines BLI
, BL2 and the connection line b11. bz2 also has ■. ,
A voltage of /2 is supplied and a so-called precharge state is established. Then, the access transistor of the memory cell becomes conductive in response to the selection signal of the word line, and from the movement of the charge of the capacitance of the memory cell, for example, the first bit line B
The voltage of LI becomes vcc/2+ΔVs (on the contrary, when no charge is accumulated in the cell capacitance, the voltage becomes Vcc/2−ΔVs), and the potential of the first bit line becomes ΔVs (or −ΔVs).
only rises. Note that the second bit line BL is used for reference.

In this way, the potential of the first bit line is, for example, VCC/2+
ΔVs and the charge of the memory cell appears on the bit line, the above NMO3) transistors NMS, , N
Control voltage Φ supplied to MS2. is a voltage V that is at a certain intermediate level and increases the on-resistance,
On the other hand, the control voltages φ and ゛ supplied to the PMOS transistors PMS+ and PMSz are the control voltages Φ. It is assumed that the voltage is in reverse phase with the voltage and increases the on-resistance. Therefore, each MO3) transistor NMS, , NMSz
, PMS+, and PMS2 are each set to a high resistance state, and each CMOS switch is set to a high impedance state BR1I having a high resistance.

Next, at the time indicated by the broken line in FIG. The latch operation is started by changing the voltages to V cc/2 and 0, respectively. In the state after the start of latching in the sense amplifier section, each of the CMOS switches has a control voltage Φ. .

Φ,' is in a high impedance state R□, so the first and second bit lines BLI, BL2 do not affect the capacitance C8, and the connection lines b7!1. b1
2 is the main capacitance component, and therefore the time constant of the transient phenomenon can be reduced, the through current can be suppressed, and the latch operation of the sense amplifier section can be made faster.

Note that such a high-speed latch is shown in FIG. 2 by the potential of the connections vAb11°b12.

Next, after such high-speed latching is performed, or after the launch of the sense amplifier section is completed, or after the data is determined, the NMOS transistor NMS
The control voltage Φ supplied to I, NMS,. the high voltage V
, and on the other hand, the above PMO3) transistor PMS+,
Control voltage Φ supplied to PMSt. ′ is the control voltage Φ
, is set to a voltage that reduces the on-resistance of the opposite phase, and each of the above CMOS switches is set to a low impedance state RE, RL having a low resistance.

In this way, when each of the CMOS switches is set to the low impedance state RL having a low resistance, the first and second bit lines BLl and BL2 are controlled based on the data determined by the sense amplifier section. Therefore, charges are rapidly transferred between the sense amplifier section and the first and second bit lines BLI and BL2, and the voltage of the bit lines is controlled at high speed.

FIG. 2 shows this situation, and as the resistance of the CMOS switch is lowered, the connection line b11. b12 and the above first
It is shown that, although the potentials of the connection lines bzt and be2 fluctuate somewhat due to the movement of charges between the second focus lines BLI and BL2, it quickly converges.

At this time, since the control is performed based on the determined data of the sense amplifier section, the control is performed reliably, and therefore there is no need to sacrifice sensitivity when increasing the speed.

Next, a second embodiment of the present invention will be described.

The second embodiment of the present invention, as shown in FIG.
A resistor R3 is connected in parallel to a CMOS switch consisting of an NMOS transistor NMS, and a resistor R8 is connected in parallel to a CMOS switch consisting of an NMOS transistor NMS and a PMOS transistor PMSz. In FIG. 3, the same reference numerals are used for the same parts as those shown in FIG.

The configuration of this second embodiment has a first bit line BL1 and a second bit line BL2, similar to that shown in FIG. , and NMO3) transistor NMS, and resistor RS
+ is connected to one end of the CMOS switch connected in parallel, and the second bit line BL2 is connected to PMO3) transistor PMS2 and NMOS transistor PMS2.
It is connected to one end of a so-called CMOS switch in which z and a resistor R3° are connected in parallel. Then, as in the first embodiment, the NMO3) transistors NMS, , N
A control voltage Φ is supplied to MS, while the above PMO
3) The transistors PMS+ and PMSi are provided with a control voltage φ having a phase opposite to the control voltage φ. It is connected so that ゛ is supplied.

Similarly to the first embodiment, the PMOS transistor PMS, the NMOS transistor NMSL, and the resistor R
A connecting line b11 is connected to the CMOS-switch in which 3 and 3 are connected in parallel, and this connecting line b7! ■ are PMOS transistors PM, NM that constitute the sense amplifier section
P which is connected to the output terminal of the inverter consisting of the OS transistor NM1 and constitutes another inverter.
MOS transistor PMt and NMO3) transistor N
Connected to the gate of M2. In addition, the above NMOS transistor NMSt and PMO3) transistor PMS,
A tangent M line b12 connected to a CMOS switch 7 consisting of a resistor R5 and a resistor R5 is connected to a PM
O3) Transistor PM and NMOS transistor NMt
connected to the output terminal of an inverter consisting of P
MOS transistor PM, and NMO3I-transistor N
MI is connected to each gate.

In addition, the above PMO3) transistors P M l, P M
Control voltages Φ and P are supplied to the source side of 2, and
The structure is such that control voltages Φ and H are supplied to the sources of the NMOS transistors NM, NMt.

The sense amplifier circuit of the second embodiment has resistors R3, R3!, connected in parallel to each CMOS switch in the first embodiment. Therefore, by using V(() and 0, which are easy to supply in a CMOS circuit, there is no need to create a new intermediate voltage such as voltage VL, and it is possible to directly create a predetermined high impedance state RN. can.

Regarding its operation, the connection line b11. Only bffi2 becomes the main capacitance part, making it possible to speed up the latch operation of the sense amplifier section. After that, the CMOS switch having resistors RS + and RS z is made to have a low resistance, and the bit line is controlled. be exposed. At this time, the potential of the bit line is controlled using the potential determined by the latch operation of the sense amplifier section, so that it is controlled reliably and at high speed.

Furthermore, as another embodiment, the present invention can be applied to a so-called shared sense amplifier circuit used to reduce the capacitance of the pin I-line.
This can be easily achieved by changing the timing of switches of transistors formed for division and controlling the transistors so that the resistance becomes high at the start of sensing and then becomes low resistance.

〔Effect of the invention〕

In the sense amplifier circuit of the present invention, at the start of sensing, the load connected to the bit line has a high resistance. Therefore, the movement of current from or to the bit line is suppressed, and therefore the latch operation in the sense amplifier section can be performed at high speed. After a latching operation in the sense amplifier section that is performed at high speed by the load, the potential of the bit line is controlled with the potential determined by the latching operation of the sense amplifier section,
Reliable and high-speed control is achieved.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an example of the sense amplifier circuit of the present invention, FIG. 2 is a time chart for explaining an example of its operation, and FIG. 3 is a circuit diagram showing another example of the sense amplifier circuit of the present invention. It is a diagram. Further, FIG. 4 is a circuit diagram showing an example of a conventional sense amplifier circuit, and FIG. 5 is a time chart for explaining the operation of the conventional example. BLl, BL2...Bit line bzl, b12...Connection line PMS, , PMS2...PMOS transistor (load) NMSl, NMS2...NMo5 transistor (negative charge)

Claims (1)

[Scope of Claims] A sense amplifier circuit configured with CMOS and configured to sense a signal appearing on a bit line, characterized in that a load having a high resistance at the start of sensing and a low resistance thereafter is connected to the bit line. circuit.