JP3478917B2 - Sense amplifier circuit - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a current sense type sense amplifier circuit used in a semiconductor memory device.

[0002]

2. Description of the Related Art A memory data read circuit such as a read-only semiconductor memory (ROM or EPROM) is required to read data at high speed, and a current sense type sense amplifier circuit for detecting a minute current flowing in a memory cell is used. To be FIG. 7 shows a conventional sense amplifier circuit of this kind, which is also shown in Japanese Patent Laid-Open No. 1-165095.

In the conventional example shown in FIG. 7, a current sense type sense amplifier circuit S0 and "1" and "0" of a memory cell M0 are provided.
And a reference voltage output circuit (reference amplifier circuit) SR which gives a reference voltage VREF for determining.

In FIG. 7, PMOS transistors P2 and P3 whose sources are both connected to a power supply VCC and whose gates are commonly connected to form a current mirror, and a drain on the side of the PMOS transistor P2 whose gate and drain are short-circuited are input. An NMOS transistor N1 whose drain and source are respectively connected to the terminal DI0, one input terminal to the input terminal DI0, the other input terminal to the sense amplifier activation control terminal SAN, and an output terminal to the gate of the NMOS transistor N1. NOR gate G5 connected respectively, NMOS transistor N3 whose drain and source are respectively connected to the drain and reference potential (GND) of PMOS transistor P3, and PMOS transistor P
3 is connected to the connection node A of the drain of the NMOS transistor N3 and the drain of the NMOS transistor N3.
A sense amplifier circuit S0 is configured by an inverter G1 whose outputs are connected to T, respectively. The memory cell M0 is selected by decoding the address signal applied to the memory module and selecting the word line W0 and the data line D0. NMOS connected in series between the input terminal DI0 of the sense amplifier circuit S0 and the data line D0
Data line selection switches Y1 and Y2 composed of transistors
Is a selection switch for selectively connecting the data line to the sense amplifier circuit S0 according to the address signal. The reference amplifier circuit SR side has the same configuration as the sense amplifier circuit S0 side, but the NMO in the sense amplifier circuit S0 is the same.
The NMOS transistor corresponding to the S transistor N3 is composed of two transistors N6 and N7. The NMOS transistors N6 and N7 are of the same size as the NMOS transistor N3, and each gate and drain are short-circuited to produce a reference voltage VREF.
And connect to the gate of NMOS transistor N3
It forms a current mirror with the MOS transistor N3. The other MOS transistors P2 and P8 in the sense amplifier circuit S0 and the reference amplifier circuit SR,
P3 and P9 and N1 and N8 have the same size.

Although there are ion implantation type and floating gate type memory cells, "1", "1" depending on the magnitude of the threshold voltage Vth of the memory cell due to process or electrical writing or non-writing operation. Data discrimination of 0 "is performed.

The sensing operation in FIG. 7 will be described below.

In FIG. 7, reference amplifier circuit S
The memory cell MR connected to the R side is in the non-write state, that is, the threshold voltage Vth is low, and the word line connected to the gate is in the selected state.
R is always on. Also, the data line selection switch Y1
R and Y2R are always maintained in the ON state. Therefore, when the low level sense activation signal is applied to the sense amplifier activation control terminal SAN, the input terminal DIR is initially at the low level, the output of the NOR gate G6 becomes High, the NMOS transistor N8 is turned on, and the PMOS transistor P8 transfers to the memory cell MR. An electric current flows toward it.
This current is transmitted to the PMOS transistor P9 side by the current mirror configuration. If the mirror ratio is 1, a current similar to the current of the memory cell MR becomes the drain current of the PMOS transistor P9 and the NMOS transistor N9.
6 and N7. Furthermore, the NMOS transistor N6
N7 is an NMOS transistor N in the sense amplifier circuit S0
3, the current is transmitted to the NMOS transistor N3 side because it forms a current mirror with the current mirror 3, but since the mirror ratio is 1/2, the current of the NMOS transistor N3 is 1 / l of the drain current of the PMOS transistor P9. Two
become. The NOR gate G6 and the NMOS transistor N8 form a voltage clamp circuit that suppresses a rise in the potential of the data line, and are provided to clamp the potential of the data line to about the logic threshold voltage VLT of the NOR gate G6. That is, when the NMOS transistor N8 is turned on, the PMOS transistor P8 charges the data line floating capacitance CR due to the wiring capacitance and the diffusion capacitance of the memory cell to raise the data line potential, but the data line potential becomes the logic threshold voltage VLT of the NOR gate G6. When it reaches N
The output of the OR gate G6 becomes Low, and the current of the NMOS transistor N8 is narrowed down to prevent further increase in potential.
The same applies to the NOR gate G5 and the NMOS transistor N1 in the sense amplifier circuit S0.

First, assuming that the memory cell M0 is not written, that is, the threshold voltage Vth is low, the memory cell M0 is turned on by selecting the word line W0 (applying a high level to the word line W0). The data line D0 is selected by the data line selection switches Y1 and Y2 formed of NMOS transistors, and the reference amplifier circuit S
Similarly to the R side, when a low level sense activation signal is applied to the sense amplifier activation control terminal SAN, the NMOS transistor N1 is turned on and a sense current flows from the PMOS transistor P2 to the memory cell M0. This current is transmitted to the PMOS transistor P3 side by the current mirror configuration, and becomes the same drain current as the PMOS transistor P8 in the reference amplifier circuit SR if there is no characteristic variation in the memory cells M0 and MR. On the other hand, since the NMOS transistor N3 is set to 1/2 the drain current of the PMOS transistor P3 as described above, the operating point of the node A in FIG. 7 becomes a voltage close to the VCC power supply voltage, that is, a high level, and the voltage is passed through the inverter G1. As a result, "0" output is obtained at the sense amplifier output terminal SOUT. Next, the memory cell M0 is programmed, that is, the threshold voltage V
When th is high, the memory cell M0 is in the OFF state even if the word line W0 is selected. In this case, when the NMOS transistor N1 turns on, first the PMOS transistor P
The floating capacitance C0 of the data line is charged by 2 and the potential of the data line rises. Due to the rise of the data line potential, the NMOS
As the transistor N1 turns off, the PMOS
The transistor P2 also turns off, and the drain current of the PMOS transistor P3 also becomes zero. Since the NMOS transistor N3 is in the ON state, the operating point of the node A is L
It becomes the ow level and "1" output is obtained at the sense amplifier output terminal SOUT via the inverter G1.

[0009]

In the above-mentioned conventional example, in order to discriminate between "1" and "0" data in the memory cell M0, the reference memory circuit SR uses the dummy memory cell MR.
Is used to generate the reference voltage VREF. Since the dummy memory cell MR is in the ON state as described above, the current always flows through the PMOS transistors P8 and P9 in the reference amplifier circuit SR, and the invalid current is consumed on the side of the reference amplifier circuit SR which is not related to the original sense operation. ing. If a plurality of dummy memory cells and reference amplifier circuits are provided in the semiconductor memory device in order to absorb manufacturing variations in memory cell characteristics, the influence on the current consumption is further increased. Further, providing the dummy memory cell and the reference amplifier circuit also has an invalid layout region in the semiconductor memory device, which is disadvantageous in terms of chip area.

Further, in order to reduce the influence of characteristic variations between the PMOS transistors P2 and P8 on the sense amplifier circuit S0 side in order to speed up the rising of the data line and in comparing the current with the dummy memory cell MR. In addition, the current driving capability of the PMOS transistor P2 (and P8) must be ensured, so that the non-writing (Vth
When reading a small memory cell, a sense current determined from the memory cell side flows between the PMOS transistor P2 and the memory cell M0. Normal sense amplifier circuit S0
Is provided with a number of circuits according to the number of external data buses connected to the semiconductor memory device. For example, when the number of data buses is 16, 16 sense amplifier circuits are required to output sense data to each data bus at the same time. Therefore, the sense current is also 16 circuits, and the current consumption is greatly affected.

An object of the present invention is to provide the dummy memory cell,
To provide a current sense type sense amplifier which is advantageous in terms of integration with a simple circuit configuration by enabling "1" and "0" data discrimination without using a reference voltage source such as a reference amplifier circuit, and consumption current. It is to provide a current sense type sense amplifier capable of high-speed data reading while reducing the noise.

[0012]

A gate of an NMOS transistor N3, which has been used to determine a "1" or "0" decision level of sense data by eliminating a reference amplifier circuit and being connected to a reference voltage VREF in the past, is connected to a data line side ( Input terminal DI
0). PM that turns on the sense amplifier circuit and turns on for a predetermined period to precharge the data line
PM that constitutes the current mirror of the OS transistor P1
An NMOS transistor P5 that is provided in the gates of the OS transistors P2 and P3 and that suppresses the voltage rise of the data line is always on. A PMOS transistor P5 and an NMOS whose gate is connected to the input terminal DI0
It is controlled by the output of the load MOS type inverter including the transistor N2.

A current comparison with the reference side becomes unnecessary, and the PMOS transistor P1 for precharging is independently provided to supply a sense current.
It becomes unnecessary to secure the current capacity of the transistor P2, and the sense current flowing to the memory cell side during the sensing operation is set to P
It can be limited by the MOS transistor P2. In addition, the data line potential after precharging is held at the high level (clamp voltage) by holding the charge of the data line because the memory cell is off when the memory cell is written, and the memory cell is turned on when not written. Then, the charge on the data line is extracted and becomes the low level. Therefore, the NMOS transistor N whose gate is connected to the data line
Reference numeral 3 is ON when reading a written memory cell and OFF when reading a non-written memory cell. However, a certain finite time is required to extract the charge of the data line by the non-write memory cell, and the NMOS transistor N3
Can maintain the ON state, but the data line potential is above the load M.
Since it drops from about the logic threshold voltage VLT of the OS type inverter, its gate-source voltage VGS is small and the drain current is suppressed. On the other hand, the PMOS transistor P3, which is a load of the NMOS transistor N3, is the PMOS transistor P3 when reading the write memory cell.
And a load MOS type inverter output consisting of an NMOS transistor N2 whose gate is connected to the input terminal DI0 is L
Since the NMOS transistor N1 is turned off and the NMOS transistor N1 is turned off, the sense current of the PMOS transistor P2 does not flow, and thus the current does not flow to the PMOS transistor P3 that forms a current mirror with the sense current, and the PMOS transistor P3 is in the OFF state. At this time, since the NMOS transistor N3 is in the ON state as described above, the operating point of the PMOS transistor P3 and the NMOS transistor N3 becomes Low during the precharge period, and the reading of the write memory cell is completed at the same time when the precharge is completed. On the contrary, when reading a non-written memory cell, the output of the inverter becomes High, the NMOS transistor N1 is turned on, and the sense current flows through the PMOS transistor P2, whereby the PMOS transistor P3 side is also turned on. At this time, the NMOS transistor N3 is in the OFF state (or a state close to the OFF state).
Therefore, the operating points of the PMOS transistor P3 and the NMOS transistor N3 rapidly become High, and the reading of the non-written memory cell is completed.

As described above, the PM of the sense data judgment output section
Since the OS transistor P3 and the NMOS transistor N3 determine the decision output level by the exclusive operation, the PMO
The through current between the S-transistor P3 and the NMOS transistor N3 is small, so that a low-current consumption and high-speed determination output can be obtained.

Further, an NMO for suppressing the voltage rise of the data line
PM in which the gate of the S transistor N1 is always on
By controlling by the output of the load MOS type inverter consisting of the OS transistor P5 and the NMOS transistor N2 whose gate is connected to the input terminal DI0, the precharge current rises because the precharge can be started from the ON state of the NMOS transistor N1. Therefore, the precharge period can be shortened and the read time can be shortened.

[0016]

BEST MODE FOR CARRYING OUT THE INVENTION A first embodiment of the present invention will be described with reference to FIG.

In FIG. 1, PMOS transistors P2 and P3 forming a current mirror, a source on the side of PMOS transistor P2 whose gate and drain are short-circuited, and
PMOS that connects drain and source to VCC power supply and gate to sense amplifier start control terminal SAN
The drain of the transistor P4, the drain of the PMOS transistor P2, and the drain and the source of the NMOS transistor N1 which connect the drain and the source to the input terminal DI0 respectively, and the reference potential (hereinafter referred to as GND) of the NMOS transistor N1 are connected to the input. An NMOS transistor N2 whose gate is connected to the terminal DI0, and an NMOS
PM whose drain and source are connected to the gate of transistor N1 and VCC power supply, respectively, and whose gate is connected to GND
A drain and a source are connected to the drain and source of the OS transistor P5 and the PMOS transistor P3, respectively, and a drain and a source are respectively connected to the input terminal DI0 and the input terminal DI0, and a sense amplifier is connected. Start control terminal SA
An NMOS transistor N4 whose gate is connected to N, and P
The gates of the MOS transistors P2 and P3, the drain and the source are respectively connected to the VCC power supply, and the PMOS transistor P1 whose gate is connected to the precharge control terminal PREN and the drain of the PMOS transistor P3 are inputted to the sense amplifier output terminal SOUT. A sense amplifier circuit S0 is configured by the inverter G1 connected to the. The configuration of the memory cell M0 selection circuit (Y1, Y2) connected to the input terminal DI0 of the sense amplifier circuit S0 is the same as that of the conventional example of FIG.

Next, the sensing operation in this embodiment will be described with reference to FIG.
Will be explained.

FIG. 2 is a basic driving timing chart of the sense amplifier circuit of the present invention. First, when both the sense amplifier sounding control terminal SAN and the precharge control terminal PREN are at the high level, the sense amplifier circuit S0 is in the standby state. At this time, since the NMOS transistor N4 in the sense amplifier circuit S0 is in the ON state, the input terminal DI0 is at the GND level and the NMO
Data line selection switches Y1 and Y composed of S transistors
If the data line D0 is selected by 2, the data line D
0 also becomes the GND level. Further, since the NMOS transistors N2 and N3 whose gates are connected to the input terminal DI0 are in the OFF state and the PMOS transistor P5 is always in the ON state, the gate of the NMOS transistor N1 is biased to the VCC power supply voltage and the NMOS transistor N1 is turned ON. It is in a state. The PMOS transistors P1 and P4 are both in the OFF state, and the gate connection node PG of the PMOS transistors P2 and P3 is biased to the GND level by the NMOS transistor N1. Therefore, the PMOS transistor P3 is turned on, the drain connection nodes A of the PMOS transistor P3 and the NMOS transistor N3 are biased to the VCC power supply voltage, and the sense amplifier output terminal SOUT outputs "0". In this standby state, there is no direct current path between the VCC power supply and GND, and the current consumption is zero.

Next, the sense amplifier start control terminal SAN is set to the low level and at the same time the precharge control terminal PR is set.
The data line is precharged by inputting a one-shot pulse that is at Low level only for a predetermined period to EN. When the sense amplifier activation control terminal SAN becomes low level, the NMOS transistor N4 is turned off, the PMOS transistor P4 is turned on, and the sense amplifier circuit S0 is activated. However, since the PMOS transistor P1 is turned on at the same time, the node PG is biased to the VCC power supply voltage. Done PMO
S transistors P2 and P3 are precharge control terminals PR
It is in the OFF state while EN is at the Low level. On the other hand, N
Since the MOS transistor N1 is in the ON state from the standby state, the PM is turned on by turning on the PMOS transistor P1.
The data line D0 is supplied from the VCC power source through the gate and drain of the OS transistor P2 and the NMOS transistor N1.
A current flows into the data line D0 and the data line D0 is precharged.
The potential of the data line D0 rises due to precharge, but N
When the threshold voltage Vth of the MOS transistor N2 is reached, the NMOS transistor N2 turns on and the data line D0
The gate voltage of the NMOS transistor N1 is lowered as the potential rises, and the current of the NMOS transistor N1 is reduced. As a result, the potential rise of the data line D0 is suppressed, and eventually P
The potential of the data line D0 is held near the logic threshold voltage VLT of the inverter composed of the MOS transistor P5 and the NMOS transistor N2. At this time, since the NMOS transistor N3 is also turned on, the node A becomes low level and the precharge control terminal PR
The sense amplifier output terminal SOUT outputs "1" during the precharge period when EN is at the Low level.

The Lo of the precharge control terminal PREN
The w period, that is, the precharge period is set so that the precharge operation is completed within the precharge period based on the current setting of the data line capacitance C0 and the precharge PMOS transistor P1, that is, the PMOS transistor P5.
The necessary and sufficient time is set to start the operation of the inverter including the NMOS transistor N2 and the NMOS transistor N2. For example, if the data line capacitance C0 is 2 pF, the current of the PMOS transistor P1 is 1 mA, and the inverter VLT is 1.5 V, the precharge period tWPRE is (2 pF / 1 mA) ×
The setting should be 1.5 V = 3 ns or more.
As described above, the precharge period may be a relatively short time, so that it can be generated from the sense amplifier activation control terminal SAN signal by using a gate delay as shown in FIG. Figure 3
, D1, D2, ... Are odd-numbered stages of delay inverters, and a one-shot pulse corresponding to the delay amount of the inverter can be obtained on the falling side of the sense amplifier start control terminal SAN signal. Precharge control terminal PR
PM for precharge when EN returns to high level
When the OS transistor P1 is turned off and the precharge operation is completed, the sense operation is started at the same time. First, when the memory cell M0 is not written, the memory cell M0 becomes O
Since it is in the N state, electric charges are extracted from the data line capacitance C0 charged by the precharge, and the potentials of the data line D0 and the input terminal DI0 are lowered. The potential of the data line D0 is the PMOS transistor P during the precharge period.
5 and the NMOS transistor N2 are biased in the vicinity of the logic threshold voltage VLT, the output of the inverter, that is, the gate potential of the NMOS transistor N1 is inverted and increased by a slight decrease in the potential of the data line D0. Along with this, the NMOS transistor N1 shifts to the ON state and lowers the potential of the node PG. The stray capacitance of the node PG is due to the gate capacitance of the PMOS transistors P2 and P3, etc., and is considerably smaller than the data line capacitance C0.
The potential of G rapidly decreases toward the potential of the data line D0. The potential of the node PG changes from the VCC power supply voltage to the threshold voltage Vth of the PMOS transistor P2.
The PMOS transistor P2 is turned on when the voltage drops by p minutes.
At the same time, the PMOS transistor P3, which forms a current mirror circuit with the PMOS transistor P2, is also turned on.
To do. At this time, since the gate voltage of the NMOS transistor N3, that is, the potential of the input terminal DI0 is lowered, NM
Like the OS transistor N4, it is almost off,
Therefore, the node A is turned on by turning on the PMOS transistor P3.
The potential of can rise rapidly and a high-speed sense output operation can be obtained.

On the other hand, when the memory cell M0 is written,
Since the memory cell M0 is in the OFF state, the potential of the data line charged by the precharge is maintained as it is. Therefore, the NMOS transistor N1 maintains the OFF state, so that the potential of the node PG does not decrease and the PMOS transistors P2 and P3 also maintain the OFF state. Further, the NMOS transistor N3 continues to be in the ON state because the potential of the data line does not decrease, and the potential of the node A maintains the Low level as in the precharge period. Therefore, the memory data read is completed at the same time as the precharge is completed. In this embodiment, the PMOS transistor P2 does not participate in the precharge of the data line and serves only as a current bias source for the memory cell M0 during the sensing operation. Since it is not necessary to compare the current with the reference side as in the conventional example shown in FIG. 7, the bias current to the memory cell M0 can be set on the PMOS transistor P2 side. That is, it is possible to regulate the bias current to the memory cell M0 during the sensing operation and reduce the current consumption due to this.

Also on the side of the PMOS transistor P3, "0" / depends on the operating point (node A potential) with the NMOS transistor N3 which is always on as in the conventional example.
Instead of performing the "1" judgment, the PMOS transistor P
3, because the node A potential is determined by the exclusive operation of the NMOS transistor N3, the PMOS transistor P3,
The through current between the NMOS transistors N3 can be made extremely small, and the potential can be fixed at high speed. Therefore, by increasing the current setting on the side of the PMOS transistor P3 by the mirror ratio of the PMOS transistors P2 and P3, it is possible to further increase the speed without affecting the current consumption.

As described above, according to this embodiment, it is possible to obtain a sense amplifier circuit which consumes low current and enables high-speed data reading. Further, since the reference amplifier circuit in the conventional example is unnecessary and the circuit configuration can be simplified, a sense amplifier circuit advantageous in terms of integration can be obtained.

A second embodiment of the present invention is shown in FIG. This embodiment is the same as the first embodiment shown in FIG.
NMOS transistor N5 is connected between ND and PMO
A PMOS transistor P6 is added between the S transistor P3 and the node A, respectively. N
The inverted signal PRE of the precharge control terminal PREN is input to the gates of the MOS transistor N5 and the PMOS transistor P6. The embodiment of FIG. 4 is particularly designed to enable normal data reading even in a low voltage range where the VCC power supply voltage is about twice the threshold voltage Vth of the MOS transistor or less. That is, since the precharge current from the PMOS transistor P1 is supplied to the data line via the NMOS transistor N1, the data line potential is VC.
Vth of NMOS transistor N1 from C power supply voltage,
It does not exceed the reduced voltage. Therefore, under the VCC power supply voltage which is about twice the Vth or less, the data line potential Vd after precharge becomes Vd = VCC-Vth,
Since Vd <Vth, the NMOS transistor N
2, 2 and N3 cannot be turned on, and the potential of the node A cannot be initialized to the low level. This means that the write side memory cell M0 cannot be read. Therefore, the NMOS transistor N connected to the node A
By turning ON 5 during the precharge period, the potential of the node A is forcibly set to the low level, and the above countermeasure is taken. Further, the PMOS transistor P6 is provided in order to prevent a through current between the PMOS transistor P3 and the NMOS transistor N5 at the time of starting the precharge by turning OFF during the precharge period. When the PMOS transistor P1 is turned on and the precharge is started, the potential of the node PG rises as the data line D0 is charged. In other words, the potential of the node PG rises with a certain slope. Therefore, immediately after the start of precharge, there is a period in which the PMOS transistor P3 is in the ON state, and the PMO
If there is no S-transistor P6, the NMOS transistor N
A through current will flow to the 5 side.

According to this embodiment, in addition to the effects of the first embodiment, a sense amplifier circuit suitable for lowering the voltage of the VCC power supply can be obtained.

A third embodiment of the present invention is shown in FIG. In this embodiment, in the embodiment of FIG. 1, NMOS transistors N21 and N22 connected in parallel are inserted between the source of the NMOS transistor N2 and GND, and the precharge control terminal P
The input to REN, the output to the gate of the NMOS transistor N21, the input to the output of the inverter G3 and the output of the inverter G3, respectively, the NMOS transistor N22.
The output of the gate is connected to the inverter G4 connected to the output of the gate.

In FIG. 5, the precharge control terminal PR
When a low-level precharge activation signal is applied to EN, first the NMOS transistor N21 side is turned on. At this time, the logic threshold voltage VLT of the inverter composed of the PMOS transistor P5 and the NMOS transistor N2 is higher than that in the embodiment of FIG. 1 by the amount that the source potential of the NMOS transistor N2 is floated by the NMOS transistor N21. Then precharge control terminal PR
When EN becomes High and the sense operation mode is set, the NMOS transistor N22 side is turned on this time. Where N
If the W / L size of the NMOS transistor N22 is set larger than that of the MOS transistor N21, the NMO
The floating of the source potential of the NMOS transistor N2 when the S-transistor N22 side is turned on becomes small, so that the logical threshold voltage VL of the inverter composed of the PMOS transistor P5 and the NMOS transistor N2 is reduced.
T is also lower than when the NMOS transistor N21 side is ON. That is, the NMOS transistors N21 and N22
Thus, it is possible to give a difference to the VLT before and after the end of precharge. In the embodiment shown in FIG. 1, when the memory cell M0 on the write side is to be read, the potential of the data line D0 after the completion of precharge is the logic threshold voltage VLT of the inverter composed of the PMOS transistor P5 and the NMOS transistor N2 as described above. Although it is held in the vicinity, the NMOS transistor N1 is returned to the ON state and P
There is a possibility that the mirror circuit of the MOS transistors P2 and P3 malfunctions and erroneous data reading occurs.
On the other hand, in the present embodiment, the VLT during the precharge period is set to be higher than the VLT after the precharge is completed, so that the data line potential at the end of the precharge is set higher than the VLT in the sense operation mode. Therefore, it is possible for the NM to reduce the potential of the data line due to the noise or the like.
It is possible to prevent the malfunction of the OS transistor N1 and the malfunction of the mirror circuit of the PMOS transistors P2 and P3.

As described above, according to this embodiment, it is possible to obtain the sense amplifier circuit which can improve the noise resistance in addition to the effect of the first embodiment.

A fourth embodiment of the present invention is shown in FIG. In this embodiment, a PMOS transistor P7 connected in parallel with the PMOS transistor P5 is provided in the embodiment of FIG.

In FIG. 6, the PMOS transistor P7
The gate is connected to the precharge control terminal PREN and is turned on only during the precharge period. PMO
When the S transistor P7 is turned on, the current capacity of the PMOS transistor P5 during the precharge period is apparently increased because it is connected in parallel with the PMOS transistor P5.
The logic threshold voltage VLT of the inverter composed of the transistor N2 shifts to a higher level. Then, at the same time when the precharge period ends, the PMOS transistor P7
Is turned off and the current capability is reduced, so that the VLT is reduced. This means that the same operation as that of the third embodiment is obtained, and therefore according to this embodiment, the same effect as that of the third embodiment can be obtained.

It is of course possible to use the constitutions peculiar to the second embodiment in combination with the third and fourth embodiments, and in that case, the effects of the second embodiment can be combined.

[0033]

As described above, according to the present invention, it is possible to obtain a sense amplifier circuit having a simple circuit structure, high speed and low current consumption, which is extremely advantageous in terms of integration. Also,
Further, a sense amplifier circuit having improved noise resistance can be obtained.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of the present invention.

FIG. 2 is a timing chart of an input signal according to the present invention.

FIG. 3 is a circuit diagram showing a configuration example of a precharge control signal generation circuit.

FIG. 4 is a circuit diagram showing a configuration of a second exemplary embodiment of the present invention.

FIG. 5 is a circuit diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 6 is a circuit diagram showing a configuration of a fourth exemplary embodiment of the present invention.

FIG. 7 is a circuit diagram showing a configuration example of a conventional sense amplifier circuit.

[Explanation of symbols]

P1 to P9 ... PMOS transistors, N1 to N7, N2
1, N22 ... NMOS transistor, Y1, Y2 ... Data line selection switch, M0 ... Memory cell, G1 ... Inverter, SAN ... Sense amplifier start control terminal, PREN ... Precharge control terminal, DI0 ... Input terminal, SOUT ... Sense amplifier output Terminal.

Front page continuation (72) Kenichi Ishibashi 5-20-1, Kamimizuhoncho, Kodaira-shi, Tokyo Inside Semiconductor Division, Hitachi, Ltd. (72) Teruji Sato 3-1-1, Saiwaicho, Hitachi, Ibaraki Hitachi, Ltd. (56) References JP 63-253598 (JP, A) JP 63-225998 (JP, A) JP 4-214292 (JP, A) (58) Survey Fields (Int.Cl. ⁷ , DB name) G11C 16/06 G11C 17/18

Claims (4)

(57) [Claims] 1. A first-conductivity-type first transistor having a gate and a drain short-circuited, and a first-conductivity-type transistor which forms a current mirror circuit with the first transistor by connecting the gate to the gate of the first transistor. A second transistor; a data line voltage suppressing unit interposed between the first transistor and an input terminal connecting the selected data line; and a sense data determining unit connected to the drain side of the second transistor. In the current sense type sense amplifier circuit, the first and second transistors are provided between the gates of the first and second transistors and the power source.
A conductive third transistor is provided, a first conductive fourth transistor is provided between the source of the first transistor and a power supply, and a second conductive fifth transistor is provided between the input terminal and the reference potential. The second conductivity type sixth transistor connected between the drain of the first transistor and the input terminal, and between the power supply and the gate of the sixth transistor. A seventh transistor of the first conductivity type connected to the potential,
An eighth of the second conductivity type, which is connected between the gate of the sixth transistor and the reference potential, and whose gate is connected to the input terminal.
The second conductivity type ninth transistor in which the data line voltage suppressing means is constituted by the transistor of No. 2, and is connected between the drain of the second transistor and the reference potential and the gate of which is connected to the input terminal.
Of the third transistor is configured to control the gate of the third transistor with a one-shot pulse synchronized with the sense amplifier circuit control signal applied to the gates of the fourth and fifth transistors. Sense amplifier circuit to do. 2. A first-conductivity-type first transistor having a short-circuited gate and drain, and a first-conductivity-type transistor which forms a current mirror circuit with the first transistor by connecting the gate to the gate of the first transistor. A second transistor; a data line voltage suppressing unit interposed between the first transistor and an input terminal connecting the selected data line; and a sense data determining unit connected to the drain side of the second transistor. In the current sense type sense amplifier circuit, the first and second transistors are provided between the gates of the first and second transistors and the power source.
A conductive third transistor is provided, a first conductive fourth transistor is provided between the source of the first transistor and a power supply, and a second conductive fifth transistor is provided between the input terminal and the reference potential. The second conductivity type sixth transistor connected between the drain of the first transistor and the input terminal, and between the power supply and the gate of the sixth transistor. A seventh transistor of the first conductivity type connected to the potential,
An eighth of the second conductivity type, which is connected between the gate of the sixth transistor and the reference potential, and whose gate is connected to the input terminal.
And a second transistor of the second conductivity type having a gate and a source connected to an input terminal and a reference potential, respectively, and a second transistor and a ninth transistor. A first-conductivity-type tenth transistor connected between drains, and a second-conductivity-type eleventh transistor in which a drain is connected to a connection point between the ninth transistor and the tenth transistor and a source is connected to a reference potential, respectively.
And a transistor for controlling the sense data by controlling the gate of the third transistor with a one-shot pulse synchronized with a sense amplifier circuit control signal applied to the gates of the fourth and fifth transistors. A sense amplifier circuit characterized in that the gates of the tenth transistor and the eleventh transistor are controlled by an inverted signal of the one-shot pulse. 3. A first-conductivity-type first transistor having a shorted gate and drain, and a first-conductivity-type transistor which forms a current mirror circuit with the first transistor by connecting the gate to the gate of the first transistor. A second transistor; a data line voltage suppressing unit interposed between the first transistor and an input terminal connecting the selected data line; and a sense data determining unit connected to the drain side of the second transistor. In the current sense type sense amplifier circuit, the first and second transistors are provided between the gates of the first and second transistors and the power source.
A conductive third transistor is provided, a first conductive fourth transistor is provided between the source of the first transistor and a power supply, and a second conductive fifth transistor is provided between the input terminal and the reference potential. The second conductivity type sixth transistor connected between the drain of the first transistor and the input terminal, and between the power supply and the gate of the sixth transistor. A seventh transistor of the first conductivity type connected to the potential,
It is connected between the 8th and 9th transistors of the second conductivity type whose one ends are connected to the reference potential and connected in parallel to each other, and between the gate of the 6th transistor and the 8th and 9th transistors, and the gate is input. A data line voltage suppressing means is constituted by a second conductivity type tenth transistor connected to the terminal, is connected between the drain of the second transistor and the reference potential, and its gate is connected to the input terminal. First of two conductivity types
The first data transistor constitutes a sense data determination means, and the gate of the third transistor is controlled by a one-shot pulse synchronized with the sense amplifier circuit control signal applied to the gates of the fourth and fifth transistors. The gates of the eighth and ninth transistors in the voltage suppressing means are controlled by one-shot pulses having the same phase and a reverse phase as the gate signal of the third transistor, respectively, and the current drivability of the eighth and ninth transistors. A sense amplifier circuit characterized by having a difference. 4. A first-conductivity-type first transistor having a shorted gate and drain, and a first-conductivity-type transistor which forms a current mirror circuit with the first transistor by connecting the gate to the gate of the first transistor. A second transistor; a data line voltage suppressing unit interposed between the first transistor and an input terminal connecting the selected data line; and a sense data determining unit connected to the drain side of the second transistor. In the current sense type sense amplifier circuit, the first and second transistors are provided between the gates of the first and second transistors and the power source.
A conductive third transistor is provided, a first conductive fourth transistor is provided between the source of the first transistor and a power supply, and a second conductive fifth transistor is provided between the input terminal and the reference potential. The second conductivity type sixth transistor connected between the drain of the first transistor and the input terminal, and between the power supply and the gate of the sixth transistor. A seventh transistor of the first conductivity type connected to the potential,
An eighth of the second conductivity type, which is connected between the gate of the sixth transistor and the reference potential, and whose gate is connected to the input terminal.
And a ninth transistor of the first conductivity type, which is connected between the power supply and the gate of the sixth transistor, and whose gate is commonly connected to the gate of the third transistor, constitutes the data line voltage suppressing means. A second conductivity type first transistor connected between the drain of the second transistor and the reference potential and having its gate connected to the input terminal.
The sense data determination means is configured by the 0 transistor, and the gate of the third transistor is controlled by a one-shot pulse synchronized with the sense amplifier circuit control signal applied to the gates of the fourth and fifth transistors. And sense amplifier circuit.