JPS62251840A - Circuit test system - Google Patents

Abstract

PURPOSE:To easily test a large scale circuit by providing the titled system with a control means for separating signal lines into front and back stages, and connecting the output parts and input parts of the front and back stages to respective input and output terminals of the large scale circuit so that the circuit can be independently tested by an external signal. CONSTITUTION:In the circuit device 1 consisting of plural circuit parts 2-7 to be tested, the connection control circuit 8 is inserted between the circuits 2 and 3, between the circuits 4 and 5, on the way of an input signal route to the circuit part 6, and on the way of an output signal route from and circuit part 7 and its connection control can be attained by external control signal terminals 19, 20. In case of testing the circuit part 2, the circuit 8 controls switching so that the output of the circuit part 2 is connected to a circuit output terminal 18 and the scale of the circuit from an input terminal 11 to the output terminal 18 is limited only to the scale of the circuit part 2.

Description

TECHNICAL FIELD The present invention relates to a circuit testing method, and more particularly to a circuit testing method for testing large-scale logic circuit devices in data processing equipment.

BACKGROUND ART Conventionally, when testing a logic circuit, a simulation is performed on a large computer based on circuit information obtained from a circuit diagram in advance to create data that can detect failures in the circuit. This data is input data to a dedicated tester for the purpose of fault detection, and consists of the input data pattern necessary to detect a fault, the correct value for this input data pattern, and information pointing out the location of the faulty circuit. It is configured.

The circuit to be actually tested is installed on the tester in units such as packages and LSIs (large scale integrated circuits), and input data patterns are given from each input bin, and the output data from the output bins is compared with the correct value. be done. When these do not match, it is determined that there is a failure, and the failure location determined in advance by a simulation algorithm is self-helply pointed out.

In such a test method, the failure detection rate becomes a problem.

In other words, during simulation, the locations where failures may occur are predicted in advance, all failures are defined, and then the failure detection algorithm is executed, and when all failures are detected and the simulation is completed, this data is detected. This means that a test on a tester has the ability to detect a predicted failure with a detection rate of 100%.

In reality, even if a simulation is performed using a large computer, it often takes several hours to several tens of hours if the circuit to be tested is large in scale or the circuit configuration is complex. This is due to the fact that the circuit between the input terminal and the output terminal has become too complex to accommodate the computer's capabilities. Therefore, in the past, tests were given up at a low detection rate and tests were conducted in an abbreviated form, or a huge amount of man-hours were required to create patterns manually.

Purpose of the Invention The present invention has been made to solve the above-mentioned drawbacks of the conventional methods, and its purpose is to provide a circuit testing method that can easily test large-scale circuits. It is in.

Structure of the Invention The circuit testing method according to the present invention is to separate a signal path of a large-scale circuit into a front-stage circuit and a rear-stage circuit, and connect the output section of the front-stage circuit to the input terminal of the large-scale circuit, and A connection control means is provided that can freely connect the input section to the output terminal of the large-scale circuit, and independent circuit tests of the preceding and subsequent circuits can be performed while controlling the connection control means by an external control signal. It is characterized by the fact that

1 1 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the invention.

In the figure, the circuit device under test 1 consists of a plurality of circuit sections 2 to 7, and each connection relationship of the equal circuit sections 2 to 7 is
Assume that it is as shown in the figure. Referring to Figure 2,
The circuit sections 2 and 3 are connected in cascade to each other, and an input signal from the input terminal 11 of the circuit is led out to the output terminal 15 of the circuit via the circuit sections 2 and 3 in this order. Similarly, circuit parts 4 and 5
are cascade-connected in this order between the input terminal 12 and the output terminal 16. The circuit units 6 and 7 are connected between the input terminal 13 and the output terminal 17 and between the input terminal 14 and the output terminal 18, respectively.

In the present invention, as shown in FIG. 1, a connection control circuit 8 is provided in the middle of the signal path of each circuit section in FIG.
This connection control is performed using external control signal terminals 19 and 20. More specifically, circuit parts 2 and 3
The signal path between the circuits 4 and 5 is separated, and the output end of the pre-stage circuit section 2.4 is connected to the input side of the connection control circuit 8. Further, the input end of the subsequent stage circuit section 385 is connected to the output side of the connection control circuit 8. The input signal path to the circuit section 6 and the output signal path from the circuit section 7 are also separated and the connection control circuit 8 is inserted therebetween.

In such a configuration, when it is desired to test the circuit section 5, for example, the connection control circuit 8 performs switching control such that the output of the circuit section 2 is connected to the circuit output terminal 18. In this way, the circuit scale from the input terminal 11 to the output terminal 18 is the same as that of the circuit section 2.
This eliminates the need to test large-scale circuits connected subsequently to the circuit section 2.3.

Even when it is desired to test the circuit section 3, if the input of the circuit section 3 is connected to the circuit input terminal 13 under the control of the circuit 8, the test of only the circuit section 3 can be easily performed.

Although an example in which only one connection control circuit 8 is provided has been described, it is obvious that the connection control circuit 8 may be provided at a plurality of locations on the signal path of a large-scale circuit.

Effects of the Invention As described above, according to the present invention, even when testing circuits in which large-scale circuits are connected in series, each circuit can be separated and tested independently. This has the effect that the ability of the simulation machine is effectively utilized and the fault detection rate is significantly improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a circuit device under test before applying the method of the embodiment of FIG. 1. Explanation of symbols of main parts 1...Circuit device under test 2-6...Circuit section 8...Connection control circuit

Claims (1)

[Claims] The middle of the signal path of the large-scale circuit is separated to form a previous-stage and subsequent-stage circuit, the output part of the previous-stage circuit is connected to the input terminal of the large-scale circuit, and the input part of the latter-stage circuit is connected to the output terminal of the large-scale circuit. A circuit testing method characterized in that a connection control means that can be freely connected to each other is provided, and while the connection control means is controlled by an external control signal, an independent circuit test can be performed on each of the preceding and succeeding circuits. .