JPS62249459A - Heametic seal type semiconductor device - Google Patents
Heametic seal type semiconductor deviceInfo
- Publication number
- JPS62249459A JPS62249459A JP61092003A JP9200386A JPS62249459A JP S62249459 A JPS62249459 A JP S62249459A JP 61092003 A JP61092003 A JP 61092003A JP 9200386 A JP9200386 A JP 9200386A JP S62249459 A JPS62249459 A JP S62249459A
- Authority
- JP
- Japan
- Prior art keywords
- base
- structural adhesive
- adhesive
- semiconductor device
- bonding
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 239000000853 adhesive Substances 0.000 claims abstract description 42
- 230000001070 adhesive effect Effects 0.000 claims abstract description 42
- 239000008188 pellet Substances 0.000 claims abstract description 10
- 239000002131 composite material Substances 0.000 claims description 6
- 239000004952 Polyamide Substances 0.000 claims description 2
- 229920002647 polyamide Polymers 0.000 claims description 2
- 238000000034 method Methods 0.000 abstract description 18
- 238000001723 curing Methods 0.000 abstract description 7
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 239000003566 sealing material Substances 0.000 abstract description 3
- 238000001029 thermal curing Methods 0.000 abstract 1
- 238000007789 sealing Methods 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 6
- 239000000919 ceramic Substances 0.000 description 5
- 239000011521 glass Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000006023 eutectic alloy Substances 0.000 description 4
- 239000004677 Nylon Substances 0.000 description 3
- 239000004020 conductor Substances 0.000 description 3
- 230000006870 function Effects 0.000 description 3
- 238000002844 melting Methods 0.000 description 3
- 229920001778 nylon Polymers 0.000 description 3
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N phenol group Chemical group C1(=CC=CC=C1)O ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920001187 thermosetting polymer Polymers 0.000 description 3
- 239000004593 Epoxy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 239000003822 epoxy resin Substances 0.000 description 2
- 238000013007 heat curing Methods 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229920000647 polyepoxide Polymers 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- 229920000459 Nitrile rubber Polymers 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- DHKHKXVYLBGOIT-UHFFFAOYSA-N acetaldehyde Diethyl Acetal Natural products CCOC(C)OCC DHKHKXVYLBGOIT-UHFFFAOYSA-N 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 229920001971 elastomer Polymers 0.000 description 1
- 239000000806 elastomer Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000011888 foil Substances 0.000 description 1
- 239000000843 powder Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229920005992 thermoplastic resin Polymers 0.000 description 1
- -1 vinyl acetal Chemical class 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/161—Cap
- H01L2924/1615—Shape
- H01L2924/16195—Flat cap [not enclosing an internal cavity]
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は気密封止型半導体装置に関し、特に、そのダイ
ボンディング技術および封止技術の改良に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a hermetically sealed semiconductor device, and particularly to improvements in die bonding technology and sealing technology thereof.
従来の気密封止凰（ハーメチックシール型）半導体装置
にあっては、半導体素子（半導体ペレット）をベースに
固着させるダイボンディング（ペレット付）が主として
Ａｕ−８ｉ共晶合金法によって行なわれ、また当該半導
体素子を外部環境から保護するためのシール方法として
、主として、Ａｕ−８ｎ共晶合金法や低融点ガラス接合
法が主として行われてきた。In conventional hermetically sealed semiconductor devices, die bonding (with pellets) for fixing semiconductor elements (semiconductor pellets) to a base is mainly performed using the Au-8i eutectic alloy method, and As sealing methods for protecting semiconductor elements from the external environment, Au-8n eutectic alloy method and low melting point glass bonding method have been mainly used.
樹脂封止型半導体装置にありては、Ａｇベーストなどの
導電性樹脂接着剤によるペレット付やエポキシ系樹脂な
どによる樹脂封止が行われているが、気密封止型半導体
装置にあっては上記した共晶合金法やガラス接合封止が
主流を占めている。For resin-sealed semiconductor devices, pellets are attached using a conductive resin adhesive such as Ag-based, and resin encapsulation is performed using epoxy resin. However, for hermetically-sealed semiconductor devices, the above methods are used. The mainstream is the eutectic alloy method and glass bonding sealing.
ペレット付のための入ｕ−８ｉ共晶合金法では、合金を
形成するために、４５０℃程度まで温度を上げて行う必
要があり、また、そのペレット付に際しては、ベースに
Ａｕメッキを施し、さらに、その上に入ＵリボンやＡｕ
箔などを敷設し、ペレットを搭載し、高温で接合させる
という方法が−般にとられている。また、低融点ガラス
による接合も、４５０℃程度の溶融炉（封止部）の中を
、当該ガラスを塗布した半導体素子組立品を通過させて
、当該ガラスを溶融させ、接合させるという方式がとら
れる。このような、ペレット付や気密封止の方法では作
業温度が高（、半導体デバイスに与える熱ストレスが大
であり、また、プロセスも複雑で、封止部を必要とした
り、装置にコストがかかり過ぎたりする。また、作業時
間も長くかかる。なお、ダイボンディングや気密封止の
方法について述べた文献の例として、１９８０年１月１
５日株工業調査会発行ｒＩＣ化実装技術」Ｐ９９〜１０
１およびＰ１４８〜１４９がある。In the U-8i eutectic alloy method for attaching pellets, it is necessary to raise the temperature to about 450°C in order to form an alloy, and when attaching pellets, the base is plated with Au, Furthermore, U ribbon or Au
A commonly used method is to lay down foil or the like, mount pellets, and bond at high temperatures. Additionally, a common method for bonding using low-melting point glass is to pass the semiconductor element assembly coated with the glass through a melting furnace (sealing section) at approximately 450°C, melt the glass, and bond. It will be done. These methods of attaching pellets and hermetically sealing require high working temperatures (high thermal stress on semiconductor devices), are complex processes, require sealing parts, and are expensive to use. In addition, it takes a long time to work.An example of a document that describes die bonding and hermetic sealing methods is January 1, 1980.
5th Stock Industry Research Association “rIC Implementation Technology” P99-10
1 and P148-149.
（１） 本発明は常温での作業（半導体素子マウント
作業）が可能で、熱硬化が低温ででき、しかも短時間に
熱硬化が可能な技術を提供することを目的とする。した
がって、半導体デバイスに与える熱ストレスも低減でき
る技術を提供することを目的とする。(1) An object of the present invention is to provide a technology that allows work at room temperature (semiconductor element mounting work), allows heat curing at low temperatures, and allows heat curing to be performed in a short time. Therefore, it is an object of the present invention to provide a technology that can also reduce thermal stress applied to semiconductor devices.
（２）本発明は、また、プロセスも簡略化され、封止な
どに犬がかりな装置を必要としない技術を提供すること
を目的とする。(2) Another object of the present invention is to provide a technique that simplifies the process and does not require a complicated device for sealing or the like.
本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
すなわち、本発明では、構造用接着剤を使用し、しかも
、この構造用接着剤によりグイボンディングを行なうと
ともに、該構造用接着剤をシール材として用いて、気密
封止型半導体装置を構成するようにした。That is, in the present invention, a structural adhesive is used, and the structural adhesive is used to perform the bonding, and the structural adhesive is used as a sealing material to construct a hermetically sealed semiconductor device. I made it.
これにより、構造用接着剤は常温でのマウント作業が可
能で、また、低温、短時間での熱硬化が可能であり、デ
バイスに与える熱の影響を低減でき、また、構造用接着
剤は自動車や航空機などの構造物やその部材などの接着
剤として使用されているように、その接着性能などにも
優れている。As a result, structural adhesives can be mounted at room temperature, and can be thermally cured at low temperatures in a short time, reducing the effects of heat on devices. It also has excellent adhesive performance, as it is used as an adhesive for structures such as airplanes and aircraft, and their components.
次に、本発明による気密封止型半導体装置の二三の例を
、図面に基づいて説明する。第１図はＤＩＦ（デュアル
・イン・ライン）形セラミックパッケージの一例を示し
、外部リードを側面にロウ付して成るサイドブレーズ型
積層セラミックパッケージを示す。Next, a few examples of hermetically sealed semiconductor devices according to the present invention will be explained based on the drawings. FIG. 1 shows an example of a DIF (dual in line) type ceramic package, which is a side blaze type multilayer ceramic package in which external leads are brazed to the side surfaces.
ベース１上に、構造用接着剤２を塗布し、該接着剤２上
に、半導体素子３をマウントし、該接着剤２を熱硬化し
て、ベース１上に半導体ペレット（半導体素子）３を固
着（グイボンディング）する。A structural adhesive 2 is applied onto the base 1, a semiconductor element 3 is mounted on the adhesive 2, the adhesive 2 is thermally cured, and a semiconductor pellet (semiconductor element) 3 is placed on the base 1. Fixation (Gui bonding).
該素子３は、コネクタワイヤ４によりメタライズ導体部
５と接続し、さらに、該導体部５を介して外部リード６
と電気的に接続している。The element 3 is connected to a metallized conductor portion 5 via a connector wire 4, and is further connected to an external lead 6 via the conductor portion 5.
is electrically connected to.
ベース１に、キャップ７を取付ける。この際にも、前記
グイボンディングに使用したと同様の構造用接着剤２を
、ベース１などに塗布しておき、熱硬化させて、ベース
１にキャップ７を取付ける。Attach the cap 7 to the base 1. At this time as well, a structural adhesive 2 similar to that used in the above-mentioned bonding is applied to the base 1 and the like, and the cap 7 is attached to the base 1 by curing with heat.
第２図は、第１図と同様にＤＩＰ形セラミックパッケー
ジの一例を示すが、ベース１とキャップ７間にリードフ
レーム８を介在させて成るサーディツプ形セラミックパ
ッケージを示す。FIG. 2 shows an example of a DIP type ceramic package similar to FIG. 1, but shows a cerdip type ceramic package in which a lead frame 8 is interposed between a base 1 and a cap 7.
ベース１上にマウントする半導体素子３のダイボンディ
ング作業は、第１図に示すものと同様に、構造用接着剤
２を使用して行なう。さらに、ベース１の封止部に、構
造用接着剤２を塗布し、ＩＪ −ドフレーム８を介装し
、構造用接着剤２をさらに塗布して、キャンプ７を該接
着剤２の熱硬化による三次元架橋構造の形成により、ベ
ース１に強固に取付けする。Die bonding of the semiconductor element 3 to be mounted on the base 1 is performed using a structural adhesive 2, similar to that shown in FIG. Further, a structural adhesive 2 is applied to the sealing portion of the base 1, an IJ-deframe 8 is interposed, the structural adhesive 2 is further applied, and the camp 7 is heated by curing the adhesive 2. By forming a three-dimensional crosslinked structure, it is firmly attached to the base 1.
接着剤をその機能により分類すると構造用と非構造用に
大別され、本発明はこの構造用接着剤をグイボンディン
グの際の接合材料およびシールに際してのシール材とし
て使用するもので、構造用接着剤とは、狭義には、高温
時においても、高いモジュラスを示し、長時間の大きい
負荷に耐えるものをいい、広義には、接着体が実際に使
用される用途、目的の実用範囲内で、高い接着力を示す
ものをいう（昭和５１年２月２０日日刊工業新聞社発行
日本接着協会編「接着）・ンドプックＪ Ｐ２Ｏ３〜Ｐ
２Ｏ４参照）。この構造用接着剤は、主として航空機や
車両や建築物など大形の構造物の材料や部材の接着に使
用されている。Adhesives can be classified into structural and non-structural adhesives according to their functions, and the present invention uses this structural adhesive as a bonding material for bonding and as a sealing material for sealing. In a narrow sense, an adhesive refers to something that exhibits high modulus even at high temperatures and can withstand heavy loads for a long time.In a broader sense, it refers to something that exhibits a high modulus even at high temperatures and can withstand heavy loads for a long time. A substance that exhibits high adhesive strength (February 20, 1976, published by Nikkan Kogyo Shimbun, edited by Japan Adhesive Association, "Adhesion", Ndopuk J P2O3~P
2O4). This structural adhesive is mainly used for bonding materials and members of large structures such as aircraft, vehicles, and buildings.
本発明に使用される構造用接着剤としては、熱硬化性の
もので、複合形構造用接着剤が好ましい。The structural adhesive used in the present invention is thermosetting, and preferably a composite structural adhesive.
この複合形のものは熱可塑性樹脂や熱硬化性樹脂やエラ
ストマーなとのそれぞれの欠点を改善する目的で複合タ
イプとしたもので、例えばエポキシ樹脂−ナイロン、−
ポリアミドのような複合成分により接着剤を構成して成
るものである。この複合形構造用接着剤としては、上記
で例示したナイロン／エポキシの他エポキシ／フェノリ
ック、ビニルアセタール／フェノリック、ニトリルゴム
／フェノリックなどが挙げられる。This composite type is a composite type for the purpose of improving the disadvantages of thermoplastic resin, thermosetting resin, and elastomer. For example, epoxy resin - nylon, -
The adhesive is made of a composite component such as polyamide. Examples of this composite structural adhesive include nylon/epoxy as exemplified above, epoxy/phenolic, vinyl acetal/phenolic, nitrile rubber/phenolic, and the like.
本発明に使用される構造用接着剤は上布されており、例
えば、東亜合成化学工業株社製ナイロン系構造接着剤（
粉末状、溶剤状などあり）ＦＳ−１７５Ｐ、ＦＳ−１７
５ＳＮなどを入手することができ、これらは例えば１３
０℃位の硬化温度で熱硬化して三次元架橋構造を形成す
ることができる。The structural adhesive used in the present invention is coated with a nylon-based structural adhesive manufactured by Toagosei Kagaku Kogyo Co., Ltd. (
Available in powder form, solvent form, etc.) FS-175P, FS-17
5SN etc. can be obtained, these are for example 13
A three-dimensional crosslinked structure can be formed by thermosetting at a curing temperature of about 0°C.
本発明に使用されるベース１やキャップ７は、例えばセ
ラミック材料により構成される。The base 1 and cap 7 used in the present invention are made of, for example, a ceramic material.
半導体素子（チップ）３は、例えばシリコン単結晶基板
から成り、周知の技術によってこのチップ内には多数の
回路素子が形成され、１つの回路機能が与えられている
。回路素子の具体例は、例えばＭＯＳ）ランジスタから
成り、これらの回路素子によって、例えば論理回路およ
びメモリの回路機能が形成されている。The semiconductor element (chip) 3 is made of, for example, a silicon single-crystal substrate, and a large number of circuit elements are formed within this chip using well-known techniques to provide one circuit function. A concrete example of a circuit element is, for example, a transistor (MOS), and these circuit elements form, for example, a logic circuit and a memory circuit function.
コネクタワイヤ４は、例えば人影細線により構成されて
いる。The connector wire 4 is composed of, for example, a thin human line.
リードフレーム８は、例えばＮｉ−Ｆｅ系合金やＣｕ系
合金により構成されている。The lead frame 8 is made of, for example, a Ni-Fe alloy or a Cu alloy.
本発明構造用接着剤によるダイポンディフグや封止の際
の硬化温度は、その使用量などにより異なり一概にいえ
ないが、２００℃以下好ましくは９０〜１３０°Ｃ１硬
化時間は６０秒程で済む。本発明によれば、構造用接着
剤２により、ベースＩＫ半導体素子３をペレット付し、
また、ベース１にキャップ７を取付は封止するようにし
たので、硬化温度が従来に比して低温で行なうことがで
き、また、これら作業を短時間に行なうことができた。The curing temperature for sealing and sealing with the structural adhesive of the present invention varies depending on the amount used, etc., but it cannot be determined unconditionally, but it is preferably 200° C. or lower, preferably 90 to 130° C. The curing time is about 60 seconds. According to the present invention, the base IK semiconductor element 3 is pelletized with the structural adhesive 2,
Further, since the cap 7 is attached to the base 1 and sealed, the curing temperature can be lower than that of the conventional method, and these operations can be performed in a short time.
したがって、半導体素子３へ与える熱ストレスも低減で
きた。Therefore, the thermal stress applied to the semiconductor element 3 could also be reduced.
また、プロセスも簡単化できた。It also made the process easier.
以上本発明者によってなされた発明を実施例に７もとづ
き具体的に説明したが、本発明は上記実施例に限定され
るものではなく、その要旨を逸脱しない範囲で種々変更
可能であることはいうまでもない。The invention made by the present inventor has been specifically explained above based on 7 examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist of the invention. Not even.
以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＤＩＰ形セクセラミ
ックパッケージいて適用した場合について説明したが、
それに限定されるものではなく、リードレスチップキャ
リアパッケージ（ＬＣＣ）などにも適用でき、その他気
密封止型半導体装置全般に適用できる。The above explanation has mainly been about the application of the invention made by the present inventor to the DIP-type ceramic package, which is the field of application in which the invention was made.
The present invention is not limited thereto, and can be applied to leadless chip carrier packages (LCCs) and other hermetically sealed semiconductor devices in general.
本題において開示される発明のうち代表的なものＫよっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。A brief explanation of the effects obtained by the representative invention K among the inventions disclosed in this subject is as follows.
すなわち、本発明によれば、作業温度が低くて済み、デ
バイスに与える熱ストレスが低減され、プロセスも簡略
化され、歩留も向上し、高信頼性の気密封止型半導体装
置を得ることができた。That is, according to the present invention, the working temperature is low, the thermal stress applied to the device is reduced, the process is simplified, the yield is improved, and a highly reliable hermetically sealed semiconductor device can be obtained. did it.
第１図は本発明の実施例を示す断面図、第２図は本発明
の他の実施例を示す断面図である。
１・・・ベース、２・・・構造用接着剤、３・・・半導
体素子、４・・・コネクタワイヤ、５・・・導体部、６
・・外部リード、７・・・キャップ、８・・・リードフ
レーム。
＼之ンFIG. 1 is a sectional view showing an embodiment of the invention, and FIG. 2 is a sectional view showing another embodiment of the invention. DESCRIPTION OF SYMBOLS 1... Base, 2... Structural adhesive, 3... Semiconductor element, 4... Connector wire, 5... Conductor part, 6
...External lead, 7...Cap, 8...Lead frame. \no
Claims (1)
て成ることを特徴とする気密封止型半導体装置。 ２、構造用接着剤により半導体ペレットが上記ベースに
ダイボンディングされて成ることを特徴とする特許請求
の範囲第１項記載の気密封止半導体装置。 ３、構造用接着剤が、複合形構造用接着剤で、かつ、ポ
リアミド系構造用接着剤である、特許請求の範囲第１項
又は第２項記載の気密封止型半導体装置。[Claims] 1. A hermetically sealed semiconductor device characterized in that a cap and a base are bonded together using a structural adhesive. 2. The hermetically sealed semiconductor device according to claim 1, wherein a semiconductor pellet is die-bonded to the base using a structural adhesive. 3. The hermetically sealed semiconductor device according to claim 1 or 2, wherein the structural adhesive is a composite structural adhesive and a polyamide structural adhesive.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092003A JPS62249459A (en) | 1986-04-23 | 1986-04-23 | Heametic seal type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61092003A JPS62249459A (en) | 1986-04-23 | 1986-04-23 | Heametic seal type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62249459A true JPS62249459A (en) | 1987-10-30 |
Family
ID=14042255
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61092003A Pending JPS62249459A (en) | 1986-04-23 | 1986-04-23 | Heametic seal type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62249459A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444286A (en) * | 1993-02-04 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor pressure sensor including lead supports within the package |
| US6489183B1 (en) * | 1998-07-17 | 2002-12-03 | Micron Technology, Inc. | Method of manufacturing a taped semiconductor device |
-
1986
- 1986-04-23 JP JP61092003A patent/JPS62249459A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5444286A (en) * | 1993-02-04 | 1995-08-22 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor pressure sensor including lead supports within the package |
| US6489183B1 (en) * | 1998-07-17 | 2002-12-03 | Micron Technology, Inc. | Method of manufacturing a taped semiconductor device |
| US7829385B2 (en) | 1998-07-17 | 2010-11-09 | Micron Technology, Inc. | Taped semiconductor device and method of manufacture |
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