JPS6224876B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an MIS type semiconductor memory device.

In a complementary MIS type semiconductor memory device, both memory cells and peripheral circuits are constituted by complementary MIS type circuits.

Therefore, each memory cell is a P channel.
It is composed of MISFET and N-channel FET. In this configuration, the area occupied by one memory cell becomes large, which becomes a cause of restraint in improving the degree of integration. Especially P channel MISFET and N channel
Since there is a well junction between the FET and the FET, a certain distance must be provided between the FET and the FET, and this has been a major cause of lowering the degree of integration.

It is an object of the present invention to solve such problems and to increase storage capacity, improve integration density, and further reduce power consumption.

In order to achieve the above object, according to the present invention,
In an MIS type semiconductor memory device comprising a semiconductor substrate including a pair of data lines, a memory cell coupled to the data line, and a sense amplifier coupled to the data line, the memory cell is an N-channel MISFET. A flip-flop includes a pair of inverters each made of a series circuit of a high-resistance polycrystalline silicon body, and the input and output of the flip-flop are cross-coupled to each other, and the pair of outputs of the flip-flop is connected to the pair of data lines. a pair of N channels for transmission, respectively coupled to
The sense amplifier operates as a pair of N-channel MISFETs each receiving signals from the pair of data lines at their gates, and a load element connected in series to the drain side of the pair of N-channel MISFETs. a pair of P-channel MISFETs, and an N-channel MISFET that is commonly connected in series to the source sides of the pair of N-channel MISFETs, and whose operation is controlled by a control signal applied to their gates.
MISFET, and in order to pre-charge the capacitors attached to the pair of data lines before reading data from the memory cell, the pair of data lines are connected to a pair of pre-charge capacitors.
The sense amplifier is coupled to a potential source through each MISFET, and when reading the memory cell, the sense amplifier amplifies a data signal read from the memory cell to the pair of data lines. do.

The present invention will be explained below with reference to Examples.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

1 is a memory cell, N-channel MISFETM ₁
~ _M4 and high resistance _R1 , _R2 . That is, one inverter is configured by the N-channel MISFETM ₁ and the high resistance R ₁ , and another inverter is configured by the N-channel MISFETM ₂ and the high resistance R ₂ . By cross-connecting these two inverters, a flip-flop, which forms the main part of the memory cell, is constructed.

M ₅ and M ₆ are P-channel MISFETs, which function as pre-charge transistors.

_M7 to _M11 are for configuring the sense amplifier.
MISFET, M ₇ and M ₉ are P channels
MISFETM ₈ , M ₁₀ , M ₁₁ are N-channel MISFETs
It is.

A pair of data lines l ₁ and l ₂ are connected to the sense amplifier, and lines l ₁ ' and l ₂ ', although not shown, are connected to the output of the data input circuit.

In this circuit, MISFETM ₅ and M ₆ are turned on and off according to the low level and high level of the chip selection signal CE. That is, since MISFETM ₅ and M ₆ are P-channel MISFETs, when the chip selection signal CE applied to their gates is at a low level,
MISFETM ₅ and M ₆ are in an on state, and conversely, when they are at a high level (Vcc level), they are in an off state. During the period when the chip selection signal CE is at low level, MISFETM ₅ , M ₆
When the data lines l ₁ and l ₂ are turned on, capacitors (not shown) associated with the data lines l 1 and l 2 are charged.
MISFETM ₃ and M ₄ are turned on by the high level of the word signal. The sense amplifier uses the clock signal φ
When the level becomes high and MISFETM ₁₁ is turned on, it becomes operational.

When reading data from memory cells, by setting the word signal to high level while the chip selection signal CE is at high level,
MISFETM ₃ and M ₄ are turned on, and the states of data lines l ₁ and l ₂ are set according to the contents of the memory cells.
That is, the chip selection signal CE is set to a low level in advance to turn on the precharge MISFET, thereby causing the data line to be turned on as described above.
l ₁ and l ₂ are charged, but when reading from the memory cell, the chip selection signal CE becomes high level, turns off the precharge MISFET, and disconnects the data lines l ₁ and l ₂ from the potential source Vcc. To separate. If the word signal is set to high level during this high level period of CE, MISFETM ₃ and _M4 will be turned on because they are N-channel MISFETs.
Depending on the on/off state of MISFETM ₁ and M ₂ of the memory cells, the potentials previously charged in the data lines l ₁ and l ₂ will change. for example,
If MISFETM ₁ is in the off state and MISFETM ₂ is in the on state, the charging potential of the data line _l1 will hardly drop, and conversely, the charging potential of the data line _l2 will change through the on state of _MISFETM2. As a result, the potential begins to drop below the precharge potential. Thereafter, the clock signal φ becomes high level, thereby enabling the sense amplifier to operate, and the sense amplifier performs an amplification operation in accordance with the state of the data line. In other words, the signal level difference between the data read from the memory cell to the pair of data lines is small because the inverter load of the memory cell is made of high-resistance polycrystalline silicon, but the difference is caused by the sense amplifier 2. As a result, this signal level difference is amplified to a large value.

Data is written to memory cells using the data line.
This is done by setting the word signal to high level with the states of l ₁ and l ₂ set.

In the present invention, an N-channel MISFET is used as the memory cell driving means, high-resistance polysilicon is used instead of a P-channel MISFET as the load means, and a normal complementary MIS type circuit is used as the memory cell peripheral circuit. ing.

FIG. 2 is a sectional view of such a complementary MIS type semiconductor memory device.

3 is an N-type semiconductor substrate, 4 is a P-type semiconductor well,
5 is a thick SiO ₂ film, 6 is a gate insulating film, 7 is a polycrystalline silicon gate electrode, 8 is a polycrystalline silicon layer formed at the same time as the gate electrode, and partially
Masked by the SiO ₂ CVD film 9, impurity doping is prevented in the portion 8a, and the resistance remains high. This polycrystalline silicon layer 8 is used as a high resistance material serving as a load means of the memory cell. 10 is the source of P channel MISFET, 1
1 is the drain of the P-channel MISFET, 12 is the source of the N-channel MISFET, 13 is the drain of the P-channel MISFET, 14 is a PSG film for surface passivation, and 15 is an aluminum electrode.

FIG. 3 shows the method of manufacturing such a semiconductor memory device in the order of steps.

(a) Oxidize the surface of the N ^- type semiconductor substrate 3 to form a SiO ₂ film 5
in the area where the well should be formed.
The SiO ₂ film 5 is removed by photoetching. Then, in this state, ions are implanted into the well. 16 is a photoresist film.

(b) Next, a P-type semiconductor well 4 is formed by diffusing P-type impurities.

(c) Remove the SiO ₂ film 5 formed on the semiconductor surface, then thinly oxidize the surface to form an insulating film 18, then deposit a nitride (Si ₃ N ₄ ) film 17 on the surface, and then Photoresist film 1
form 6. And this photoresist film 1
The nitride film 17 is photo-etched using No. 6 as a mask.

(d) Further, a photoresist film 16 is applied to the portion other than the well portion.

In this state, ions are implanted.

(e) In this state, an isolation film for element isolation is formed by selective oxidation using the nitride film 17 as a mask, and the nitride film 17 used as a mask is removed. Then, the back surface of the semiconductor substrate 3 is also etched.

(f) A gate insulating film 6 is formed by heating and oxidizing the semiconductor surface, and then polycrystalline silicon layers 7 and 8 are formed. Reference numeral 7 constitutes a gate electrode, and reference numeral 8 constitutes a high resistance element serving as a load means for the memory cell. Note that after forming the polycrystalline silicon layers 7 and 8, thin ions are implanted to control the specific resistance of the high-resistance element to a constant value.

(g) Forming a mask 19 on the semiconductor well portion.
In this state, window openings for source and drain diffusion of the P-channel MISFET are provided, and P-type impurities are diffused through the window openings to form the source 10 and drain 11.

(h) Remove the above mask and cover the P channel portion with a mask 19. Note that at this time, a portion of the polycrystalline silicon layer 8 is also covered with a mask. This is because it is necessary to prevent impurities from diffusing in order to maintain a high resistance state.

In this state, window openings for source and drain diffusion are provided, and N-type impurities are diffused through the window openings to form the source 12 and drain 13.

(i) After that, a PSG film 14 is formed. This PSG film 14 is photo-etched to form a window opening for taking out the electrode.

(j) Then form an aluminum electrode.

As described above, according to the present invention, only one channel type MISFET of the complementary MIS type circuit is used as a memory cell, and the other channel type MISFET is not used, so it is necessary to provide a wide space between the MISFET elements. Therefore, high integration can be achieved.

The resistor of the high-resistance element made of polysilicon used as the load means has a high specific resistance, so it only requires an extremely small area. The value should be set so that it can supply a small enough current to compensate for the leakage. For example, a resistance value of approximately 10 GΩ may be sufficient. Note that leakage is caused by the current flowing through the junction of parasitic capacitance and
This is caused by the tailing current flowing through the MISFET when it is in the OFF state. Therefore, the power consumption can be made almost the same as that of a complementary MIS type memory by using a high resistance element as a load means to supplement this small amount of current. Of course, a refresh circuit is also not required.

On the other hand, the present invention uses a very large resistance such as 10GΩ, which slows down the response speed when reading the memory cell, but since a complementary MIS type circuit is used as the sense amplifier, the sense amplifier compensates for the reduction in readout time.

On the other hand, peripheral circuits are complementary.
Uses an MIS type circuit and takes full advantage of the features of the complementer MIS type circuit.

As explained above, according to the present invention, it is possible to improve the degree of integration without deteriorating the electrical characteristics.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an MIS type semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a sectional view of the semiconductor memory device, and FIGS. FIG. 1...Memory cell, 2...Sense amplifier, 3...
...N-type semiconductor substrate, 4...P-type semiconductor well,
5, 6... SiO ₂ film, 7, 8... Polycrystalline silicon layer, 8a... High resistivity part, 9... CVD film (mask), 10... Source, 11... Drain, 12
...Source, 13...Drain, 14...PSG
Film, 15... Aluminum electrode, 16... Photoresist film, 17... Nitride, 18...
SiO ₂ film, M ₁ to M ₁₁ ... MISFET, R ₁ , R ₂ ... high resistance element.

Claims (1)

[Scope of Claims] 1. An MIS type semiconductor memory device comprising a semiconductor substrate including a pair of data lines, a memory cell coupled to the data line, and a sense amplifier coupled to the data line. The memory cell includes a pair of inverters each consisting of a series circuit of an N-channel MISFET and a high-resistance polycrystalline silicon body, and a flip-flop obtained by cross-coupling their inputs and outputs, and a pair of flip-flops obtained by cross-coupling their inputs and outputs. The sense amplifier includes a pair of transmission N-channel MISFETs for respectively coupling outputs to the pair of data lines, and the sense amplifier includes:
a pair of N-channel MISFETs each receiving signals from the pair of data lines at their gates;
A pair of P-channel MISFETs each operating as a load element are connected in series to the drain sides of the pair of N-channel MISFETs, and
N-channel that is commonly connected in series to the source side of the channel MISFET and whose operation is controlled by a control signal applied to its gate.
MISFET, and in order to pre-charge the capacitors attached to the pair of data lines before reading data from the memory cell, the pair of data lines are connected to a pair of pre-charge capacitors.
The sense amplifier is coupled to a potential source through each MISFET, and when reading the memory cell, the sense amplifier amplifies a data signal read from the memory cell to the pair of data lines. MIS type semiconductor memory device. 2. The MIS type semiconductor memory device according to claim 1, wherein the pre-charge MISFET is a P-channel MISFET.