JP3207492B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, it relates to a DRAM (Dynamic Random Access Memory) cell.

[0002]

2. Description of the Related Art Conventionally, a DRAM cell is composed of one MOS transistor and one capacitor. Since the cell operation is a method in which the potential of the bit line is changed only by the electric charge held in the capacitor, when the cell area is reduced, the capacity of the capacitor is not scaled, which is a serious obstacle to miniaturization.

Therefore, a gain memory cell having a function of amplifying and outputting a retained charge by itself is proposed (W.
H. Krautschneider et.al .: Microelectronic Enginee
ring. 15 (1991) 367-370).

FIG. 7 shows an equivalent circuit diagram and a sectional view of a gain memory cell. In FIG. _1, an access transistor M ₁ connected in series is provided on an active area of a silicon substrate 10.
And storage transistor M ₂ is formed. Access transistor M ₁ is word - word line (WL) connected to the polysilicon gate - and gate electrode 11, the gate - gate electrode 1
And a scan / drain regions 12, the storage transistor M ₂ gate - - source connected to the bit line (BL) and on either side of one and the gate electrode 11, the gate - In the both sides of the gate electrode 11 Source / drain region 1 connected to power supply line V _DD
2, source access transistors M ₁ and a storage transistor M ₂ share - is formed on the gate electrode 11, source - - scan / drain regions 12 and gate scan / drain region 12
And an aluminum layer 13 connecting the gate electrode 11.

Accordingly, information is held "0" and "1" in the cell is determined by charge stored in the gate of the storage transistor M _2, during the reading, it amplifies the current storage transistor M _2, Electric charges are supplied from a power supply line V _DD . Access transistor M ₁
Between the gate of the drain and the storage transistor M ₂ as the switching element S, diode - de D is interposed, plays a role not escape the charge accumulated in the gate when reading the information "1". When reverse current does not flow at all, since it is not possible to write information "0", in fact, information "1" escape gate stored charge at the time of reading does not affect the amplification function of the storage transistor M ₂ ranges Therefore, a very complicated and delicate switching characteristic that a reverse power supply flows appropriately is required.

[0006]

However, in the conventional gain memory cell described above, since a Schottky junction of silicon and aluminum is used as the switching element S, it is difficult to control a reverse power supply, and However, there is a problem that the operation margin of the device is reduced and the yield is reduced.

Further, since the access time for writing information is extremely different between "0" and "1", the DRA
There is a problem that the cell operation of M becomes unbalanced.

In addition to the usual MOS process technology,
There is a problem that a technique for forming the switching element S is required, and the manufacturing process is complicated.

[0009] The object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a semiconductor memory device which can be easily manufactured, can be miniaturized, and has excellent controllability.

[0010]

According to the present invention, there is provided a semiconductor memory device comprising: a first MISFET;
Is connected to the source of the second MISFET, and the drain of the first MISFET or the source of the second MISFET is connected to the gate of the second MISFET via a resistor. MISF
The source of ET is connected to the bit line, and the first MIS
The gate of the FET is connected to the word line, and the second MI
The drain of the SFET is connected to a current source.
Further, the resistance is equal to the drain and the first MISFET.
The diffusion region that is the source of the second MISFET and the second
An insulating film formed between the gate electrode of MISFET and
The insulating film is provided on the gate of the second MISFET.
The second MIS is formed continuously with the insulating film.
The thickness is smaller than the gate insulating film of the FET .

[0011]

In the present invention, since the gain memory cell is constituted by the two MISFETs and the resistance element, the manufacturing process is simplified, and a DRAM cell suitable for miniaturization and having good controllability is realized.

[0012]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a gain memory cell according to the present invention.

FIG. 1 is an equivalent circuit diagram of a gain memory cell. In the figure, it is connected with the access drain of the transistor M ₁ and the source of the storage transistor M _2, and the access transistor M ₁ and the storage transistor M ₂ are connected in series. In addition, the access transistor M ₁ of the drain and the storage transistor M ₂
The gate of the storage transistor M ₂ to the connection of the source is connected through the resistance element R, the source of the access transistor M ₁ is connected to a bit line (BL), the access transistor M ₁ gate - Togawa - is connected to a word line (WL), a drain of the storage transistor M ₂ is connected to the power supply line (V _DD), the 3-element type DRAM cell is constructed.

FIG. 2 is a circuit diagram illustrating the operation of the gain memory cell. When reading information from the memory unit, the resistance R
Is extremely small, electric charges are exchanged between the memory unit and the bit line in an instant, and it is expected that information in the memory unit will be destroyed while the function as the gain memory cell does not operate. Therefore, the lower limit of the resistance R is determined with reference to the circuit diagram of FIG.

First, consider the case where information "1" is read. The precharge potential of the bit line is set to 0V. Assuming that the charge stored in the bit line and the memory unit when the time t has elapsed after the access transistor M ₁ is turned “ON” is Q _B (t) and Q _M (t), respectively, the following equation (2) ) Is obtained from FIG.

Q _B (t) / C _B + R · dQ _B (t) / dt = Q _M (t) / C _OX Q _B (t) + Q _M (t) = Q _int (2) where C the _B bit line capacitance, C _OX is the gate capacitance of the storage transistor M _2, a relationship of the following equation (3).

Q _int = C _OX · V _DD (3) When this differential equation is solved using an approximation of C _B >> C _OX , the following equation (4) is obtained.

[0018] _{Q B (t) = Q int} · {1-exp (-t / τ)} Q M (t) = Q int · exp (-t / τ) ... (4) However, τ = R · C _OX On the other hand, when there is a charge of Q _M (t) in the gate, the current flowing through the storage transistor M ₂ is given by the following equation (5).

I _d (t) = (W / L) · μ · {Q _M (t) / S} · V _DD (5) where L is the channel length of the transistor, W is the channel width, and μ is the displacement. And S is the channel area (= LW). Therefore, the charge Q _MOS (t) flowing into the bit line through the storage transistor M ₂ is expressed by the following equation (6).

Q _MOS (t) = ∫I _d (x) dx on [0, t] = (W / L) · μ · (τ / S) · V _DD · Q _B (t) ... (6) bits When the sense amplifier operates when the potential of the line changes by ΔV _SA , the following equation (7) holds.

[0021] _{Q B (t) + Q MOS} (t) = C B · ΔV SA ... (7) access time for reading the information is given by the solution of the equation (7). Since Q _B (t) is a monotonically increasing function, in order for the equation for t to have a solution, the following equation (8) is obtained considering the limit of t → ∞.

[0022] {1+ (W / L) · μ · (τ / S) · V DD} · Q int> C B · ΔV SA ... (8) Therefore, the conditions to be satisfied resistor R, C _B · ΔV _SA 》 Q
_The following equation (9) is obtained by using an approximation of _int .

[0023]

(Equation 3) At this time, the read time t _R is given by the following equation (10).

T _R = −C _OX · R · log {1− (R _C / R)} (10) The write time t _w can be calculated by the same circuit calculation.
The same result can be obtained with the following simple considerations. Since the current flowing through the resistor at the time of writing is I = V _DD / R,
The writing time t _w is given by the following equation (11).

T _w = Q _int / I = C _OX · R (11) Assuming a 0.1 μm design rule (T _OX = 4 nm), the following specific numerical values, ie, L / WＷ1 / 3 mu substituting ^{~ 100cm 2 / V / sec V} DD ~ 2V C OX ~ 6 × 10 -17 F S ~ 3 × 10 -10 cm -2 C B ~ 5 × 10 -13 F ΔV SA ~ 0.1V Then, the lower limit resistance R _C is R _C ~ 3.5 MΩ.
Becomes

FIG. 3A is a current-voltage characteristic diagram of the resistance element R. As is apparent from the figure, since the current-voltage characteristic is symmetrical at V = 0 V, the access time at the time of reading / writing becomes equal between "0" and "1", and
A well-balanced cell operation becomes possible.

FIG. 3B is a graph of the access time at the time of reading / writing using these numerical values. When R> R _C , the read time t _R monotonically decreases and approaches τ _C = C _OX · R _C ０．２0.2 nsec.

[0028] On the other hand, since the writing time t _w is monotonically increasing, given the operating speed of the DRAM cell, the upper limit of the resistance R is determined by the writing time limit. The specification of the writing time cannot be uniquely determined because it is different for each device generation, but if both the specification of the reading time and the specification of the writing time are 1 nsec or less, the area indicated by the arrow in FIG. This is within the range of the resistance R. At the time of actual manufacturing, it is only necessary to suppress the variation of the resistance R within this range, and it is possible to sufficiently control.

Generally, in a DRAM cell of 16M or more,
Since the access time specification is said to be 100 nsec or less, it is necessary to satisfy at least R · C _OX <100 nsec, which determines the maximum allowable value _Rmax of the resistor R. When seeking 0.1μm generation R _max using the above numerical values, of the order 2Jiomega.

FIG. 4 shows an example of a layout of a gain memory cell. In the figure, a resistor is formed in a portion 100 indicated by a dotted line. The occupied area per cell is a region 200 surrounded by a chain line, which corresponds to two MOS transistors. Since the transistor area is reduced with miniaturization, it can be seen that the DRAM cell of the present invention is very suitable for miniaturization.

Next, a method of manufacturing a gain memory cell will be described with reference to FIG.
This will be described below. FIG. 5 shows a manufacturing process diagram in the AA section of FIG.

First, using a normal MOS process, P
Element isolation is performed on the type silicon substrate 1, and a gate electrode 2 is formed on a predetermined portion of the active region of the P type silicon substrate 1. Thereafter, ion implantation is performed using the gate electrode 2 as a mask to form source / drain diffusion regions 3 on the surface of the P-type silicon substrate 1 on both sides of the gate electrode 2 (FIG. 5).
a).

Next, after a silicon oxide film 4 is deposited on the entire surface by CVD, predetermined source / drain diffusion regions 3 are formed.
A contact hole 4a for forming a resistance element is formed in the upper silicon oxide film 4. Then, after polycrystalline silicon 5 serving as a resistance element is deposited on the entire surface by the LPCVD method, patterning is performed, and polycrystalline silicon 5 is left on contact hole 4a. Next, arsenic is ion-implanted over the entire surface,
The resistance value of the polycrystalline silicon 5 is set to ~ MΩ.
At this time, the dose of the ion implantation is appropriately optimized according to a desired resistance value. Subsequently, arsenic is ion-implanted at a high dose only around the contact hole 4a to lower the contact resistance (FIG. 5B).

Finally, after depositing the silicon oxide film 4 again, a contact hole 4b is formed in the silicon oxide film 4 on the predetermined source / drain diffusion region 3, and then the contact hole 4b is formed. Form metal wiring 6 (FIG. 5)
c).

As described above, the gain memory cell of this embodiment can be formed extremely easily using a normal MOS process, and does not require any special technique. As a method for forming the resistance element, it is also effective to use amorphous silicon (αSi—H) or single crystal silicon using an epitaxial growth method, in addition to the polycrystalline silicon 5. Also in this case, it is necessary to appropriately optimize the doping amount of the impurity according to a desired resistance value.

FIG. 6A is a sectional view of a gain memory cell according to another embodiment. According to the figure, the silicon substrate 1
Access connected in series transistor M ₁ and a storage transistor M ₂ is formed thereon. Gate access transistor M ₁ is formed on the silicon substrate 1 -
Oxide film 7 and a gate formed on gate oxide film 7.
Gate electrode 2 and a source / source formed on both sides of gate electrode 2.
And a drain diffusion region 3. On the other hand, the storage transistor M ₂ has a gate oxide film 7 formed on the silicon substrate 1, a gate electrode ₂ formed on the gate oxide film 7, and both sides of the gate electrode 2. The formed source / drain diffusion region 3 and an extremely thin oxide film 7a formed between the gate electrode 2 and the source diffusion region 3 and serving as a resistance element
The resistance value of the resistance element is controlled by forming a damaged layer in the ultra-thin oxide film 7a by ion implantation or the like.

FIG. 6 (b) shows a current-voltage characteristic diagram of a resistance element formed of an extremely thin oxide film 7a. According to this, it can be seen that the current-voltage characteristics are symmetric at V = 0 V, and a stable cell operation can be realized. Further, according to the present embodiment, no contact opening for connecting a resistor is required, so that the area can be further reduced.

It goes without saying that the present invention can be variously modified and used without departing from the spirit thereof.

[0039]

As described above, according to the present invention, a DRAM cell which can be easily manufactured by ordinary MOS process technology, can be miniaturized, and has excellent controllability can be realized. In addition, the operation margin of the cell can be improved, and the yield can be improved. Further, the cell operation of the DRAM can be made uniform, and a well-balanced cell operation at the time of access can be achieved.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit diagram of a semiconductor memory device of the present invention.

FIG. 2 is a circuit diagram illustrating a cell operation of the semiconductor memory device of the present invention.

FIG. 3 is a diagram illustrating a cell operation of the semiconductor memory device of the present invention.

FIG. 4 is a diagram illustrating a layout of a semiconductor memory device of the present invention.

FIG. 5 is a cross-sectional view illustrating a manufacturing process of the semiconductor memory device of the present invention.

FIG. 6 is a sectional view and a resistance characteristic diagram of the semiconductor memory device of the present invention.

FIG. 7 is an equivalent circuit diagram and a sectional view of a conventional gain memory cell.

[Explanation of symbols]

 Reference Signs List 1 P-type silicon substrate 2 Gate electrode 3 Source / drain diffusion region 4 Silicon oxide film 5 Polycrystalline silicon 6 Metal wiring

Continuation of front page (56) References JP-A-64-72554 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 27/108 H01L 21/8242

Claims (2)

(57) [Claims] 1. A drain of a first MISFET and a source of a second MISFET are connected, and the drain of the first MISFET or the source of the second MISFET and the gate of the second MISFET have a resistance. A semiconductor memory in which a source of the first MISFET is connected to a bit line, a gate of the first MISFET is connected to a word line, and a drain of the second MISFET is connected to a current source. In the device, the resistor comprises a drain of a first MISFET and a second MISFE.
The diffusion region that is the source of T and the gate of the second MISFET
An insulating film formed between the insulating film and the
Is continuously formed on the gate insulating film of the second MISFET.
And the gate of the second MISFET is formed.
A semiconductor memory device having a smaller thickness than an insulating film . 2. The channel length of the second MISFET is L, the channel width is W, the channel area is S, the mobility is μ,
The gate capacitance C _ox, the power supply voltage V _DD, the minimum voltage of the bit line capacitance can be detected C _B and a sense amplifier △ V
_{When SA} , the resistance value R is expressed by the following equation. 2. The semiconductor memory device according to claim 1, wherein the above expression (1) is satisfied.