JPS62248200A - Self-correcting semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the size of the scale of an additional circuit by controlling a selecting switch so that neighboring groups of memory cells and neighboring groups of inspection cells do not belong to the same horizontal/vertical group. CONSTITUTION:Cell information are selected by a horizontal group selecting switch 10' and a vertical group selecting switch 11', and transmitted respectively to nodes N50-N55 and N60-N65. Thereafter, horizontal/vertical group parity check circuits 14 and 15 which connected with the cascade connection circuits to which a one-input parity circuit is cascade-connected in two stages respectively read the six bits of check-result at high speed out to nodes N20 and N21. By means of the combination of bits from the nodes N20 and N21, a data from the node N23 of a multiplexer 7' is corrected and supplied to an output terminal. As a result, the size of circuit-scale of the additional circuit can be reduced, and the action can be speeded up.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a self-correcting semiconductor memory device, and specifically, the present invention relates to a self-correcting semiconductor memory device that has a self-correcting function that automatically corrects bit errors within a memory. The present invention relates to a semiconductor memory that costs -1 yen, and particularly relates to a self-correcting semiconductor memory that reduces the scale of an additional circuit for error correction and enables high-speed error correction operations.

[Conventional technology]

Semiconductor memory (referred to as self-correcting memory) that has a self-correcting function that corrects bit errors within the memory includes:
Basic configuration of a semiconductor memory device in which a horizontally stacked parity code is applied to multiple memory cells connected together to a word line (
Japanese Patent Application No. 56-37223, Japanese Patent Application No. 57-152597
(Japanese Patent Application No. 59-86930) has been proposed. An example of this improved configuration is shown in Fig. 3 (, ]), and the correction principle is shown in the same figure (bl). Here, ■ is a memory cell, 2 is a parity cell that stores inspection information of memory cell information, and 3 is a parity cell that stores inspection information of memory cell information. is a word line, 4 is a bit line, 5 is a parity bit line for parity cells, 6 is a column decoder, of which 6-1 is a lower column decoder into which column address A., A1 is input, 6-2 column address A2. Upper column decoder to which A3 is input, 7 is a multiplexer, 8 is a one-person coverage circuit that switches the path for transmitting the two reference voltages "11" and "L" according to input information, 9 is IO horizontal group selection A horizontal group parity check circuit including a switch, 11 is a vertical group selection switch, 12 is one horizontal group, and 13 is one vertical group, INVI is an inverter, ΔNDI is an AND gate, and EOR1 is an exclusive OR. Gate, 0 again
1 to CIG indicate cell numbers.

First, the correction principle will be explained using FIG.
) (parity cell of IN), parity cell information is stored in each parity cell so that even parity is established in each horizontal group and each vertical group.

In this state, for example, if the parity of the 12 horizontal groups and the 13 vertical groups shown in the figure is checked, and the parity results are "de", that is, a parity error has occurred, this means that the parity of the 12 horizontal groups and the 13 vertical groups shown in the figure is By inverting this information, bit errors can be corrected by ignoring errors in memory cell information located at the intersections of 13 vertical groups. 10 horizontal group selection switches and 11 vertical group selection switches are connected to one word line 3 shown in a), and one horizontal group and one vertical group in which the memory cell information to be corrected is connected, respectively. The parity check is performed by the vertically connected circuit of the one-person coverage circuit shown by 8, and the result is used to correct the output information to be corrected obtained by the multiplexer 7. The self-correcting semiconductor memory shown in FIG.
N2 and node N3. The connection relationship with transistors Q1.N4 is determined by the input signal and its complementary signal. Q2. By connecting the circuits to be exchanged in cascade using Q, Q4 and placing these circuits on the bit lines, a selector for selecting one horizontal group and one vertical group and a selector for performing parity check of each group are created. The parity check circuit can be integrated, which not only increases the speed of circuit operation but also reduces the size of additional circuitry.

However, in such a configuration, it is necessary to provide a one-person coverage circuit for each bit line to configure the horizontal group parity check circuit shown in 9.
There was a problem with the layout when it was applicable to M. Furthermore, due to the presence of a horizontal group selection switch indicated by 1o and the difference in wiring length between each input parity circuit,
The speeds of the water/I1 group parity check and the vertical group parity check are not well balanced, which is a factor that prevents speeding up of error correction operations.

[Object of the Invention] In order to eliminate these drawbacks, the present invention provides a method for determining the number of physically adjacent bits grouped by By controlling the horizontal group and vertical group selection switches so that each of the memory cells and test cells do not belong to the same horizontal group and the same vertical group, horizontal group parity check and vertical group parity check can be performed using exactly the same circuit configuration. The parity check circuit is constructed from multiple stages of cascaded parity circuits, and its purpose is to provide a smaller and faster error correction circuit.

[Explanation of Examples]

FIG. 1 is an explanatory diagram of the principle that makes the present invention possible, and (al
is 9 (hard memory cell l and 7 (cause parity cell 2)
are connected to one word line 3, and are numbered C1-C16 according to their physical locations. Figure (b) shows these 16+1! This is an example in which the cells of 2 are expanded into a two-dimensional logical address space so that the same horizontal group and the same - river stone group are easily understood, and this expansion method is the key to the present invention. If you look at this figure (bl), you will see that in the same figure (al) there are four physically adjacent cell groups, namely 01 to C4, C
In each group 5-C8, C9-12, C13-C16, four cells belong to separate horizontal and vertical groups.

When a horizontal group and a vertical group are formed with such a configuration, the selection of the horizontal group and vertical group in which the cell to be corrected is bent is one from Cl-C4 and one from 05 to C8.
Then, one cell information is selected from 09 to CI2 and one cell information is selected from C13 to C16. For example, fbl in the same figure
If the cell information of 06 is to be corrected, 12 horizontal groups, namely C14, C2, C6, CIO, and 13 vertical groups, namely C
9, C6, C3, and Cl6, but since the cells to be selected exist one each in the four cell groups mentioned above, the horizontal group selection switch and the vertical group selection switch can be configured in exactly the same way. In addition, in the same figure (C1 shows another development method that makes the present invention possible, C1-C4, C5-C8,
In this example, the parity cells are C
4, C5, C7, C1l, C12, C15, C16.
, CIO, C12, C13, and C16. Thus, it is clear that there are many other types of horizontal group and vertical group selection logics that make the present invention possible. In fact, these Cl-C16
A plurality of sets of cells connected to the same word line but physically adjacent to each other are made to belong to different code groups, and a desired code group C1-C16 is selected by a self-lter, for example, and a signal is sent to a switch circuit. FIG. 2(a) shows an embodiment of the present invention, and in order to explain the parity check circuit, a 25-bit memory cell and an 11-bit parity cell are connected to one word line. Physical arrangement of cells and co-horizontal groups.

The switch for selecting the same vertical group is based on the selection logic of FIGS. 1(a) and (b), as shown in FIG. 2(b). That is, all cells of a contiguous cell group consisting of 6 bits belong to separate horizontal and vertical groups.

1-5. ANDI and EORI are the same as in Figure 3, and 6
-1', 6-2', 7' are 6-1.6-2.7 in Figure 3
10' is a horizontal group selection switch, 11' is a vertical group selection switch, 14 is a horizontal group parity circuit, and 15 is a horizontal group selection switch.
is a vertical group parity check circuit. Also Hq-H5
, VO-Vs are column addresses A, respectively. -A2. A
It corresponds to the decoded signals of 3 to A5. The circuits 14 and 15 are configured, for example, as shown in FIG. 2(e). In the configuration example shown in FIGS. 2(al, fb) and (C), the circuit operation will be described by taking as an example the case where the cell information of C8 is to be corrected.

C2. which yields to the same horizontal group as the cell information of C8. C14,C
The cell information of 20, C2G, and C32 is 10 by the output of 111 of the lower column decoder output shown by 6-1'.
(selected with the horizontal group selection switch)
0, N5L N52. N53. N54.
This will be communicated to N55.

On the other hand, just like this, C3.08 belongs to the same group 16. C13, C24, C29, C3/I
cell information is selected by the vertical group selection switch 11' by the output of v2 of the upper column decoder output indicated by 6-2', and is sent to node N60. N61. NG2. N63
．． N64° is transmitted to N65. After this, Figure 2 (
The cascade connection circuit of the one-person coverage circuit shown by 8 in C1 is 2.
N20 and N21 with stage cascaded configuration
The horizontal group parity check result and the vertical parity check result of 6 bits each are read out at high speed. A multi-stage configuration such as tc+ in FIG. 2 operates faster than a single-stage cascade connection circuit 6, and the greater the number of input bits, the greater the effect of the multi-stage cascade connection.

After that, N20. By the combination of N21, the data at the node N23 of the multiplexer output of 7' is corrected and supplied to the output terminal. Regarding the write operation, please refer to Japanese Patent Application No. 1983-
The basic configuration is the same as that of No. 37223 and Japanese Patent Application Laid-open No. 57-152'597, and the explanation thereof will be omitted here. Further, FIG. 2(d) shows another embodiment of the parity circuit, in which φ,.

φ2 is a clock input signal, and 8' is the one-person coverage circuit of 8 itself, which inputs complementary signals.The actual configuration is as follows, since the bit lines of a normal memory are a complementary bit line pair. It has an 8' configuration rather than an 8. Further, [NVl is an inverter. In this circuit,
When the memory is on standby, the clock φ1. φ2 is Low, transistors Q, C2, and C5 are off, and all 8' output nodes are grounded. (Node N50 ~
55, N50 to N55 are all High). Next, during operation, nodes N50 to N55. After the complementary signals appear at N50' to N55', the clocks φ1 and φ2 are sequentially set to Lo.
-→11ight, the switching operation is started and the 6-bit parity check result is read out to N20. Also, the clock φ1. If the activation timing of φ2 is the same, that is, if the φ2 signal is doubled by φ, a small amount of through current will flow temporarily, but if the parity check is performed at a higher speed, such a dynamic parity check circuit can be used as a dynamic parity check circuit like a dynamic RAM. Figure 2 (at, (cl, (d)) is effective for memory with a precharge period.
Comparing this configuration with the conventional configuration shown in Figure 3+a),
The one-person coverage check circuit for each bit line, which was required for the horizontal group parity check, can be realized by using the same type of circuit as the vertical group parity check, and the layout is sufficient even when the bit line pitch is reduced. This makes it possible to greatly contribute to reducing the scale of additional circuitry for error correction. Furthermore, the horizontal group parity check and the vertical group parity check can be achieved using exactly the same circuit format, and the parity check circuit can be realized by cascading multiple stages of cascaded single-person coverage circuits, resulting in a good speed balance. Enables high-speed error correction.

In FIG. 2, which shows this embodiment, the column decoder is shown at the top for convenience of drawing, but it goes without saying that it can also be placed in the array adjacent to the horizontal group or vertical group selection switch. This is possible, and the configuration can be such that the logical product of the upper column decoder output and the lower column decoder output is taken as a column decoder output signal, and the signal is input to the multiplexer, thereby realizing a more compact self-correcting memory.

[Effects of the Invention] As explained above, the present invention provides a self-correcting semiconductor memory in which a plurality of physically adjacent groups are grouped in units corresponding to the number of bits forming one horizontal group or one vertical group. Since the horizontal group and vertical group selection switches are controlled so that each η of memory cells and test cells does not belong to the same horizontal group or the same vertical group, the horizontal group parity check circuit and the vertical group parity check circuit are (It can be realized with a similar circuit configuration, and the additional circuit can be made smaller by reducing the number of single-person coverage circuits.
Horizontal group and vertical group parity check circuits can be realized with a multi-stage cascade connection configuration of one-person coverage circuits connected in cascade with the same circuit configuration, and there is an advantage that high-speed and balanced circuit operation can be achieved at the same time.

[Brief explanation of drawings]

FIGS. 1(a), (b), (C1 shows an example of an improved configuration that illustrates the principle of the present invention. ■...Memory cell, 2...Parity cell, 3...
Word line, 4... Bit line, 5... Parity bit line, 6.6'... Column decoder, 6-6', 6-1
'...lower colla J decoder, 6-2.6-2'...
・Upper column decoder, 7,7'...Multiplexer, 8°8'...1 person coverage circuit, 9.14...
Horizontal group parity check circuit, 10. to'...
Horizontal group selection switch, 11. It'... Vertical group selection switch, 12... Horizontal group, 13... Overlapping group, 1
5...Vertical parity check circuit patent applicant l'
Hon Telegraph and Telephone Co., Ltd. Agent Patent Attorney Hisago Tamamushi
Department (2 outsiders) (a) Korororo possible A/Kuro times rowsei Korororo A? A. ) (N2+) Figure 2 (c) tlJ Figure 2 (d) Procedural amendment May 2, 1988 Date of Otsu 1, Indication of case 1986 Patent Application No. 92517 2, Title of invention Self-correcting semiconductor Storage device 3, relationship with the case of the person making the amendment Patent applicant address 1-1-6 Uchisaiwai-cho, Chiyoda-ku, Tokyo Name (422) Nippon Telegraph and Telephone Corporation Representative Makoto Fuji
4, Agent 6, Subject of amendment Amend the phrase ``in one body'' in line 18 of page 3 of the specification in the detailed description of the invention section to ``one piece.''that's all

Claims (3)

[Claims] (1) A plurality of memory cells that store information, a plurality of check cells that store information for detecting bit errors occurring in the memory, and form horizontal and vertical parity codes together with the information of the memory cells; A word line for selecting a plurality of memory cells and test cells, a bit line for exchanging information with the memory cells, a test bit line for exchanging information with the test cells, and a memory cell to be tested belongs to. A switch that uses a column decode signal to select bit line information and test bit line information belonging to the horizontal group and vertical group that include the memory cell to be tested in the code group, and two reference voltages "H" and "L". Means for switching transmission paths is connected in multiple stages, and means for performing a parity check by inputting a plurality of signals from the switch, and automatic bit error correction using the output of the means for performing a parity check. In a semiconductor memory to be corrected horizontally, each of a plurality of physically adjacent memory cells and test cells grouped in units corresponding to the number of bits forming one horizontal group or vertical group is The means for controlling the physical arrangement of the test cells and the selection logic of the switches so as not to belong to groups and vertical groups, and for performing the parity check, is based on two reference voltages "H".
, a self-correcting semiconductor memory device characterized in that it is constructed by cascading a plurality of circuits in which means for switching paths for transmitting "L" are connected in cascade. (2) In the self-correcting semiconductor memory device according to claim (1), the output signal pair of the cascaded circuits is input to the cascaded circuit of the next stage via an inverter, and the "H" A self-correcting semiconductor memory device, wherein a reference voltage is applied to the plurality of cascaded circuits via transistors. (3) A self-correcting semiconductor memory device according to claim (2), wherein the plurality of stages of cascade-connected circuits are activated by a single clock.