JPS62247443A - Channel control system - Google Patents

Abstract

PURPOSE:To avoid such a case where a microprocessor is occupied by a single channel only and to secure the highly efficient channel processing, by producing a request for the processing to be carried out successively when a process of a microprogram is through and rearranging the priority between the processing requests of other channels and the using right of the microprocessor. CONSTITUTION:A common control part 6 includes the 1st microprocessor 8 and the 2nd microprocessor 9 is provided to an individual control part 7. The part 7 reads cyclically the control information on each channel out of a memory means 11 and replaces them. When the selecting permission is designated by the processor 8, a priority deciding circuit 13 selects one of those processing requests stored in the request registers 12-0, 12-1, 12-2... according to the priority and outputs the selected request.

Description

[Detailed Description of the Invention] [Summary] In a microprocessor that commonly controls a plurality of channels, in order to subdivide the processing unit of each channel and to ensure equal processing opportunities for each channel, it is possible to Occasionally, requests for subsequent processing can be issued, and processing requests from other channels can be re-prioritized with respect to the right to use the microprocessor, thereby preventing one channel from monopolizing the microprocessor and improving efficiency. It is designed to perform good channel processing.

[Industrial application field]

The present invention relates to an interrupt processing method for a microprocessor in a channel processing device in a general computer system, and more particularly to a startup method for a microprocessor that requires common and equal control of a plurality of channels.

[Conventional technology]

FIG. 7 is a diagram showing the configuration of a general computer system having a channel processing device. In FIG. 7, 1 is a central processing unit, 2 is a channel processing unit, 3 is a main storage unit, and 4 is a main storage unit.
indicates a storage control device, CH indicates a channel, and 10 indicates an input/output device.

Conventionally, the channel processing device 2 has a channel mode for controlling each individual channel CH, and a
It is a microprocessor that has two modes: a CPU mode that controls instructions.

To switch from CPU mode to channel mode, use I
When the O instruction is issued, 10 is written to the register corresponding to the channel number.
There are two cases in which the channel issues an interrupt request and switches to channel mode when an instruction is issued, and another case in which a data transfer request occurs and the channel switches to channel mode, which is generally called a cycle steal. There are two cases in which the mode may be switched. The switching from the channel mode to the CPU mode occurs when the channel processing device 2 waits for the next IO instruction to be issued after the 0 instruction is completed, or when the cycle steal ends.

[Problem to be solved]

Recently, however, there has been an increase in the number of channels and a corresponding demand for higher processing efficiency, which has created a need for improvements to the conventional cycle-stealing method.However, the conventional method described above has the following drawbacks. Therefore, it is not possible to meet the demand for higher efficiency.

(a) Since the cycle steal processing time for one channel is long, the processing of other channels is forced to wait.

(b) Interrupting the channel at a convenient time when issuing 10 instructions and waiting until the next 10 instructions are issued are factors that make it difficult to enter cycle steal processing.

The present invention is intended to eliminate the above-mentioned drawbacks, and is capable of equally processing IO commands and (1) processing other than 0 commands, and
The purpose of this invention is to provide a channel control method that can shorten the processing time for one channel.

(Means for Solving the Problems) The basic idea of the present invention is as follows: (1) Subdividing the microprogram processing unit of one channel.

■ Eliminate the microprogram loop of waiting for 10 instructions to be issued and ■ waiting for 0 instructions to be executed.

The idea is to control the microprocessor. To this end, the present invention includes a storage means for storing control information for each channel in a channel processing device, an individual control unit that cyclically and individually controls the control information in the order of channel numbers, and an individual control unit. a priority determination circuit that determines the priority of execution of various processing requests retrieved from the storage means for each request content in order of channel number; and after determining the priority, the control B information is received from the storage means for microprogram execution. A readout means and a means for writing a time processing request into the storage means upon completion of microprogram execution are provided. However, the individual control unit issues a microprogram execution request in the same way as processing other than 10 instructions.

(b) A series of microprograms that would conventionally be processed continuously is divided into parts and temporarily terminated for processing on other channels. At the end of the process, the individual control unit is notified of a microprogram processing request to be performed subsequently, and the individual control unit issues a microprogram execution request in the same way as other processes.

That is what it says.

FIG. 1 is a diagram showing an outline of a channel processing device to which the present invention is applied. In FIG. 1, 4' is an MCU interface control section, 5 is a general processor, 6 is a channel common control section, 7 is an individual control section, 8 is a first microprocessor, 9 is a second microprocessor, and 10 is a channel control section. , respectively. In the illustrated example, the channel processing device 2 has 16 channels 10, but by connecting four sets of the common control unit 6 and the individual control units 7 to the general processor 5, the number of channels 10 can be increased to a maximum of 64. can be controlled. The channel processing device 2 includes a general processor 5, a channel common control section 6, and an individual control section 7. The common control section 6 is provided with a first microprocessor 8, and the individual control section 7 is provided with a second microprocessor 9. The general processor 5 executes and decodes instructions (for the CPU), loads/stores subchannels (for the M
CU), 10 interrupts (to the CPU), etc. The first microprocessor 8 of the common control unit 6 is
0 instruction analysis and execution, subchannel load/store,
It has functions such as data transfer with the main storage device 3, successive output of CCW (channel command word), and 10 interrupts. The second microprocessor 9 of the individual control unit 7 mainly handles IO
A function to perform sequence control of the zein interface, and check the on/off of the tag in signal of the IO zein interface.
It has a function to turn on/off the out signal, and further a function to analyze the status of the IO interface.

FIG. 2 is a diagram showing the configuration of a storage means for storing control information for each channel. In FIG. 2, 11 indicates a storage means. The storage means 11 stores control information for the channel of machine number O, control information for the channel of machine number l, . . . 2
Control information for the channel of machine number F is stored. In the individual control unit 7, the control information of each channel is stored in the storage means 11 cyclically.
It is read from and updated. That is, the individual control unit 7 reads the channel control '4n information of the machine number O in the storage means 11 in the #0 cycle, performs the determination process in the next cycle, performs the old input in the next cycle, and The channel control information of the machine number I in the storage means 11 is read out in a cycle, the determination process is performed in the next cycle, the channel control information of the machine number F in the storage means 11 is read out in the #F cycle, and the channel control information of the machine number F in the storage means 11 is read out in the #F cycle. is read out, judgment processing is performed in the next cycle,
Writing is performed in the next cycle, channel control information of machine number O in the storage means 11 is read out again in cycle #0, determination processing is performed in the next cycle, and writing is performed in the next cycle. The common control unit 6 reads the control information from the storage means 11 when necessary, and writes the result to the storage means 11 when processing is completed.

The storage means 11 contains microprogram execution requests (of the first microprocessor 8). Hereinafter, the term microprogram refers to the microprogram of the first microprocessor 8. These microprogram execution requests include the following.

Execution and decoding of i and ro instructions 2 Load/store subchannels 3 Transfer data to and from main memory 4 Read channel command words 5.10 Storage means for storing control information for each interrupt channel 11 includes a control register that can be read/written only by the individual control unit 7 that performs cyclic control in synchronization with the channel number, and a control register that can be read/written by both the common control unit 6 and the individual control unit 7. There is a control register. For convenience, the former will be referred to as control registers and the latter as stack registers.

FIG. 3 is a diagram showing the format of part of the channel-specific control information stored in the stack register.

In FIG. 3, MM RE (IUEST C0DE is a code indicating the content of a process execution request from a microprogram to the micro program itself, and MMRQ is an MI
CROTO (formerly CROl18QUEST) indicates that there is a request for processing from the microprogram itself to the microprogram itself, and MOP is an abbreviation for MIC.
It is an abbreviation for RO0PERATION and indicates that processing related to MMRQ is being executed. It is the individual control unit 7 that turns on the MOP. At this time, MMRQ is set to off. IOP is an abbreviation for 100PRATION, and indicates that a process related to the 0 instruction is being executed.

It is the individual control unit 7 that sets 10P on.

The IOP is set off as directed by the microprogram. DOP is an abbreviation for DATA 0PRATION and indicates that processing related to data transfer is being executed. It is the individual control unit 7 that turns on the DOP.

The DOP is set off as directed by the microprogram.

FIG. 4 is a diagram showing the format of part of the channel-specific control information stored in the control register. In FIG. 4, 10 REQUEST C0DE is an IO instruction code, and IOR port stands for 10 RBQUEST, indicating that there is an IO instruction processing execution request. DAT
A REQUST C0DE indicates the content of the processing execution request regarding data transfer (for example, 16-byte store, etc.). DRQ indicates that a processing request regarding data transfer has occurred. It is the individual control unit 7 that sets DRQ on. l0R(1 is set off during priority determination and at the same time IOP is sent on.

Similarly, DRQ is set off during prioritization;
At the same time, DOP is set on.

FIG. 5 is a diagram illustrating how various processing requests taken out by the individual control unit are transmitted to the microprocessor control circuit through the priority order determining circuit, until the channel number and processing request code are transmitted. In Figure 5, 12-1 (i=
0.1.2...) are request registers, 13 is a priority determination circuit, and 14 is a first microprocessor control circuit. Request register 12-0 is assigned to MMRQ, request register 12-1 is assigned to 10RQ, and request register 12-2 is assigned to DRQ.

■ indicates that the processing request stored in the request register is valid. Each request register 12-0.12-1.
12-2. ... stores the channel number and processing request code REQ C0DE. The channel number in the request register indicates which channel the request relates to. When selection permission is specified by the first microprocessor 8, the priority determination circuit 13
Request register 12-0°12-1.12-2. . . . selects one request from among the processing requests stored in . . . according to the priority order, and outputs the selected request. The output from the priority determination circuit 13 is the channel number and RBQ C0DE.
It is composed of MODIFIER. REQ C0
DE MODIFIER is a major classification of request types (MMR
Q, l0RQ, mouth RQ, etc.) and RHQ C0DE. The output of the priority determination circuit 13 is input to the first microprocessor control circuit 14. The first microprocessor control circuit 14 may be considered to generate an address and the like for the control memory of the first microprocessor 8. When the first microprocessor 8 processes the processing request, the first microprocessor 8 issues selection permission to the priority determining circuit 13.
give to

As mentioned above, the individual control unit 7 reads the stack register and control register of the machine number N at the timing determined by the machine number N, but when there is a processing request, it reads out the stack register and control register of the machine number N, provided that the corresponding request register is empty. and writes the processing request to the corresponding request register. If not empty, aircraft number N
Waits until the next timing assigned to the channel.

FIG. 6 is a diagram showing the configuration of one embodiment of the second microprocessor 9. In FIG. 6, 15 is a second microprocessor control memory, 16 is a control memory address register, 17 is a selector, 18 is a shift register for holding addresses, 19 is a control memory data register, and 20 is a tagout register. , 21 is a tag-in register, 22 is a second microprocessor control circuit, and 23 is a write register. Address register 16 specifies the address of control memory 15. After reading from control store 15, the contents of address register 16 are updated and input to the right end of shift register 18. Shift register 18 has 15 register elements. Assuming that the address stored in the address register 16 specifies the storage location of the micro-order for controlling the channel of machine number N, the address stored in the leftmost register element of the shift register 18 is It specifies the storage location of the micro order for controlling the channel of machine number N+1, and the address stored in the next register element is the memory location of the micro order for controlling the channel of machine number N+2. Specifies the location. The same applies hereafter. shift register 18
It goes without saying that the contents of are shifted to the left every l cycles. The selector 17 selects either the upper input or the lower input according to the value of selection instruction No. 18, and inputs the selected address to the address register 16.

The leftmost register element of the shift register 18 is connected to the upper input, and the address generated by the second microprocessor control 1 circuit 22 is supplied to the lower input. Micro orders read from control store 15 are stored in control store data register 19. Depending on the contents of the control storage data register 19, the individual control unit 7
Control of each part of the controller, data writing to the storage means 11, etc. are performed. The second microprocessor control circuit 22
It performs controls such as generating the start address of a microprogram for processing processing requests from the microprocessor 8 and updating control storage addresses according to the contents of the tag-in register 21. Write register 23
The data to be written in the writing tα means 11 is set in .

When the central processing unit 1 sends an input/output command, it operates as follows.

(a) First, the central processing unit 1 inquires of the individual control unit 7 via the general processor 5 and the signal line 1 whether or not the input/output command can be executed.

fb) The individual control unit 7 reads, for example, the control information area of the machine number O in the storage means 11 in the #O cycle, performs determination processing in the next cycle, and writes in the next cycle. If the above inquiry is received during the cycle, it is determined whether or not it is OK, and if it is OK, it is sent to the channel common control unit 6 with [IO instruction code, 10 address,
Instructs to read the "start address of CCW". This instruction is performed by writing predetermined 10 RHQUEST CODIE and l0REQ into the control register of machine number O in the storage means 11. At this time, if the request register 12-1 is empty, this processing request is immediately set in the request register 12-1.

(The C1 channel common control unit 6 reads the To command in accordance with the above processing request.

(d) After analyzing the type of command and reading the CCW, the channel common control unit 6 transmits the command to the individual control unit 7.

MM REQUEST COD[! and MMRQ are stored in the stack register in the following cases, for example. For example, when the first microprocessor 8 takes a long time to process an error, the entire error process is performed by A.

MM REQUES which divides into parts B, C, and D and requests partial error processing B when partial error processing A is completed.
T Write C0DE and MMRQ to the stack register and request partial error handling C when partial error handling B is completed MM REQUEST C0DE and MM
REQ to write RQ to the stack register and request partial error handling when partial error handling C is completed.
Write LIEST C0DE and MMRQ to the stack register of the corresponding channel machine number.

Further, 1. It is assumed that the first microprocessor 8 is performing CCW feed processing. CCW is the command code,
It consists of flags including the Pct flag, data length, data address, etc., but the parts directly required by the individual control unit 7 are the command code, data length, and data address. The process is divided into a process of fetching the command code, data length, and data address from the main memory and sending the command code, data length, and data address to the individual control unit 7, and a Pct process. The first microprocessor 8 fetches the ccw from the main memory and includes the command code 1, the data length, and the data.
After performing the process of sending the address to the individual control unit 7, Pct
If the flag is on, MMR requests PCI processing.
Write EQUEST C0DB and MMRQ to the stack register of the corresponding channel machine number.

〔Effect of the invention〕

As is clear from the above description, according to the present invention, the running mode of the microprogram of the channel common control section is
Instead of being divided into CPU mode and channel mode, IO command processing and processing other than IO commands are made equal, and the processing time for one channel can be shortened.

[Brief explanation of drawings]

Fig. 1 is a diagram showing an overview of a channel processing device to which the present invention is applied, Fig. 2 is a diagram showing the configuration of a storage means for storing control information for each channel, and Fig. 3 is a diagram showing the structure of a storage means for storing control information for each channel. FIG. 4 is a diagram showing the format of part of the channel-specific control information stored in the control register;
FIG. 5 is a diagram showing how various processing requests taken out by the individual control unit are transmitted to the first microprocessor control circuit along with the channel number through the priority determining circuit, and FIG. FIG. 7 is a diagram showing the configuration of an embodiment of the microprocessor No. 2, and FIG. 7 is a diagram showing the configuration of a general computer system having a channel processing device. 1... Central processing unit, 2... Channel processing unit, 3
...Main storage device, 4.Storage control device, 5.General processor, 6.Channel common control unit, 7..
Individual control unit, 8... first microprocessor, 9.
... second microprocessor, 10... channels,
11... Storage means, 12... Request register, 13.
... Priority determination circuit, 14... First microprocessor control circuit, 15... Control memory of second microprocessor, 16... Control memory address register,
17... Selector, 18... Shift register for holding address, 19... Control storage data register, 2
0...Tag-out register, 21...Tag-in register
Register, 22... second microprocessor control circuit.

Claims (1)

[Claims] In a channel processing device in a general computer system, a microprocessor (
a channel common control unit (6) including a channel common control unit (6), an individual control unit (7) that controls processing of each channel cyclically and individually in order of channel number, and a channel common control unit (6) to an individual control unit (7); ), and a control information transmitting means (11) for transmitting control information from the individual control section (7) to the channel common control section (6); A channel common control unit for a series of channel processing, comprising a priority determination circuit (13) that determines the priority of execution of various processing requests taken out from (11) in order of channel number and for each request content. (6)
The processing unit of the microprogram is subdivided, and when the processing of one of the subdivided microprograms is completed, a processing request to be performed next is written to the control information transmission means (11), and various processing requests generated from the individual control unit and A channel control method characterized by re-prioritizing microprocessor usage rights.