JPS6224713A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To increase number of bits without increasing number of resistors and switches by providing a resistor string between a power and common so as to obtain a voltage being a voltage division of the power voltage and using an on-resistance of a transmission gate so as to divide further the said voltage. CONSTITUTION:Other ends of CMOS transmission gates 110, 112, 114 are connected in common (node N5) and other ends of CMOS transmission gates 111, 113 are connected in common (node N6). A decode signal A7 is applied to a gate of N-channel MOS transistor constituting the CMOS transmission gates 117, 118 and a signal being an inversion of the decode signal A7 by an inverter 127 is fed respectively to gates of a P-channel MOS transistors. Then an analog voltage VA corresponding to a digital signal inputted from a connecting point (node N7) between the CMOS transmission gates 115 and 116 is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION This invention relates to digital-to-analog (D/A') converters using resistor strings.

[Technical background of the invention]

Conventionally, resistor string type D/A converters, for example,
It is configured as shown in the figure. Figure 3 shows 3-bit D
/A converter, 8 is connected between the power supply vDD and the ground point.
The resistors R0 to R1 are connected in series. Each of the above resistances R6
=R.

One end of the switch Y-8W0 to SW is connected to one end of the switch Y-8W0 to SW, respectively. And the above switches SW0 to SW,
is controlled on/off in accordance with the input digital signal, and an analog voltage A is obtained from the common connection point on the other end side of the switches SWo to SW. In addition, the above resistance Ro "" R
The resistance values of y are all the same, and in the case of MO8C, it is composed of a diffusion layer, a polycrystalline silicon layer, a metal layer, etc. Also, the above sweets fsW0~SW? is designed so that no more than two switches are turned on at the same time, and each switch! 9Wo,S
W is an Nf Jarnel type MO8 as shown in Fig. 4 (al K).
) a transmissive gate consisting of a runlister Qt;
FIG. 4 (P-channel type MO8 as shown in bl) run lister Q! or N-channel type MO8 as shown in Figure 4 (cl ItC).
) Run Lister Q1 and Pf Yarnel type MO8) Run Lister Q
, and the like are connected in parallel. The MO8) run lister Q--Q* functions as a switch by being controlled to be conductive by the control signal φ,1.

The relationship between the input digital signal, the switch that is closed (turned on), and the output analog voltage vA is shown in Table 1 below.

Table 1 Now, if 000 is input as a digital signal, SWo is closed (turned on) and the analog voltage is set to 7.
O/s VDD J (m92nd position) is output. Also, if the digital signal is 001, switch SW
1 is closed and the analog voltage 7 is r 1/8 V
DD J is output. Thereafter, similarly, as shown in Table 1 above, the switch corresponding to the input digital signal is closed, and the analog voltage 7 corresponding to the digital signal is
People are output.

The relationship between the digital signal and analog voltage shown in Table IK above is shown in a graph in FIG.

FIG. 6 shows a schematic diagram of a 4-bit resistor string type linear converter. In the case of 4 bits, the basic configuration and operation are the same as in the case of 3 bits described above. However, in the case of a 4-bit D/person converter, the number of resistors and switches is twice that of the 3-bit case, and there are 16 resistors R0 to R0 and switches SW, to SW.
,, are required. In Fig. 7, D/ of Fig. 6 above is shown.
A converter input digital signal and output analog voltage vA
Indicates the relationship between

[Problems with background technology]

Incidentally, an n-bit resistor string type D/A converter generally uses two resistors and two switches. This means that the area occupied by the resistor and switch doubles for each additional bit. Therefore, as the number of pits increases, more of the area in the resistor string converter is occupied by resistors and switches.

The manufacturing cost of an IC increases in proportion to the area of the IC if the manufacturing process is the same, so resistor string type D/A converters with a large number of bits become expensive due to the increased area occupied by the resistors and switches. There are drawbacks to doing so.

[Purpose of the invention]

This invention was made in view of the above circumstances,
The purpose is to provide a digital/analog converter in which the number of pits can be increased without significantly increasing the number of resistors and switches. In order to achieve the above object, a resistor string is provided between the power supply and the ground, a voltage obtained by dividing the above power supply voltage by the resistor is obtained from one end or the other end of each resistor that constitutes the resistor string, and this voltage is applied to a transformer. By further dividing the voltage using the on-resistance of the Mitsushicon gate, an analog voltage is obtained from K.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a 4-bit CMO 8 resistor string type D/A converter.

Four resistors R, to R8 are connected in series between the power supply VDD and the ground point. At one end side node N of the resistor R0,
P-channel type MOS) run lister and N-channel type M
OS) 0MO8 as a switch consisting of a run lister
) One end of the transmissive gate 11G is connected, and the other end nodes N, -N4VC of the resistors R0 to R3 are connected to the transmissive gates 11, -11, respectively.
One end of 4 is connected. Each of the above CMO8) N-channel type M constituting the transmission gates 116 to 114
OS) Each gate of the run lister receives a decoded signal A' obtained by decoding the input digital signal. ~
A4 is supplied, and the gates of the P-channel MO8 transistors are supplied with signals obtained by inverting the decode signals A0 to A4 by inverters 120 to 124, respectively, to control conduction.

In addition, the above CMO 8) Lance Mitsushikon Gate 11o
, J 1. , J J, the other end is a common connection (node Ns)
and the above CMO8) Lancemissi Adventure Game) I J
The other ends of I and I J3 are commonly connected (node N6). The above nodes N,,N.

Between Ka, 0MO8) Lance Mitsushikon Gate 11s,
116 are connected in series, and 0MO8) transmissive gates 11. .

11 are connected in series. CMO8) N-channel MO constituting the transmissicon gates ll, , 116
8) Decode signal A is applied to each gate of the run lister.
, , A, are supplied to the gate of the P-channel type MO8) run lister, and the decoded signals A, , A are applied to the inverters 12s, 12. An inverted signal is supplied.

In addition, 1 above CMO 8) Lance Mitsushikon Gate 11, .
11. A decode signal A is supplied to the gates of the Nf'' Yarnell type MOS transistors constituting the P
The gates of the channel type MO8) run listers are connected to the inverters 12. An inverted signal is supplied. And the above CMO8) Lancemitsu i/
II ingate l no, and 1 no. connection point (node Ny
) to obtain seven analog voltages corresponding to the input digital signals.

To the input digital signal and the above decoded signal 〇～A
, is shown in Table 2 below.

Table-2 Next, in the configuration as described above, the information is input.

The operation will be explained by taking as an example the case where the digital signals are 0100, 0101, 0f10, and 0111. When the digital signal is 0100, the decoded outputs A, , A, are 1", and all others are 1O". Therefore, 0MO8)LanceFage)JJl, 116 is turned on, and other CMOS
Since the transfer gate is turned off, its equivalent circuit becomes Ki as shown in FIG. 2(a). FIG. 2 (resistances r, , r, in al itc are 0MO8) are the on-resistances of the transmixing gates 111 and 116, and their resistance values are sufficiently large compared to the resistors R0 to R. Therefore, node N,
The desired 1/4VD is output as an analog voltage vA.

When the digital signal is 0101, the decode signal A1
*AH, A6, AV are '1'', all others are 0
” Stops. This allows 0MO8) Transfer Gate J 1..112, 116, 11.

11a turns on, 0MO8) transfer gate 11o
, 11. ．． 114.11. turns on.

Therefore, the circuit of FIG. 1 can be expressed as an equivalent circuit as shown in FIG. 2 (bl). In FIG. '
a *”I and r, (0MO8) 7 sumi 1 game) JJ, , 11.. 11. ON resistance)
are connected in series. These resistances r1 *'@, r
? Since the combined resistance value of R and r is sufficiently larger than the resistance value of resistor R8, the presence of a parallel resistance to R can be almost ignored. In the configuration shown in FIG. 2(b), the voltage at node N6 is output as seven analog voltages. Now, each of the above CMO 8) Lanmissi Invasion Gate 11
Assuming that the on-resistances of o to 118 are all equal, the voltage at node N6 is 1/4 (±
1/16■DD) VC/F N t O voltage (=
”/4 VDD) wo processing*voltage, that is 5/16v
DD is output.

When the digital signal is 0110, the decode signal AI
, A, , A, and person are each ``1'', and all others are 1O''. Therefore, 0MO8) Transmitsushi Engate J11.

11. 11. and 116 are turned on, and all others are turned off. The equivalent circuit at this time is shown in FIG. 2(c)K. Figure 2 (
In C1, the voltage at node N, is equal to the voltage at node N, ,N,
1/(/16?=2 VDD) of the voltage between Ic/-FN,', OK pressure (=”/4 V
DD), that is, 8/16 VDD, and this voltage is output as an analog voltage.

When the digital signal is 0111, the decode signal A1
, A, A, and A are @1, all others are 10"
It becomes. Therefore, the CMOS transmissive code 111gll*.

11s, 1.1', and 11. is on and all others are off. The equivalent circuit at this time is shown in FIG. 2(d). In FIG. 2 (dl, the voltage at node N is
, N, 3/4 of the voltage between (=3/16VDD) K
/-1'Nt f:)'II pressure (= ”/4 VDD
), that is, 7/, 6VDDVc, and this voltage becomes the analog voltage 7 (below, in the same way, other digital signals are 0MO8)
The transmission gates 11° to 11 are selectively turned on/off using decode signals A0 to 11 as shown in Table 2 above.
By controlling off, seven analog voltages corresponding to the input digital signals are obtained.

As mentioned above, according to the configuration shown in FIG.
The number of bits can be increased without significantly increasing the number of resistors and switches.

For example, in the case of 4 bits, the conventional configuration required 16 resistors and switches, whereas the configuration of the present invention requires only 4 resistors and 9 switches.

[Effect of invention]

As explained above, according to the present invention, a digital-to-analog converter can be obtained in which the number of resistors and switches can be increased without significantly increasing the number of resistors and switches.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing a digital/analog converter according to an embodiment of the present invention, FIG. 2 is an equivalent circuit diagram for explaining the operation of the circuit shown in FIG. 1, and FIGS. 3 to 7 1 and 2 are diagrams for explaining conventional digital/analog converters, respectively. VDD...power supply (reference voltage source), R0~R8...resistance, 11°~11. ... Transmilan seal! G group, 11. ．． 11. ...First. Second transmitsushiran gate, 111. l1m...3rd. 4th transmission game), Ao~A,...decode signal, 7 people...analog voltage. Applicant's agent Patent attorney Takehiko Suzue Figure 1

Claims (1)

[Claims] A resistor string provided between the first and second reference voltage sources, and one end connected to the connection point of each resistor constituting this resistor string and the first and second reference voltage sources, and the odd-numbered and even a group of transmission gates whose other ends are connected in common; first and second transmission gates which are connected in series between common connection points on the other end sides of the odd-numbered and even-numbered transmission gate groups; 3rd and 4th connected in series between common connection points
a transmission gate, selectively supplying a decode signal of the input digital signal to each transmission gate of the transmission gate group and the first to fourth transmission gates to perform on/off control; A digital/analog device characterized in that an analog voltage is obtained from the connection point of the first and second transmission gates, and the same decode signal is supplied to the third and fourth transmission gates for on/off control. converter.