JPS6224675A - Non-volatile memory and making thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to the field of integrated circuit manufacturing. More particularly, the present invention relates to the field of electrically programmable read only memory (EPROM) manufacturing.

Prior Art and Problems EPROMs are read-only memory devices in which stored data can be erased and new data written in its place.

A widely used format, EPROM, is a floating
It is a gate field effect transistor type. Suze's book [Physics of Semiconductor Devices J
(See 1981 > Chapter 8.61.

A partial circuit diagram of an EPROM using floating gate field effect transistors is shown in FIG.

Memory cells 26-1-1 through 26-2-4 are floating gate field effect transistors. In response to signals applied to row address input lines 21 from read/write indicator 23, row decoder 28 selects row lines 24-1 and 24-1.
4-2 generates an output signal. In response to signals applied on column address input line 22 and from read/write indicator 23, column decoder 29 generates and receives signals on column lines 25-1 through 25-5.

The output signal of the memory is available on output line 27.

For example, the data stored in the memory cell 26-1-1
When reading a bit, a high voltage output signal is generated on row line 24-1 and a low voltage output signal is generated on all other row lines. At this time, the column decoder 29 senses the impedance of the memory hill 26-1-1 via the column lines 25-1 and 25-2. If the floating gate of memory cell 26-1-1 has an excess of electrons, the negative charge of these excess electrons increases the threshold voltage of memory cell 26-1-1, thus causing row line 24 The voltage available at -1 is insufficient to cause the channels of memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects the high impedance and generates the appropriate signal on output line 27. If no excess electrons are stored in the floating gate of memory hill 26-1-1, row line 24-1
The voltage applied to is sufficient to cause memory cell 26-1-1 to conduct. Therefore, column decoder 29 detects the low impedance and generates the appropriate signal on output line 27.

EPROM 20 is thus programmed by negatively charging the 70-ting gates of selective memory cells. For this reason, from the memory cell substrate,
Hot electrons are injected through the insulating layer beneath the floating gate.

When manufacturing EPROMs using conventional methods (e.g., U.S. Pat. No. 4.151.021, issued to Musk Roy on April 24, 1979, Title: Method for Manufacturing Highly Concentrated 70-Ting Gate EPROMs). The problem arises when forming the thick field region 29 of FIG. 4b of this patent.

Conventionally, such regions are formed by thermal oxidation.

Thermal oxidation consumes silicon not only vertically but laterally from the substrate. Therefore, when patterning the oxide mask for thick oxide regions, buffer regions must be provided to accommodate this lateral movement of the oxide regions. This buffer area can be EPRed using conventional methods.
Increases the surface area of the substrate required to fabricate the OM.

L ” 2 E Using the method of one embodiment of the present invention, a highly integrated EPRO
It is possible to manufacture an EPROM array that is an M array.

First, a polycrystalline silicon floating gate and gate oxide layer are formed and partially patterned over the surface of the substrate. A thin thermally grown oxide layer is then formed over the entire array. Source/drain regions are then implanted into the substrate through this thin silicon dioxide layer. A thick silicon dioxide layer is then deposited over the surface of the array by chemical vapor deposition. That contact,
Coat the surface of the array with photoresist. This photoresist, by its nature, creates a planarized surface on the upper layer of photoresist. Next, the photoresist and silicon dioxide layers are etched using an etching method such that the etching ratio of photoresist to silicon dioxide is 1:1. The photoresist is completely removed by etching, leaving no planarized silicon dioxide surface. The silicon dioxide layer is then further etched to expose the top surface of the floating gate. An interlayer dielectric layer is then formed over the surface of the array, and an active gate is then formed over the surface of the interlayer dielectric.

Another embodiment of the invention includes forming refractory metal silicide regions on the bit lines of the array. The use of silicided bit lines in this type of array is difficult because traditional methods require the thermal growth of thick field oxide regions on top of the silicided regions.
Previously, this was not possible. It is very difficult, if not impossible, to grow silicon dioxide over silicided regions. Yet another embodiment of the invention provides a polysilicon "cap" over the top surface of the floating gate. These "key A7 tubes" strengthen the capacitive coupling between the active gate and the floating gate, thus increasing programming efficiency.

Embodiment FIGS. 2A to 2E are simplified side views showing the processing steps of one embodiment of the present invention. Figures 2A-2E represent a cross-section of one of the arrays constructed in accordance with the ideas of the present invention. A polycrystalline silicon layer 33 and a gate oxide layer 32 are formed over the surface of substrate 31 using methods well known in the art, resulting in the structure shown in FIG. 2A. Next, the structure of FIG. 2Δ is subjected to thermal oxidation to form a silicon dioxide layer 36.

The silicon dioxide layer 36 is used as one method to improve charge retention on the floating goo 1. Then an energy of about 150 kiloelectron volts and about 5E15
Dopant ion implantation is performed, such as arsenic ions with a density of (5×10 ) ions/α2. This ion implantation is driven in to form source/drain regions 34 shown in FIG. 2B. A thick layer of silicon dioxide is then formed over the surface of the structure of FIG. 2B by chemical vapor deposition to form a silicon dioxide layer 37 shown in FIG. 2C. A photoresist layer is applied over the surface of the silicon dioxide layer 37 to provide a photoresist layer 38 . Because the photoresist used to create photoresist layer 38 is liquid when applied, the surface of photoresist layer 38 is nearly planar. Next, the structure of FIG.
An anisotropic etching method is applied, such as etching with an etching ratio of 1 to 1. The etch rates of various etching systems vary widely, and each system must control its process to provide a roughly one-to-one etch rate of photoresist and silicon dioxide. However,
This ratio was achieved using a plasma etching method using a C2F6+C to IF3+02 plasma. Etching is continued until the surface of polysilicon layer 33 is exposed. The resulting structure is shown in Figure 2D.

An interlevel dielectric layer 39 is then formed over the surface of the structure of FIG. 2D, as shown in FIG. 2E.

An active gate material, such as a polycrystalline silicon layer 40, is then formed over the surface of the living room insulator layer 39.

Polysilicon layer 4o forms the word lines of the EPROM array manufactured using this embodiment of the invention. Importantly, the surface of the polysilicon layer 40 is planar, and this layer 40 is formed on the sides of the polysilicon layer 33 used to form the floating gates of the memory cells of the EPROM array. This is not to be done. Since the polycrystalline silicon layer 4o is not formed on the side surfaces of the polycrystalline layer 33, the polycrystalline silicon layer 40 can be completely etched away without leaving any harmful filaments (linear etch residue).

In another embodiment of the invention, a masking layer 42 comprised of a silicon dioxide layer and a silicon nitride layer is formed and patterned along polycrystalline silicon layer 33, as shown in FIG. 3A. Next, a thin oxide layer 36 is grown by thermal oxidation. The resulting structure is subjected to ion implantation as previously described with respect to FIGS. 2A-2E.

As a result, source/drain regions 34 are formed as shown in FIG. 3Δ. (In FIGS. 3A to 3C, parts with the same reference numerals as in FIGS. 2A to 2E have the same functions.) Next, as shown in FIG. 38, by chemical reaction vapor phase growth, A silicon dioxide layer 45 is formed over the structure of FIG. 3A and then anisotropically etched back to form a third C.
A sidewall silicon dioxide layer 47 is formed as shown. This anisotropic etching method completely removes the silicon dioxide layer 45 above the source/drain regions 34, but does not remove the mask layer 42 above the polysilicon gate 33. This structure is then subjected to a contact silicidation process using methods well known in the art to form a refractory metal silicide region 43 on the surface of the source/drain region 34.
form. These silicide regions lower the sheet resistance of the source/drain regions 34 and the number of contacts from the metal column lines (not shown in the drawings) used to compensate for the higher resistivity of the source/drain regions 34. Minimizes the potential for use of source/drain regions 34 as column lines for the EPROM. Furthermore, the silicide regions 43 make better ohmic contact to the metal column lines (not shown in the drawings) that contact the source/drain regions 34. These properties lower the overall resistance of the column lines, thus reducing the resistance-capacitance product and increasing the speed of the memory array for circuits containing such column lines.

In yet another embodiment of the invention, a polycrystalline silicon "cap" 46 as shown in FIG. 4A is formed by depositing and patterning a thin polycrystalline layer over the surface of the structure of FIG. 2D. Form. The structure of FIG. 4Δ is further processed as described for FIG. 2E to form the structure of FIG. 4B. The structure of FIG. 4B provides greater programming efficiency by increasing the capacitive coupling between word line 40 and floating gate 33. This stronger capacitive coupling results in a stronger electric field across gate oxide layer 32 (for the same substrate and active gate voltages) than in the structure of FIG. 2E.

This stronger electric field increases the number of electrons injected through the gate oxide layer 32, thus improving programming efficiency.

FIG. 5 is a perspective view of an EPROM manufactured using the process described in FIGS. 2A-2E. FIG. 5 has a bit line isolation region 50 which is a P-doped region formed using methods well known in the prior art.

The method of the present invention allows for the production of very shallow source/drain regions because the field oxide regions are formed by chemical vapor deposition rather than thermal oxidation, which rapidly diffuses dopants. This is a method for manufacturing EPROM. This has the advantage of less lateral diffusion and more thick electron formation. Additionally, smaller EPROM arrays can be fabricated because the field oxide regions are not formed by thermal oxidation, which causes lateral diffusion of the field oxide regions. Furthermore, silicided sources/
A drain can be formed.

In connection with the above description, the following sections are further disclosed.

(1) In a method of forming a nonvolatile memory, a semiconductor substrate is prepared, a conductive strip is formed on the surface of the substrate insulated from the substrate, and the conductive strip is formed between the conductive strip and the lip. forming a source/drain region in the substrate; forming a layer of insulating material between the conductive strip I and the lip layer having a top surface substantially the same as the top surface of the conductive stop; forming a layer of electrically conductive material between the conductive strips with a coplanar upper surface, forming a layer of electrically conductive material on the surface of the insulating material and insulated from the conductive strip; Etching a layer of conductive material and the conductive strip to form a word line extending from the layer of conductive material perpendicular to the conductive strip and a floating line disposed from the conductive strip below the word line. A method including forming a gate.

(2) In the method described in item (1), the substrate is made of crystalline silicon.

(3) In the method described in item (1), the conductive strip is made of polycrystalline silicon.

(4) In the method described in item (1), the insulator layer is made of silicon dioxide.

(5) The method of paragraph (4), wherein the insulator layer is deposited by chemical vapor deposition.

(6) In the method described in item (1), the layer of conductive material is made of polycrystalline silicon.

(7) Prepare a semiconductor substrate, and on the surface of the substrate,
forming a conductive strip insulated from the substrate, forming a source/drain region in the substrate between the conductive strips, depositing a conformal layer of insulating material over a surface of the substrate and the conductive strip; to the point where the top surface of the layer of insulating material is substantially flush with the top surface of said conductive strip;
planarizing the layer of insulating material to form a thin conductive strip over the surface of the conductive strip, the thin conductive strip being wider than the conductive strip and extending over the surface of the conformal layer as well as the thin conductive strip; forming a layer of conductive material on a surface thereof, insulated from the strip, etching the layer of S-type material, the thin conductive strip and the conductive strip to form the conductive strip from the layer of conductive material; A method of forming a non-volatile memory comprising forming a word line extending perpendicularly to the conductive strip and forming a floating gate disposed below the word line from the conductive strip and the thin conductive strip.

(8) a plurality of source/drain regions formed in a substrate, a plurality of channel regions disposed between the source/drain regions in the substrate, and a plurality of channel regions formed adjacent to the channel regions; a plurality of floating gates insulated from the floating gates; a plurality of active gates formed over a surface of the field oxide region and over the floating gate but insulated from the floating gate; A non-volatile memory array having

(9) In the nonvolatile memory array described in paragraph (8), a nonvolatile memory array in which a highly conductive region is formed in the source/drain region. 〇 (10) According to paragraph (9) In the nonvolatile memory array described above, the high conductivity region is composed of high melting point metal silinide. a non-volatile memory array in which the active gate is isolated from the floating gate by a dielectric comprised of layers of silicon nitride and silicon dioxide;

(12) The nonvolatile memory array according to item (8), in which the field isolation region is made of silicon dioxide.

(13) The nonvolatile memory array of paragraph (8), wherein the field isolation region is deposited by chemical vapor deposition and planarized.

(14) A plurality of source/drain regions formed in the plate thickness, a plurality of channel regions located in the substrate between the source/drain regions, and a plurality of channel regions formed adjacent to the channel regions. is disposed between a plurality of floating gates insulated therefrom and the floating gel, formed on the surface of the substrate, and having an upper surface substantially coplanar with the upper surface of the floating gate. a plurality of isolation regions; a plurality of conductive layers formed on surfaces of the floating gate and field isolation regions; and a plurality of conductive layers insulated from the surface of the field oxide region and the conductive cap. a plurality of active gates formed on a surface of an electrically programmable memory array.

(15) The method described in item 11), further comprising the step of forming a layer of a highly conductive material on the surface of the source/drain region.

(16) In the method described in item (15), the highly conductive layer is made of metal silicide.

(17) The method described in item (7), further comprising the step of forming a layer of a highly conductive material on the surface of the source/drain region.

(18) In the method described in item (17), the highly conductive material is formed of metal silicide.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an EPROM, FIGS. 2A to 2E are simplified side views showing the processing steps of one embodiment of the present invention, and FIG.
Figures 3A-3C are simplified side cross-sectional views of another embodiment of the invention including a silicide source/train region;
Figure 4B shows the active gate of an EFROM cell and 70
FIG. FIG. 2E is a perspective view of an EPROM manufactured using the process described in connection with FIGS. 2E. Explanation of main symbols 31: Substrate 32: Gate oxide layer 33: Polycrystalline silicon layer 34: Source/train region 37: 2M silicon layer 39: Interlayer insulator layer 40: Polysilicon layer

Claims (1)

[Claims] (1) In a method for forming a nonvolatile memory, a semiconductor substrate is prepared, conductive strips are formed on the surface of the substrate insulated from the substrate, and conductive strips are formed in the substrate between the conductive strips. forming a source/drain region and forming a layer of insulating material between the conductive strips having a top surface substantially identical to a top surface of the conductive strips and insulating the layer over the surface of the layer of insulating material as well as from the conductive strips; forming a layer of conductive material on the surface, and etching the layer of conductive material and the conductive strip to form a word line extending from the layer of conductive material perpendicular to the conductive strip. and forming a floating gate disposed below the word line from the conductive strip. (2) a plurality of source/drain regions formed in a substrate, a plurality of channel regions disposed between the source/drain regions in the substrate, and a plurality of channel regions formed adjacent to the channel regions; a plurality of floating gates insulated from the floating gates; and a plurality of active gates formed over a surface of the field oxide region and over the floating gate but insulated from the floating gate. Non-volatile memory array.