CN1082723C - Read only memory structure and manufacture thereof - Google Patents
Read only memory structure and manufacture thereof Download PDFInfo
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- CN1082723C CN1082723C CN97105499A CN97105499A CN1082723C CN 1082723 C CN1082723 C CN 1082723C CN 97105499 A CN97105499 A CN 97105499A CN 97105499 A CN97105499 A CN 97105499A CN 1082723 C CN1082723 C CN 1082723C
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Abstract
The present invention relates to a read only memory structure comprising an insulation substrate layer, a lattice structure, a first insulation layer, a second insulation layer and word lines, wherein the lattice structure is composed of a plurality of separated position lines which are parallel to an X direction, and separated channel regions connected with the position lines; the channel regions are vertical to the X direction and are parallel to a Y direction; the lattice structure is formed on the insulation substrate layer; the first insulation layer is filled with the lattice structure; the second insulation layer is formed on the surface of each layer; the separated word lines are parallel to the Y direction and are formed on the surface of the second insulation layer, wherein the word lines correspond to the channel regions; the channel regions can contain more than two different starting voltages.
Description
The present invention relates to a kind of read-only memory structure and manufacture method thereof, particularly relate to a kind of amorphous silicon read-only memory structure and manufacture method thereof.
Read-only memory has been widely used in mini computer, and in the digital device of a class such as microprocessor system, it can be used to store some system datas, for example resident program such as BIOS.Because the manufacturing process of read-only memory (being called for short ROM) is very complicated, and the processing of a lot of time-consuming steps of needs and material, therefore, the client normally earlier gives memory manufacturing works with routine data, by factory it is coded among the ROM again, to make finished product.
Most ROM element is except sequencing (programming) the data difference that the stage deposited in, remaining structure is all identical, therefore, read-only memory can be fabricated into the step before the sequencing earlier, and with this not the semifinished product warehouse of sequencing store away, treat that the client sends here after the order of specific program, can make photomask rapidly, to carry out sequencing, the client is given in shipment again, so above-mentioned back sequencing photomask formula read-only memory has become the industry customary way.
General read-only memory commonly used is to utilize channel transistor to be used as memory cell (memory cell), and in the sequencing stage, optionally implanted dopant is to the dedicated tunnel district, changes starting voltage (threshold voltage) and reaches control store cell conduction (ON) or close the purpose of (OFF) with mat.The structure division of read-only memory wherein, polysilicon word line WL (Word Line) strides across bit line BL (Bit Line), and the passage of memory cell then is formed at below that word line WL covered and the zone between the bit line BL.And whether read-only memory promptly injects with the ion of passage, comes stores binary data " 0 ", " 1 ".
Please refer to Fig. 1, Fig. 1 shows the part equivalent circuit diagram of the photomask read-only memory 10 of prior art, comprising some word line WL that arrange in the parallel array mode and the bit line BL that arranges in the parallel array mode.The data of after 10 sequencing of photomask read-only memory, being stored, be by selecting these memory cell that is positioned at word line WL and bit line BL intervening portion decisions, for example reaching the purpose of storage data by these the different starting voltages that memory cell had (threshold voltage) combinations on intervening portion.Wherein, has relative low starting voltage by transistor 12 formation that will be positioned at bit line BL0 and word line WL0 intervening portion, and will be in logic the data storing of " 0 " or " ON " in this transistor 12, or form by the transistor 14 that this is positioned at word line WL0 and bit line BL2 intervening portion and to have relative high starting voltage, and with data " 1 " or " OFF " is stored in this transistor 14.
And the mode of data read, be that pairing this bit line in memory cell position and the word line that will desire reading of data imposes a specific potential (potential), and whether the electric current of measuring this bit line change, and decides this transistor that constitutes memory cell whether low starting voltage is arranged.For example, select one to have the transistorized position of low starting voltage as 12, this transistorized grid (joining with word line) and drain electrode (joining with bit line) are applied a specific potential, make this transistor turns, then, can learn that the stored data of this memory cell are " 0 " or " ON " in logic according to the size of current on this bit line that records.In like manner, in this example, if this memory cell is made up of a transistor with high starting voltage, transistor as shown in the reference numeral 14, then the specific potential that is applied on its grid can't make this transistor turns, so this storage data is in logic " 1 " or " OFF " as can be known.
Please refer to Fig. 2, Fig. 2 shows the part pattern of the photomask read-only memory of a prior art, these photomask read-only memorys are formed on the P type silicon base 20, and imbed bit line (buried bit lines) 22,26 and paratope line 24,28 with what N type impurity (N-typeImplantations) injected that parallel array arranges.This bit line 22,26 is connected to a power line V, these paratope line 24,28 ground connection, and these transistors are then as the memory cell of storage data.This photomask read-only memory also has word line WL0, WL1 etc.These word lines are haply perpendicular to these bit lines, and are transistorized gate regions.In these word lines and the formed transistor of bit line intervening portion, a part of transistor forms the passage area 30 with low starting voltage, and remaining field-effect transistor forms the passage area 32 with higher relatively starting voltage.
As for traditional read-only memory manufacturing, then as shown in Figure 3, it is presented at a kind of method of sequencing of the photomask read-only memory of the prior art among Fig. 1,2.At first, inject N type impurity on silicon base 15, for example, arsenic ion to form a plurality of buried bit lines that are equally spaced (buried bit lines) 11, then constitutes channel region between the buried bit line 11.Secondly, carry out oxidation operation, and utilize different oxidations rate, form the thin oxide layer 17b of thicker separator 17a in buried bit line 11 tops and channel region top.Then, deposit a polysilicon layer and constitute pattern, form word line 13, constitute channel transistor, finish the semi-finished product manufacturing of conventional photomask read-only memory across bit line through etching.Then carry out the operation of this photomask rom programization, form a mask layer 19, the channel region 15 that exposes the desire coding, p type impurity reinjects, boron ion for example, finish coding and inject (Code Implanyt) operation, and in the programmed process of this photomask read-only memory, then can decide different doped source according to different transistor characteristics.
Wherein in this photomask read-only memory, transistorized starting voltage is decided by that just its channel region injects the degree of doped source, for example, can inject suitable doped source in these transistor channels districts that set in logic " 1 " or " OFF " for; And these will be set in the transistor channels district of in logic " 0 " or " ON ", then not inject any doped source.
Yet above-mentioned photomask read-only memory can produce following point in programmed process:
(1) many buried bit lines that are equally spaced form with implanted dopant on silicon base (Implant Dose), when element dwindles, if with too high incorporation, easily cause horizontal proliferation (Lateral Diffusion), adjacent leakage current (Junction Leakage), reach the phenomenon that breakdown voltage value can't improve, so can't effectively improve component density.
(2) planarization (claims complanation again, plananzation) be one of very important step on the present semi-conductive technology, therefore how to reduce wafer surface and shorten the influence that is caused because of interelement distance, and with the planarization in addition that rises and falls of the height on surface, be the task of top priority that must solve in present very lagre scale integrated circuit (VLSIC) (VLSI) technology, yet in existing technical process, owing to form insulating oxide with thermal oxidation (Thermal Oxide) step, therefore form the technology planarization fully of memory cell.
Purpose of the present invention just is to address the above problem, and a kind of read-only memory structure that improves component density and help planarization is provided.
For achieving the above object, the invention provides a kind of read-only memory structure, comprising:
One surface has the substrate of one first insulating barrier;
One makes the semiconductor layer that grid is arranged, it is formed on this first insulating barrier, and be divided into along the parallel bit line of being separated by of a first direction, along one with the vertical second direction of first direction and a parallel channel region and the boundary grid gap between this bit line and channel region that is separated by and connects each bit line;
One second insulating barrier fills up these grid gaps;
One the 3rd insulating barrier is formed on above-mentioned each laminar surface;
One conductor layer is formed on the 3rd insulating barrier, and becomes many along the parallel lead of being separated by of second direction through etching, and wherein the position of these many leads and these channel regions are overlapping.
Wherein in read-only memory structure, this conductor layer can be polysilicon layer, tungsten or titanium coating.And this semiconductor layer can be amorphous silicon layer or polysilicon layer, and above-mentioned insulating barrier is a silicon oxide layer, and this multiple bit lines distributes with equi-spaced apart each other in addition.
This is external read-only memory structure is carried out sequencing coding after, these channel regions have set ion doping concentration respectively, to produce different starting voltages.
Another kind of read-only memory structure of the present invention comprises:
One dielectric base layer;
One trellis, by many along the parallel bit line of being separated by of a first direction, form along a parallel channel region and a boundary grid gap between this bit line and channel region that is separated by and connects each bit line with the vertical second direction of first direction, it is formed on this dielectric base layer;
One first insulating barrier fills up these grid gaps;
One second insulating barrier is formed on above-mentioned each laminar surface; And
Many are formed at this second surface of insulating layer along the parallel lead of being separated by of second direction, and wherein these many leads are corresponding to these channel regions.
Wherein, this lead is as word line, the encoded injection of these channel regions.
And the manufacture method of a kind of read-only memory of the present invention comprises the following steps:
(a) in a substrate, form one first insulating barrier;
(b) on this first insulating barrier, form semi-conductor layer;
(c) to this semiconductor layer composition, through etching form a plurality of first directions part and one and its mutually perpendicular a plurality of second directions parts, and these two parts between the trellis that constitutes of grid gap;
(d) in these grid gaps, fill up one second insulating barrier;
(e) this second direction partly is defined as channel region, and this first direction is partly formed bit line;
(f) form one the 3rd insulating barrier at above-mentioned each laminar surface;
(g) form a conductor layer on the 3rd insulating barrier, and form many along the parallel word line of being separated by of this second direction through etching, wherein these many word lines are corresponding to these channel regions; And
(h) to these channel regions encode composition and implantation step, finish the manufacturing of follow-up read-only memory.
In addition, above-mentioned steps (a) also can directly replace with a dielectric base.
Below in conjunction with accompanying drawing in detail the preferred embodiments of the present invention are described in detail.In the accompanying drawing:
Fig. 1 shows the part equivalent circuit diagram of the photomask read-only memory of prior art;
Fig. 2 shows the part pattern of the photomask read-only memory of a prior art;
Fig. 3 is presented at a kind of method of sequencing of the photomask read-only memory of the prior art among Fig. 1,2; And
Fig. 4 A to 4J shows the manufacturing process of the preferred embodiment of read-only memory of the present invention.
According to a preferred embodiment of the invention, a kind of making step of read-only memory structure is as follows.
See also Fig. 4 A-4C, at first select a dielectric base layer, or in a substrate 40, form an insulating barrier 41 earlier; Secondly, form semi-conductor layer 43 on this insulating barrier 41, it forms the trellis as Fig. 4 C through etching.
For example Fig. 4 A forms oxide layer 41 to substrate 40 surfaces earlier, then as Fig. 4 B, deposition forms semi-conductor layer 43 on this oxide layer 41, this semiconductor layer is P type or N type, and is one of amorphous silicon layer and polysilicon layer, as intrinsic amorphous silicon layer (Intrinsic Amorphous Silicon Layer), and through the ion doping step to adjust concentration, wherein, an embodiment of this step is under about 350 ℃～575 ℃, utilizes plasma reinforced chemical vapour deposition method (PECVD) with SiH
4Decomposing gas is deposited as amorphous silicon layer, then adjusts its concentration with ion doping step such as boron ion.
Secondly shown in Fig. 4 C, limit the pattern of trellis with lithography process, it is through this amorphous silicon layer 43 of etching, and form many parallel directions X semiconductor layer 43a, 43b of being separated by, parallel Y direction semiconductor layer 50a-50f of being separated by with many, wherein this Y direction semiconductor layer such as 50a-50f connect this directions X semiconductor layer such as 43a, 43b, and then are grid gap 45 between directions X semiconductor layer 43a, 43b and this Y direction semiconductor layer 50a-50f.
See also Fig. 4 D, 4E, as Fig. 4 D, this step is for to fill up an insulating barrier 44 with flatening process in the grid gap 45 of this trellis.One preferred embodiment for above-mentioned each laminar surface with " revolve and cover glass " (SOG) process deposits one oxide layer as 44, after etch-back, fill up this grid gap 45 (Fig. 4 C), to form the effect of planarization, in addition, this step also can chemical mechanical milling method (CMP) technical process replace.
Secondly as Fig. 4 E, this step is used for limiting multiple bit lines and channel region, and this bit line is carried out ion implantation technology.For example be coated with one deck photoresist earlier, behind exposure imaging, zone between this adjacent two bit line 43a, 43b forms strip photoresist layer 51a, 51b, a 51c who covers, in order to these many parallel Y direction semiconductor layer 50a-50f of being separated by are defined as channel region, these many parallel each other directions X semiconductor layer 43a, 43b of being separated by then are defined as the bit line that connects each channel region, subsequently at this bit line 43a, 43b dopant ion to reduce its resistance, as with the first type impurity, the arsenic ion of N type (As) injects to form a plurality of N spaced apart
+Bit line is removed this layer photoresist 51a-51c with appropriate solvent afterwards.
See also Fig. 4 F, this step is for to form an insulating barrier 49 and a conductor layer 53 successively at above-mentioned each laminar surface.For example deposit an oxide layer 49 earlier, on this oxide layer 49, form a conductor layer 53 then, one of group that one preferred embodiment is made of polysilicon, tungsten, titanium, aluminium etc. for this conductor layer constitutes, its can physics (PVD) or chemical vapor deposition method (CVD) deposit formation.
See also Fig. 4 G, this step is for limiting lead such as word line.For example with the lithography process step to these conductor layer 53 compositions and etching forms many along parallel line 53a, 53b of being separated by of direction Y and therebetween groove 55a, 55b, 55c, wherein these many word line 53a, 53b are corresponding to these channel regions 50a-50f.
And a plurality of metals-oxides-semiconductor structures that constitute according to this, respectively as the memory cell (Memory Cell) of storage data.
Above-mentioned technical process is that read-only memory is fabricated into the step before the sequencing, manufacturer can with this not the semifinished product warehouse of sequencing store away, treat that the client sends here after the order of specific program, can make photomask rapidly to carry out sequencing.See also Fig. 4 H and Fig. 4 I, it is respectively according to the A-A ' of Fig. 4 G, the cross-section structure of B-B ' line, limits and injects (code define﹠amp in order to describe these channel regions are encoded; Code implant), in as the metals-oxides-semiconductor structure of " opening " or " pass ", to produce the step of different starting voltages.As behind deposition one dielectric layer 57; cover the channel region that desire forms the semiconductor structure of " opening " with photoresist 59; 50d as Fig. 4 H; and to all the other channel regions that expose such as Fig. 4 H; the 50c of 4I injects ion; as N type impurity or p type impurity; and then make each corresponding cell stores logic zero data or logic one data; then according to traditional post-order process process; as make metallic contact (Contact); plain conductor (Metallurgy); isolated protective layer (Passivation); and packing, finish read-only memory structure of the present invention.
In addition, can obtain read-only memory structure shown in Fig. 4 G according to above-mentioned technical process, it comprises: a surface has the substrate 40 of insulating barrier 41; One trellis, it is an amorphous silicon layer, and forms along the parallel channel region 50a-50f of being separated by and connecting each bit line of Y direction along parallel bit line 43a, the 43b of being separated by of directions X by many, it is formed on this insulating barrier 41; One insulating barrier 44 fills up the grid gap 45 (Fig. 4 C) in this trellis; Silicon oxide layer or ONO layer (silicon oxide/silicon nitride/silicon oxide) 49 are formed at above-mentioned each laminar surface; Reach many and be formed at this insulating barrier 49 surfaces along parallel word line 53a, the 53b of being separated by of Y direction, wherein these many word line 53a, 53b are corresponding to these channel regions 50a-50f.
Wherein above-mentioned channel region has set ion doping concentration respectively, to produce different starting voltages.And in the described structure, this multiple bit lines distributes with equi-spaced apart each other.
See also Fig. 4 J, it is the equivalent structure schematic diagram according to Fig. 4 G, it comprises word line WL1～WL3 and bit line BL1, BL2, wherein below semiconductor line 43a, 43b constitute bit line BL1, BL2, conductor lines 53a up, 53b constitute word line WL1, WL2, according to this figure, can find out the transistor 55 that constitutes by channel region 50c, keep closing because of injecting ion, and the transistor 56 that constitutes by channel region 50d, then after applying a voltage to word line WL2, this channel region of conducting 50d, and make electric current flow to bit line BL2 from bit line BL1.
In sum, the present invention has following advantage:
(1) because the present invention forms insulating oxide with thermal oxidation (Thermal Oxide) step that flatening process replaces prior art, for example CMP technology or SOG technology, and used dielectric layer material such as the silica of this SOG is the surface that covers wafer with the kenel of solvent, therefore SOG rises and falls to height, and to fill out ability (gap fill) better than the dielectric layer with the chemical vapour deposition technique made for the ditch of outward appearance, and its less hole (voids) that causes.
(2) bit line of the present invention be not on silicon base implanted dopant form, so when element dwindles, do not have horizontal proliferation, adjacent leakage current, reach the phenomenon that breakdown voltage value can't improve.
As for the work of read-only memory structure of the present invention, it can see through the selection of word line and bit line, and sensing amplifier is stored in the interior numerical data of memory cell to the detecting of each memory cell current and read.
More than the narration and graphic example only for convenience of explanation, those skilled in the art is to be understood that and the invention is not restricted to this.In addition, the material that this specification is lifted, conduction property, numerical value, process conditions etc. are not used to limit the present invention yet.Though the present invention discloses as above with regard to a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make some and change and retouching, so protection scope of the present invention should be limited by accompanying Claim without departing from the spirit and scope of the present invention.
Claims (19)
1. read-only memory structure comprises:
One surface has the substrate of one first insulating layer of silicon oxide;
One makes the amorphous silicon semiconductor layer that grid is arranged, it is formed on this first insulating layer of silicon oxide, and be divided into along the parallel bit line of being separated by of a first direction, along one with the vertical second direction of this first direction the parallel channel region of being separated by and connecting each bit line, and the grid gap of a boundary between this bit line and channel region;
One second insulating layer of silicon oxide fills up these grid gaps;
One the 3rd insulating layer of silicon oxide is formed on above-mentioned each laminar surface;
One conductor layer is formed on the 3rd insulating layer of silicon oxide, and becomes many along the parallel lead of being separated by of this second direction through etching, and wherein the location overlap of these many leads is on these channel regions.
2. structure as claimed in claim 1, wherein, this semiconductor layer is one of amorphous silicon layer and polysilicon layer.
3. structure as claimed in claim 1, wherein, this conductor be polysilicon layer, layer of titanium metal, tungsten layer, and aluminium lamination one of them.
4. structure as claimed in claim 1, wherein, this lead is a word line.
5. structure as claimed in claim 1, wherein, above-mentioned insulating barrier is a silicon oxide layer.
6. structure as claimed in claim 1, wherein, these channel regions have different starting voltages respectively.
7. structure as claimed in claim 1, wherein, this multiple bit lines distributes with equi-spaced apart each other.
8. the manufacture method of a read-only memory comprises the following steps:
(a) in a substrate, form one first insulating layer of silicon oxide;
(b) on this first insulating layer of silicon oxide, form an amorphous silicon semiconductor layer;
(c) to this amorphous silicon semiconductor layer composition, through etching form a plurality of first directions part and one and its mutually perpendicular a plurality of second directions parts, and these two parts between the trellis that constitutes of grid gap;
(d) in these grid gaps, form one second insulating layer of silicon oxide;
(e) in the grid gap, fill up one second insulating layer of silicon oxide with SOG or cmp planarization metallization processes;
(f) this second direction partly is defined as channel region, and this first direction partly is defined as bit line;
(g) form one the 3rd insulating layer of silicon oxide at above-mentioned each laminar surface;
(h) form a conductor layer on the 3rd insulating layer of silicon oxide, and form many along the parallel word line of being separated by of this second direction through etching, wherein these many word lines are corresponding to these channel regions; And
(i) via these word lines to this channel region encode the definition and implantation step, finish the manufacturing of follow-up read-only memory.
9. method as claimed in claim 8, wherein, this step (b) is for forming semi-conductor layer on this first insulating barrier, and through the ion doping step to adjust concentration.
10. method as claimed in claim 8, wherein, this step (f) is that the zone between the adjacent two first directions part of this trellis forms a photoresist layer that covers, partly be channel region in order to limit this second direction, and this first direction partly is a bit line, subsequently at this bit line dopant ion reducing its resistance, and remove this photoresist.
11. method as claimed in claim 8, wherein, this step (i) is for forming one the 4th insulating barrier successively at above-mentioned each laminar surface earlier, one photoresist layer, and with lithography process to this photoresist layer composition, to form the window that exposes the 4th insulating barrier above the channel region that injects ion in desire, carry out ion doping subsequently, finishing coding via these windows, and remove this photoresist layer to these channel regions.
12. the manufacture method of a read-only memory comprises the following steps:
(a) form a dielectric base;
(b) on this dielectric base, form semi-conductor layer, and through the ion doping step to adjust concentration;
(c) with lithography process to this semiconductor layer composition, through etching form a plurality of first directions part and one and its mutually perpendicular a plurality of second directions parts, and these two parts between the trellis that constitutes of grid gap;
(d) in these grid gaps, fill up one first insulating barrier with flatening process;
(e) zone between the adjacent two first directions part of this trellis forms a photoresist layer that covers, in order to this second direction partly is defined as channel region, and this first direction partly is defined as bit line, subsequently at this bit line dopant ion reducing its resistance, and remove this photoresist layer;
(f) form one second insulating barrier at above-mentioned each laminar surface;
(g) form a conductor layer on this second insulating barrier, and form many along the parallel word line of being separated by of this second direction through etching, wherein these many word lines are corresponding to these channel regions; And
(h) via these word lines to this channel region encode the definition and implantation step, finish the manufacturing of follow-up read-only memory.
13. method as claimed in claim 12, wherein, this step (b) is that deposition forms an amorphous silicon layer on this dielectric base.
14. method as claimed in claim 12, wherein, the semiconductor layer of this step (b) is the P type.
15. method as claimed in claim 12, wherein, the semiconductor layer of this step (b) is the N type.
16. method as claimed in claim 12, wherein, in this step (h), this coding definition and implantation step are in order to improve the starting voltage of this channel region.
17. method as claimed in claim 12, wherein, in this step (h), this coding definition and implantation step are in order to reduce the starting voltage of this channel region.
18. method as claimed in claim 12, wherein, in this step (h), this coding implantation step injects p type impurity.
19. method as claimed in claim 12, wherein, in this step (h), this coding implantation step injects N type impurity.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97105499A CN1082723C (en) | 1997-06-06 | 1997-06-06 | Read only memory structure and manufacture thereof |
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| CN97105499A CN1082723C (en) | 1997-06-06 | 1997-06-06 | Read only memory structure and manufacture thereof |
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| CN1202013A CN1202013A (en) | 1998-12-16 |
| CN1082723C true CN1082723C (en) | 2002-04-10 |
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| CN97105499A Expired - Fee Related CN1082723C (en) | 1997-06-06 | 1997-06-06 | Read only memory structure and manufacture thereof |
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| CN102361030B (en) * | 2011-09-02 | 2013-12-04 | 长沙艾尔丰华电子科技有限公司 | One-time programmable memory cell array and manufacturing method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4597060A (en) * | 1985-05-01 | 1986-06-24 | Texas Instruments Incorporated | EPROM array and method for fabricating |
| US5523251A (en) * | 1994-10-05 | 1996-06-04 | United Microelectronics Corp. | Method for fabricating a self aligned mask ROM |
| US5539234A (en) * | 1993-10-25 | 1996-07-23 | United Microelectronics Corporation | Bottom gate mask ROM device |
| EP0727820A1 (en) * | 1995-02-17 | 1996-08-21 | Hitachi, Ltd. | Semiconductor memory device and method of manufacturing the same |
-
1997
- 1997-06-06 CN CN97105499A patent/CN1082723C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4597060A (en) * | 1985-05-01 | 1986-06-24 | Texas Instruments Incorporated | EPROM array and method for fabricating |
| US5539234A (en) * | 1993-10-25 | 1996-07-23 | United Microelectronics Corporation | Bottom gate mask ROM device |
| US5523251A (en) * | 1994-10-05 | 1996-06-04 | United Microelectronics Corp. | Method for fabricating a self aligned mask ROM |
| EP0727820A1 (en) * | 1995-02-17 | 1996-08-21 | Hitachi, Ltd. | Semiconductor memory device and method of manufacturing the same |
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| CN1202013A (en) | 1998-12-16 |
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