CN1084930C - Structure of read-only memory and its producing method - Google Patents
Structure of read-only memory and its producing method Download PDFInfo
- Publication number
- CN1084930C CN1084930C CN97112725A CN97112725A CN1084930C CN 1084930 C CN1084930 C CN 1084930C CN 97112725 A CN97112725 A CN 97112725A CN 97112725 A CN97112725 A CN 97112725A CN 1084930 C CN1084930 C CN 1084930C
- Authority
- CN
- China
- Prior art keywords
- layer
- insulating barrier
- conductor
- read
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The present invention relates to a read-only memory structure comprising a substrate of which the surface is provided with a first insulation layer, a conductor layer, a second insulation layer, a third insulation layer, a semi-conductor layer and channel regions, wherein the conductor layer formed on the first insulation layer is etched into a plurality of separated conductor lines which are parallel to a first direction; the second insulation layer is filled between the conductor lines; the third insulation is formed on the surface of each layer; the semiconductor layer in grid arrangement is formed on the third insulation layer and is divided into a plurality of separated position lines which are approximately vertical to a first direction and parallel to a second direction; the separated channel regions connected with the position lines are parallel to the first direction, wherein the positions of the channel regions are overlapped on the conductor lines.
Description
The present invention relates to a kind of read-only memory structure and manufacture method thereof, particularly relate to a kind of amorphous silicon read-only memory structure and manufacture method thereof.
Read-only memory has been widely used in mini computer, and in the digital device of a class such as microprocessor system, it can be used to store some system datas, for example resident program such as BIOS.Because the manufacturing process of read-only memory (being called for short ROM) is very complicated, and the processing of a lot of time-consuming steps of needs and material, therefore, the client normally earlier gives memory manufacturing works with routine data, by factory it is coded among the ROM again, to make finished product.
Most ROM element is except sequencing (programming) the data difference that the stage deposited in, remaining structure is all identical, therefore, read-only memory can be fabricated into the step before the sequencing earlier, and with this not the semifinished product warehouse of sequencing store away, treat that the client sends here after the order of specific program, can make photomask rapidly, to carry out sequencing, the client is given in shipment again, so above-mentioned back sequencing photomask formula read-only memory has become the industry customary way.
General read-only memory commonly used is to utilize channel transistor to be used as memory cell (memorycell), and in the sequencing stage, optionally implanted dopant is to the dedicated tunnel district, changes threshold voltage (threshold voltage) and reaches control store cell conduction (ON) or close the purpose of (OFF) with mat.The structure division of read-only memory wherein, polysilicon word line WL (Word Line) strides across bit line BL (BitLine), and the passage of memory cell then is formed at below that word line WL covered and the zone between the bit line BL.And whether read-only memory promptly injects with the ion of passage, comes stores binary data " 0 ", " 1 ".
Please refer to Fig. 1, Fig. 1 shows the part equivalent circuit diagram of the photomask read-only memory 10 of prior art, comprising some word line WL that arrange in the parallel array mode and the bit line BL that arranges in the parallel array mode.The data of after 10 sequencing of photomask read-only memory, being stored, be by selecting these memory cell that is positioned at word line WL and bit line BL intervening portion decisions, for example reaching the purpose of storage data by these different threshold voltages that memory cell had (threshold voltage) combinations on intervening portion.Wherein, has relative low threshold voltage by transistor 12 formation that will be positioned at bit line BL0 and word line WL0 intervening portion, and will be in logic the data storing of " 0 " or " ON " in this transistor 12, or form by the transistor 14 that this is positioned at word line WL0 and bit line BL2 intervening portion and to have relative high threshold voltage, and with data " 1 " or " OFF " is stored in this transistor 14.
And the mode of data read, be that pairing this bit line in memory cell position and the word line that will desire reading of data imposes a specific potential (potential), and whether the electric current of measuring this bit line change, and decides this transistor that constitutes memory cell whether low threshold voltage is arranged.For example, select one to have the transistorized position of low threshold voltage as 12, this transistorized grid (joining with word line) and drain electrode (joining with bit line) are applied a specific potential, make this transistor turns, then, can learn that the stored data of this memory cell are " 0 " or " ON " in logic according to the size of current on this bit line that records.In like manner, in this example, if this memory cell is made up of a transistor with high threshold voltage, transistor as shown in the reference numeral 14, then the specific potential that is applied on its grid can't make this transistor turns, so this storage data is in logic " 1 " or " OFF " as can be known.
Please refer to Fig. 2, Fig. 2 shows the part pattern of the photomask read-only memory of a prior art, these photomask read-only memorys are formed on the P type silicon base 20, and imbed bit line (buried bit lines) 22,26 and paratope line 24,28 with what N type impurity (N-typeImplantations) injected that parallel array arranges.This bit line 22,26 is connected to a power line V, these paratope line 24,28 ground connection, and these transistors are then as the memory cell of storage data.This photomask read-only memory also has word line WL0, WL1 etc.These word lines are haply perpendicular to these bit lines, and are transistorized gate regions.In these word lines and the formed transistor of bit line intervening portion, a part of transistor forms has the passage area 30 of low threshold voltage, and remaining field-effect transistor forms the passage area 32 with relative higher threshold voltage.
As for traditional read-only memory manufacturing, then as shown in Figure 3, it is presented at a kind of method of sequencing of the photomask read-only memory of the prior art among Fig. 1,2.At first, inject N type impurity on silicon base 15, for example, arsenic ion to form a plurality of buried bit lines that are equally spaced (buried bitlines) 11, then constitutes channel region between the buried bit line 11.Secondly, carry out oxidation operation, and utilize different oxidations rate, form the thin oxide layer 17b of thicker separator 17a in buried bit line 11 tops and channel region top.Then, deposit a polysilicon layer and constitute pattern, form word line 13, constitute channel transistor, finish the semi-finished product manufacturing of conventional photomask read-only memory across bit line through etching.Then carry out the operation of this photomask rom programization, form a mask layer 19, the channel region 15 that exposes the desire coding, p type impurity reinjects, boron ion for example, finish coding and inject (Code Implant) operation, and in the programmed process of this photomask read-only memory, then can decide different doped source according to different transistor characteristics.
Wherein in this photomask read-only memory, transistorized threshold voltage is decided by that just its channel region injects the degree of doped source, for example, can inject suitable doped source in these transistor channels districts that set in logic " 1 " or " OFF " for; And these will be set in the transistor channels district of in logic " 0 " or " ON ", then not inject any doped source.
Yet above-mentioned photomask read-only memory can produce following point in programmed process:
(1) many buried bit lines that are equally spaced form with implanted dopant on silicon base (Implant Dose), when element dwindles, if with too high incorporation, easily cause horizontal proliferation (LateralDiffusion), adjacent leakage current (Junction Leakage), reach the phenomenon that breakdown voltage value can't improve, so can't effectively improve component density.
(2) planarization (claims complanation again, planarization) be one of very important step on the present semi-conductive technology, therefore how to reduce wafer surface and shorten the influence that is caused because of interelement distance, and with the planarization in addition that rises and falls of the height on surface, be the task of top priority that must solve in present very lagre scale integrated circuit (VLSIC) (VLSI) technology, yet in existing technical process, owing to form insulating oxide with thermal oxidation (Thermal Oxide) step, therefore form the technology planarization fully of memory cell.
Purpose of the present invention just is to address the above problem, and a kind of read-only memory structure and manufacture method thereof that helps improving density and planarization is provided.
To achieve these goals, the invention provides a kind of read-only memory structure, comprising:
One dielectric base layer;
One conductor layer is formed on this dielectric base layer, and becomes many along the parallel conductor lines of being separated by of first direction through etching, and this conductor lines is as word line;
One first insulating barrier fills up between these conductor lines;
One second insulating barrier is formed on above-mentioned each laminar surface; And
One makes the semiconductor layer that grid is arranged, it is formed on this second insulating barrier, and be divided into along the parallel multiple bit lines of being separated by of second direction of vertical this first direction, and along the parallel channel region of being separated by and connecting each bit line of this first direction, wherein the location overlap of these channel regions is on these conductor lines, and wherein each bit line is through overdoping, thereby constitutes a plurality of MOS structures.
In above-mentioned memory construction, this semiconductor layer can be amorphous silicon layer or polysilicon layer, and this conductor layer can be polysilicon, Titanium, tungsten or aluminum metal layer, and this multiple bit lines is equidistantly spaced apart with one each other.
In addition, after read-only memory being carried out the sequencing coding, these channel regions have set ion doping concentration respectively, to produce different threshold voltages.
And the manufacture method of a kind of read-only memory of the present invention comprises the following steps:
(a) form a dielectric base;
(b) on this dielectric base, form a conductor layer, and form many along parallel word line of being separated by of a first direction and groove therebetween through etching;
(c) on this groove, form one first insulating barrier;
(d) form one second insulating barrier at above-mentioned each laminar surface;
(e) on this second insulating barrier, form semi-conductor layer, and through the ion doping step to adjust its concentration; And
(f) to this semiconductor layer composition, form a plurality of first directions part and one and the trellis that partly constitutes of its mutually perpendicular a plurality of second directions through etching, wherein this first direction partly is positioned at top that should many word lines;
(g) in the grid gap of this trellis, fill up one the 3rd insulating barrier;
(h) this first direction partly is defined as channel region, and this second direction partly is defined as bit line; And
(i) to this channel region encode the definition and implantation step, finish the manufacturing of follow-up read-only memory.
Above-mentioned steps (a) can directly replace with a dielectric base.
Below in conjunction with accompanying drawing in detail the preferred embodiments of the present invention are described in detail.In the accompanying drawing:
Fig. 1 shows the part equivalent circuit diagram of the photomask read-only memory of prior art;
Fig. 2 shows the part pattern of the photomask read-only memory of a prior art;
Fig. 3 is presented at a kind of method of sequencing of the photomask read-only memory of the prior art among Fig. 1,2; And
Fig. 4 A to 4K shows the manufacturing process of the preferred embodiment of read-only memory of the present invention.
According to a preferred embodiment of the invention, a kind of making step of read-only memory structure is as follows.
See also Fig. 4 A, 4B at first selects a dielectric base layer, or forms an insulating barrier earlier in a substrate; Secondly, on this insulating barrier, form a conductor layer.For example select an oxide layer 41 earlier, or be chosen on the P type silicon base 40 oxide layer 41 of deposition, on this oxide layer 41, form a conductor layer 43 then, one preferred embodiment one of is become to constitute by groups such as polysilicon, tungsten, titanium, aluminium for this conductor layer, its can physics (PVD) or chemical vapor deposition method (CVD) deposit.
See also Fig. 4 C, this step is for forming many along the parallel conductor lines of being separated by of a direction such as word line and groove therebetween on above-mentioned insulating barrier.For example these conductor layer 43 compositions are formed many along parallel word line 43a, 43b of being separated by of direction Y and groove 45 therebetween through etching, as 45a, 45b, 45c with the lithography corrosion process step.
See also Fig. 4 D, this step is for to fill up an insulating barrier, as flatening process on this groove.One preferred embodiment is at above-mentioned each laminar surface with " revolve and cover glass " (SOG) " process deposits one oxide layer is as 44; fill up this groove 45 (Fig. 4 C) through returning after carving; to reach the effect of planarization, in addition, this step also can chemical mechanical milling method (CMP) replacement.
See also Fig. 4 E, 4F, this step is to form insulating barrier 47 at above-mentioned each laminar surface, and forms a conductor layer 49 on this insulating barrier, and it forms a trellis through etching.
For example Fig. 4 E forms oxide layer 47 to above-mentioned each laminar surface earlier, deposition forms semi-conductor layer on this oxide layer 47 then, as intrinsic amorphous silicon layer 49 (Intrinsic Amorphous SiliconLayer), and through the ion doping step to adjust concentration, wherein, one embodiment of this step is under about 350 ℃～575 ℃, utilizes plasma reinforced chemical vapour deposition method (PECVD) with SiH
4Decomposing gas is deposited as amorphous silicon layer, then adjusts its concentration with ion doping step such as boron ion.
See also Fig. 4 F, it limits the pattern of trellis with lithography corrosion process, through this amorphous silicon layer 49 of etching, and form many parallel directions X semiconductor layer 49a, 49b of being separated by, parallel Y direction semiconductor layer 50a-50f of being separated by with many, wherein this Y direction semiconductor layer such as 50a-50f connect this directions X semiconductor layer such as 49a, 49b, and to should many word line 43a, 43b and be positioned at insulating barrier 47 surfaces.
See also Fig. 4 G, 4H, Fig. 4 G for example, this step is for to fill up an insulating barrier 48 with flatening process in the grid gap of this trellis.Secondly as Fig. 4 H, this step is used for to multiple bit lines and channel region composition, and this bit line is carried out the ion injecting program.For example be coated with one deck photoresist layer earlier, behind exposure imaging, zone between this adjacent two bit line 49a, 49b forms strip photoresist layer 51a, 51b, a 51c who covers, in order to these many parallel Y direction semiconductor layer 50a-50f compositions of being separated by are defined as channel region, and these many directions X semiconductor layer 49a, 49b of being separated by parallel to each other are defined as the bit line that connects each channel region, subsequently at this bit line 49a, 49b dopant ion to reduce its resistance, as with the first type impurity, the arsenic ion of N type (As) injects to form a plurality of N spaced apart
+Bit line is removed this layer photoresist with appropriate solvent afterwards, and a plurality of MOS (Metal-oxide-semicondutor) structure that constitutes according to this, respectively as the memory cell (MemoryCell) of storing data.
Above-mentioned technical process is that read-only memory is fabricated into the step before the sequencing, manufacturer can with this not the semifinished product warehouse of sequencing store away and treat that the client sends here after the order of specific program, can make photomask rapidly to carry out sequencing.See also Fig. 4 I and Fig. 4 J, it is respectively according to the A-A ' of Fig. 4 H, the cross-section structure of B-B ' line, in order to describe the encode definition and inject (codedefine ﹠amp of these channel regions; Code implant), in as the MOS structure of " opening " or " pass ", to produce the step of different threshold voltages.Form channel region of semiconductor structure of " opening " such as the 50d of Fig. 4 I as cover desire with photoresist 54; and the 50c of all the other channel regions that expose such as Fig. 4 I, 4J injected ion; and then make each corresponding cell stores logic zero data or logic one data; then according to traditional subsequent technique; as make Metal Contact (Contact), plain conductor (Metallurgy); passivation protection layer (Passivation) and packing are finished read-only memory structure of the present invention.
The above-mentioned technical process of foundation can obtain the read-only memory structure as Fig. 4 G in addition, and it comprises: a surface has the substrate 40 of insulating barrier 41; Many along the parallel conductor lines of being separated by of direction Y such as word line 43a, 43b and groove 45 (Fig. 4 C) therebetween, and it is formed on this insulating barrier 41; One insulating barrier 44 fills up this groove 45; One silica layer or ONO layer (silicon oxide/silicon nitride/silicon oxide) 47 are formed at above-mentioned each laminar surface; And many parallel bit line 49a, the 49b of being separated by of the direction X along this direction of approximate vertical Y, it be an amorphous silicon layer, reaches the parallel channel region 50a-50f of being separated by and connecting each bit line of Y in the direction, wherein these channel regions are to should many word line 43a, 43b.
Wherein above-mentioned channel region has set ion doping concentration respectively, to produce different threshold voltages.And in the described structure, this multiple bit lines distributes with equi-spaced apart each other.
See also Fig. 4 K, it is the equivalent structure schematic diagram according to Fig. 4 G, it comprises word line WL1～WL3 and bit line BL1, BL2, wherein below conductor lines 43a, 43b constitute word line WL1, WL2, semiconductor line 49a, 49b up constitutes bit line BL1, BL2, according to this figure, can find out the transistor 55 that constitutes by channel region 50c, keep closing because of injecting ion, the transistor 56 that is made of channel region 50d is then after applying a voltage to word line WL2, this channel region of conducting 50d, and make electric current flow to bit line BL2 from bit line BL1.
In sum, the present invention has following advantage:
(1) because the present invention forms insulating oxide with thermal oxidation (Thermal Oxide) step that flatening process replaces prior art, the planarization of CMP technology or SOG for example, and used dielectric layer material such as the silica of this SOG is the surface that covers wafer with the kenel of solvent, therefore SOG rises and falls to height, and to fill out ability (gap fill) better than the dielectric layer with the chemical vapour deposition technique made for the ditch of outward appearance, and its less hole (voids) that causes.
(2) bit line of the present invention be not on silicon base implanted dopant form, so when element dwindles, do not have horizontal proliferation, adjacent leakage current, reach the phenomenon that breakdown voltage value can't improve.
As for the work of read-only memory structure of the present invention, it can see through the selection of word line and bit line, and sensing amplifier is stored in the interior numerical data of memory cell to the detecting of each memory cell current and read.
More than the narration and graphic example only for convenience of explanation, those skilled in the art is to be understood that and the invention is not restricted to this.In addition, the material that this specification is lifted, conduction property, numerical value, process conditions etc. are not used to limit the present invention yet.Though the present invention discloses as above with regard to a preferred embodiment; but it is not in order to limit the present invention; those skilled in the art can make some and change and retouching, so protection scope of the present invention should be limited by accompanying Claim without departing from the spirit and scope of the present invention.
Claims (24)
1. read-only memory structure comprises:
One dielectric base layer;
One conductor layer is formed on this dielectric base layer, and becomes many along the parallel conductor lines of being separated by of first direction through etching, and this conductor lines is as word line;
One first insulating barrier fills up between these conductor lines;
One second insulating barrier is formed on above-mentioned each laminar surface; And
One makes the semiconductor layer that grid is arranged, it is formed on this second insulating barrier, and be divided into along the parallel multiple bit lines of being separated by of second direction of vertical this first direction, and along the parallel channel region of being separated by and connecting each bit line of this first direction, wherein the location overlap of these channel regions is on these conductor lines, and wherein each bit line is through overdoping, thereby constitutes a plurality of MOS structures.
2. structure as claimed in claim 1, wherein, this semiconductor layer is one of group of amorphous silicon layer and polysilicon layer.
3. structure as claimed in claim 1, wherein, this conductor layer is constituted by polysilicon, Titanium, tungsten or the arbitrary of aluminum metal layer group.
4. as the described structure of one of claim 1-3, wherein, described dielectric base layer comprises a substrate and is formed on a insulating barrier on the substrate.
5. structure as claimed in claim 4, wherein, above-mentioned substrate is a silicon base, above-mentioned insulating barrier is a silicon oxide layer.
6. structure as claimed in claim 1, wherein these channel regions have different threshold voltages respectively.
7. structure as claimed in claim 1, wherein, this multiple bit lines is set spaced apart with one each other.
8. structure as claimed in claim 7, wherein, this multiple bit lines distributes with equi-spaced apart each other.
9. structure as claimed in claim 1, wherein, the semiconductor layer of doing the grid arrangement also comprises the insulating barrier that fills up grid.
10. the manufacture method of a read-only memory comprises the following steps:
(a) form a dielectric base;
(b) on this dielectric base, form a conductor layer, and form many along parallel word line of being separated by of a first direction and groove therebetween through etching;
(c) on this groove, form one first insulating barrier;
(d) form one second insulating barrier at above-mentioned each laminar surface;
(e) on this second insulating barrier, form semi-conductor layer, and through the ion doping step to adjust its concentration; And
(f) to this semiconductor layer composition, form a plurality of first directions part and one and the trellis that partly constitutes of its mutually perpendicular a plurality of second directions through etching, wherein this first direction partly is positioned at top that should many word lines;
(g) in the grid gap of this trellis, fill up one the 3rd insulating barrier;
(h) this first direction partly is defined as channel region, and this second direction partly is defined as bit line; And
(i) to this channel region encode the definition and implantation step, finish the manufacturing of follow-up read-only memory.
11. method as claimed in claim 10, wherein, this step (c) is for to fill up first insulating barrier with flatening process on this groove.
12. method as claimed in claim 10, wherein, this step (e) is for forming semiconductor layer on this second insulating barrier, and through the ion doping step to adjust concentration.
13. method as claimed in claim 10, wherein, this step (g) is for to fill up the 3rd insulating barrier with the SOG flatening process in the grid gap of this trellis.
14. method as claimed in claim 10, wherein, this step (g) is for to fill up the 3rd insulating barrier with the cmp planarization metallization processes in the grid gap of this trellis.
15. method as claimed in claim 10, wherein, this step (h) is that the zone between the adjacent two second directions part of this trellis forms a photoresist layer that covers, in order to the partially patterned channel region that is defined as of this first direction, and this second direction partly is defined as bit line, subsequently at this bit line dopant ion reducing its resistance, and remove this photoresist layer.
16. method as claimed in claim 10, wherein, this step (i) is for forming a photoresist layer at above-mentioned each laminar surface earlier, and with lithography corrosion process to this photoresist layer composition, to form set window above the channel region that injects ion in desire, carry out ion doping subsequently finishing coding via these windows, and remove this photoresist layer these channel regions.
17. method as claimed in claim 10, wherein, the dielectric base that forms in step (a) comprises a silicon base and the insulating barrier that is positioned on the silicon base.
18. method as claimed in claim 17, wherein, this step (e) is that deposition forms an amorphous silicon layer on this second insulating barrier.
19. method as claimed in claim 17, wherein, the semiconductor layer of this step (e) is the P type.
20. method as claimed in claim 17, wherein, the semiconductor layer of this step (e) is the N type.
21. method as claimed in claim 17, wherein, in this step (i), this coding definition and implantation step are in order to promote the threshold voltage of this channel region.
22. method as claimed in claim 17, wherein, in this step (i), this coding definition and implantation step are in order to reduce the threshold voltage of this channel region.
23. method as claimed in claim 17, wherein, in this step (i), this coding implantation step injects p type impurity.
24. method as claimed in claim 17, wherein, in this step (i), it is assorted that this coding implantation step injects N type matter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97112725A CN1084930C (en) | 1997-06-16 | 1997-06-16 | Structure of read-only memory and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97112725A CN1084930C (en) | 1997-06-16 | 1997-06-16 | Structure of read-only memory and its producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1202738A CN1202738A (en) | 1998-12-23 |
| CN1084930C true CN1084930C (en) | 2002-05-15 |
Family
ID=5172458
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97112725A Expired - Fee Related CN1084930C (en) | 1997-06-16 | 1997-06-16 | Structure of read-only memory and its producing method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1084930C (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4356024A (en) * | 1980-02-20 | 1982-10-26 | Bayer Aktiengesellschaft | Process for the preparation of 1-amino-1,3,5-triazine-2,4(1H, 3H)-dione compounds |
-
1997
- 1997-06-16 CN CN97112725A patent/CN1084930C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4356024A (en) * | 1980-02-20 | 1982-10-26 | Bayer Aktiengesellschaft | Process for the preparation of 1-amino-1,3,5-triazine-2,4(1H, 3H)-dione compounds |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1202738A (en) | 1998-12-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5274588A (en) | Split-gate cell for an EEPROM | |
| US7045849B2 (en) | Use of voids between elements in semiconductor structures for isolation | |
| US7215577B2 (en) | Flash memory cell and methods for programming and erasing | |
| EP0550404B1 (en) | A method of making a capacitive coupling device, especially in an EEPROM | |
| US7696557B2 (en) | Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation | |
| US8114737B2 (en) | Methods of forming memory cells on pillars and memories with memory cells on pillars | |
| CN100343955C (en) | Method for making integrated circuit using memory wordline hard mask extension | |
| US5168335A (en) | Electrically programmable, electrically erasable memory array cell with field plate | |
| CN1315180C (en) | Memory manufacturing process with bitline isolation | |
| US20230328975A1 (en) | Integrated Assemblies and Methods of Forming Integrated Assemblies | |
| CN113711355A (en) | Assembly including a wordline having a first metal-containing material at least partially surrounding a second metal-containing material and having a crystallinity different from a crystallinity of the second metal-containing material | |
| EP3994728A1 (en) | Assemblies having conductive structures with three or more different materials | |
| US20220246536A1 (en) | Integrated Assemblies and Methods of Forming Integrated Assemblies | |
| CN1084930C (en) | Structure of read-only memory and its producing method | |
| CN1082723C (en) | Read only memory structure and manufacture thereof | |
| US7888707B2 (en) | Gated diode nonvolatile memory process | |
| US11728263B2 (en) | Integrated assemblies having conductive-shield-structures between linear-conductive-structures | |
| US7157335B1 (en) | Using thin undoped TEOS with BPTEOS ILD or BPTEOS ILD alone to improve charge loss and contact resistance in multi bit memory devices | |
| WO2000041236A1 (en) | Integrated circuit memory cell upon a dielectric base |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |