FR2580421A1 - ELECTRICALLY PROGRAMMABLE DEAD MEMORY - Google Patents

Abstract

IN IT, FRAUD IS AVOIDED BY MANUFACTURING, INTERNALLY IN THE MEMORY, THE DIFFERENT POTENTIALS THAT IT USES TO CHECK THE CHOSEN MEMORY POINTS. VERIFICATION OF THE WRITING OF INFORMATION IN A POINT IS OBTAINED BY SUBJECTING THIS POINT TO A CALIBRATED SELECTION VOLTAGE, TO WHICH AN EXTERNAL OPERATOR CANNOT HAVE ACCESS. THIS CALIBRATED VOLTAGE IS PROVIDED BY A GENERATOR-MULTIPLIER 14. THE latter DEBITS INTO ONE OR MORE CALIBRATORS 18 TO MANUFACTURE ALL THE USEFUL VOLTAGES. READ AND WRITE ORDERS ARE THEN GIVEN TO A SWITCHING CIRCUIT 47 WHICH CAUSES THE CORRESPONDING APPLICATION OF THESE CALIBRATED VOLTAGES. AN EXTERNAL OPERATOR CANNOT ENTER THE MEMORY OF LEVEL FALSIFIED SIGNALS TO CHANGE THE MEANING OF THE CONTENT OF THE RECORDED INFORMATION.

Description

Z580421

I

  ELECTRICALLY PROGRAMMABLE DEAD MEMORY

  The subject of the present invention is a read only memory

  electrically grammable, for example EPROM or EEPROM. These memories have the advantage that their programming can be done by the user. Furthermore, in some cases, they can even be erased and then rewritten a certain number of times if the need arises. The information storage element is a

  floating gate transistor. This transistor can have two states.

  In a first state, no charge is trapped on the floating grid. A conduction channel can be installed between source and drain of this transistor. This can therefore lead; it behaves like a closed switch. In a second state, electrons were trapped on the floating grid. They prevent the creation of a conduction channel in the substrate between source and drain. The

  transistor is blocked and behaves like an open switch.

  The advantage of this type of storage element lies in the non-volatility of the information recorded. The electrical charges trapped in the floating grid only leak slowly. The pressure drop in the floating grid determines the retention time of a memory point. At the end of this time, the stored information is no longer readable. This retention time is generally of the order of 5 to years, it depends on the amplitude and the duration of the voltage applied during programming. Typical values of

  programming are 21 volts and 50 milliseconds.

  The on or off state of the transistor is measured by sending a selection pulse on its control gate. In the on state, no load is trapped on the floating gate, and the applied selection voltage puts the transistor in saturation. In practical terms, the transistor is connected by a first main electrode to a bit line voltage biased by a generator; by its other main electrode it is connected to ground. The bit line is also connected to a current sensor. This sensor measures the current delivered to the line by the generator. When the transistor turns on, it short-circuits the generator and the sensor detects a drop in current. This current drop is subsequently used as representative of the information corresponding to the programming state of the solicity transistor. In a second case, when the memory point is programmed, charges are trapped on the floating gate of the transistor. The selection voltage applied to the control gate is in the opposite direction to the potential barrier created, in the conduction channel, by the

  charges stored in the floating grid. But then it is insufficient

  fisante to modify the conduction of this channel: the transistor remains blocked. Consequently, the sensor at the end of the bit line does not perceive a variation in current. It thus detects, at the time of selection of the memory point considered, an inverse state of the first

case.

  One of the most welcoming areas of electrically programmable read-only memory technology is that of memory cards. A memory card is a card, for example in the format of a credit card of the banking system: an electronic integrated circuit is embedded in this card, and electrical connection terminals are accessible on the surface so that

  operations can be carried out with the card in a terminal.

  The basic problem with smart cards is that of fraud. We seek to prevent holders from falsifying the information contained in the card memories. A first risk to avoid is that of the introduction, in poor conditions, of critical information in the memory. Also in a first phase, this information is introduced via series of electrical pulses applied to the terminals of this memory. To ensure that the information has been entered correctly, the content of the memory is then checked by applying

  to access terminals for electrical verification pulses.

  However, we do not know how to check the effective retention power of information stored in memory points. Fraudsters are in fact suspected of tampering with the access points, for example by covering them with a tiny layer of graphite which constitutes resistance. In this way the programming of the information in the memory is not done at a level sufficient for the retention of the information to correspond to a desired duration. One might think that this fraud can be detected by sending, during verification, adequate electrical pulses to the verification access terminals. But fraudsters are also suspected of intending to also traffic the terminals

  verification access (presumably the same way).

  In other words, it is believed that a skilled fraudster could modify the conditions for programming the memory, even if this programming is carried out by the organization issuing the memory cards in question. The verification would then prove just as

  illusory since practiced under the same conditions.

  The present invention provides an effective solution to this problem: the potentials of the pulses used in verification are not in the invention potentials applied externally to the memory, but rather potentials produced internally by the latter. Setting the level of potential useful for programming

  irretrievably determines the retention period of information

  mations it contains. The intrinsic fixing of the potential level used by the verification pulses makes it possible to verify

  the reality of the information stored in the memory.

  This also means that, in the invention, if one programs and if one verifies the programmed information, one does it well or one does not do it at all. In the criticized state of the art, information could be programmed, then badly verified, to let believe, for a while, in a facade integrity of the stored information. After a certain time, the information became illegible: in fact, some became zeros. This

  significantly modified the stored information, especially if it

  these were deemed to represent a bank account balance.

  The subject of the invention is a programmable read-only memory.

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  electrically of the memory point type with floating gate transistor, and matrix accessible by rows and columns, comprising means for applying to these rows and

  these columns of the representative potentials of information to be recorded

  register in the reading control points or representative of the recorded information, characterized in that it comprises integrated means for applying to these rows and these columns

  verification potentials whose levels are fixed intrinsically

sequencing.

  The invention will be better understood on reading the description

  which follows and the examination of the figures which accompany it. In these figures, the same references designate the same elements. They are not

  given for information only and in no way limit the invention.

  They represent: FIGS. 1a and 1b an electrical operating diagram of a memory point with floating gate transistor;

  - Figure 2, a memory according to the invention.

  FIG. 1a represents the diagram of the operating characteristic of a floating gate transistor. This is also seen in Figure lb. On the ordinate of the diagram appears the current passing through the transistor 1. On the abscissa we carry the voltage applied between the reading gate 2 and a main terminal 3 of the transistor. Figure la has two curves. A first curve indicates that a current begins to cross from a

  voltage VTo, and a second curve indicates that a current

  begins to cross from a voltage VTi. The first corres-

  pond to a floating gate transistor not programmed (in fact programmed to one): no load is trapped on the floating gate 4. The potential barrier of this transistor is equal to VTO. When a voltage pulse (marked with dashes) whose value is VT is applied to this transistor 2, its transistor becomes conducting: it short-circuits a bit line 5 to ground. By cons - the right curve corresponds to a transistor having charges trapped on its floating gate, so that its potential barrier is translated from VTO to VTi. It is programmed to zero. Also receiving a value selection pulse

  VT, this transistor continues to be blocked: no current is short-

  flow from bit line 5 to ground. In the intermediate position between these two curves, two other curves are shown in dotted lines corresponding to transistors programmed at zero but whose floating gate comprises less and less trapped charges. The trapped charges are however still numerous enough for the potential barrier of these transistors to be higher than the selection voltage VT which is used for the normal reading of the cells. If these transistors are subjected to higher selection voltages, for example equal to VTi, they allow the currents Il and 12 to pass through respectively, showing, by

  the importance of these currents, their lack of retention capacity.

  They are correctly programmed (for a voltage VT) but their retention capacity is poor. The suspected fraud consists precisely in modifying the programming voltages so that the number of trapped charges is just insufficient. It also consists in modifying the verification voltage VT (by reducing it notably TI for example) so that it does not reveal currents such as Il or 12 which provide information on the lack of retention capacity. Spent a while, and once the layers

  superimposed graphite would have been removed, we would read all natu-

  really a one where previously we would have pretended to register a

zero.

  To remedy these fraud attempts, in the invention, it was simply decided to produce the verification voltages VT 'inside the memory. It is also possible to decide to produce there the reading voltages VT and programming voltages Vpp. FIG. 2 shows an electrically programmable memory 6. It is of the memory point type 7 with transistor I with floating gate 4. The transistors 1 have two main electrodes 3 and 8 respectively and a control gate 2. A first main electrode can be connected to ground while the other is connected to a line 5 called bit line. The control gate 2 is connected to another connection 9 called the word line. The bit lines and word lines are arranged in lines and columns to determine a matrix including the memory points. This memory comprises means, essentially a line decoder 10 and a column decoder 11,

  to apply potentials to the rows and columns

  sensitive to information to be recorded in points or

  command sent to read the information recorded in the points. For example, for reading the memory point 7, a current produced by the corresponding output 12 of the decoder 10 is passed through the bit line 5. By means of the column decoder 11, a control pulse is sent to the word line 9. The transistor 1 becomes conducting or remains blocked depending on whether the charges have not or have previously been trapped on its floating gate 4. A current sensor 13 connected moreover to one end of the bit line 5 detects the variation, or the absence of variation, of current. It deduces from this that the memory point was programmed at one, or

to zero respectively.

  An important characteristic of the invention comes from the fact that the potential applied to the gate 2 is not produced by the decoder 11, but is produced intrinsically by the memory itself. To this end, the latter may have an oscillating circuit, one output of which

  is connected to a rectifier. But in a preferred way it comprises

  will be an integrated high voltage multiplier generator 14 of the type

  Schenkel. These Schenkel generators are close in their function-

  ideal voltage multipliers. They include arrangements in diode and capacitance cells whose terminals are switched by clock pulses VH and V. They are supplied by the general supply Vcc of the memory. The continuous potential thus produced can be applied, according to the orders

  of selection developed by the decoder 1, on the control grid 2.

  To avoid any accidental or ill-intentioned fluctuations in the potential available at the output 17 of the generator 14, this potential can be calibrated in a calibrator 18. In this way the output

7,258,042 1

  19 of the calibrator 18 can produce constant and calibrated voltages whatever the supply conditions at VCC, of the generator 14. Any fraud attempts consisting moreover in acting on the general supply of the memory are thus also countered. It is possible to produce all useful potentials in this way: the potential Vpp useful for programming, especially the potential VTI useful for checking programming, or

  even the potential VT useful for reading information recorded

  registered in points. In a preferred embodiment the programming potential is provided externally. It is not annoying since all attempts at fraud on this potential can be

  easily identified using untouchable verification potential

  chable. In practical terms, the production of the Vpp potential could be obtained by connecting another calibrator in parallel with the calibrator 18: its input would be connected to the connection 17 its output

would deliver the Vpp potential.

  In calibrator 18, the voltage produced is limited. In a preferred embodiment, this calibrator comprises a number of transistors, in example three, of the same technology (FAMOS) as the transistor used for storing information in each memory point. Here these are the transistors 41 to 43. These transistors 41 to 43 only have the particularity that their floating gate is short-circuited at their control gate. The control gates of each of these transistors are connected to their drain. Each therefore constitutes a diode and causes a fall in calibrated VTO potential. This cascade of transistor 41 to 43 is supplied by a depleted transistor 44, polarized at the limit of blocking with its gate connected to the source electrode. An additional transistor 45, using the same technology as the transistors 1 and whose floating gate is also short-circuited at the control gate, receives on its gate the midpoint 46 of the circuit comprising the transistor 44 and the cascade of the transistors 41 to 43 The potential imposed on the gate of transistor 45 is therefore calibrated. On a first main electrode

8 2580421

  this transistor 45 receives the rectified signal from the general

  rator 14. It therefore delivers on its second main electrode a calibrated voltage signal VTl. Indeed, the voltage at its output is equal to the voltage applied to its gate minus the fall in characteristic potential between source and gate. The transistor 44 being depleted, its conduction threshold is zero. An unplanned transistor whose gate would be brought to the source potential would remain blocked. The transistors depleted in FIG. 2 include a

  mark in the shape of a cross in their design.

  We saw above that memory points could be subjected to three types of situation: writing, reading, and checking. In the invention and although this does not constitute an obligation, it has been agreed to differentiate these situations by two different orders: a first order Ver (as verification) and a second order RW (as read-write for read-write). In the chosen convention, for a memory write operation Ver will be worth one and RW will be worth zero; for reading Ver will be worth one and RW

  as well; and for verification Ver will be worth zero and RW will be worth one.

  The order Ver as well as the voltages Vpp or VT and VTi are introduced

  in a switch 47. This switch has two transa

  sistors depleted 48 and 49 in cascade. A first main electrode of transistor 48 is connected to the voltage source VT1 (output 19 of calibrator 18), its second main electrode is connected at a midpoint 50 to the first main electrode of transistor 49. The second main electrode of 49 is connected to the

  voltage source Vpp. The gate of transistor 49 receives the command Ver.

  The gate of transistor 48 receives this command Ver after it has passed through an inverter 51. A connection 71 connected to midpoint 50 is connected by depleted transistors such as 52 to each of the word lines 9. The depleted transistor 52 of which the grid is connected to

  one of its main terminals is equivalent to a resistor.

  The addresses of the memory points to be selected pass through

  an address bus 53 and are respectively translated by the deco-

  deurs 10 and 11. For the chosen line the decoder 10 produces a supply voltage. For the identified column, a selected output 58 of the decoder 11 produces a zero state. The non-selected outputs are brought to an electrical state one at the output of the decoder 11. Opposite each output of the decoder 1 is a cascade arrangement of two transistors 54 and 55 between the supply voltage Vcc and the ground. The transistor 54 is a depleted transistor. The output 58 of the decoder controlled the gate of the transistor 55. The midpoint 59 of the two transistors is connected to the gate of the transistor 54 as well as to a main electrode of a depleted transistor 56. The other electrode

  main of the depleted transistor 56 is connected to the word line 9.

  The control gate of transistor 56 receives the read order.

write RW via connection 57.

  For each of the three situations we will now study what happens to the memory point depending on whether the address of the chosen memory point is correct or not. In a first operation we want to write the memory point 7 (Ver is one and RW is zero). The considered output 58 of the decoder It is then brought to zero. The transistor turns off and it follows that the midpoint 59 of the transistors 54 is brought to Vcc. As RW is zero, transistor 56 is blocked. This transistor 56 is blocked because, as will be seen below, the voltage applied to its other terminal is greater than its blocking threshold voltage. Consequently the tension on the line of

  word 9 will be imposed by the voltage available on connection 71.

  Indeed the transistor 52, which behaves like a resistor, does not here cause a voltage drop since the current which crosses it can only go in the grid 2 of the transistor 1: that is to say that it is very low. The Ver order has a short-circuit on the transistor 49 and opens the transistor 48. Consequently, the voltage Vpp is applied to the midpoint 50 connected to the connection 71. It follows that the voltage V is brought to the gate 2 of the transistor, pp is precisely what we are looking for. At this instant, an adequate current pulse is sent to the output 12 of the decoder 10, and the transistor I thus selected is programmed (to zero or to one according to

the momentum available in 12).

  d2580421 For transistors 1 which have not been selected: that is to say those for which the output connection of the decoder It issues a state when their transistor 55 is short-circuited, their midpoint 59 between transistor 54 and 55 is therefore brought to zero. As the order RW available on connection 57 is equal to zero, but since the transistors 56 are depleted, they are nevertheless conducting. As a result, the

  voltage Vpp available on connection 71 delivered in resistors

  tances constituted by the depleted transistors 52. These are

  now connected to ground by their second main electrode

  cipal: the other word lines are therefore not brought to

Vpp programming potential.

  For the read operation, it is agreed that the orders Ver and RW are worth one. As it is a simple read operation, it is agreed that the terminals which will have to read the contents of these

  ROMs will have a connection as they apply

  will be a reading voltage (VT) instead of the previous application of the programming voltage Vpp. As the order Ver is identical to the previous case, it is therefore this new reading voltage (VT) which is applied to connection 71. For output 58

  corresponding to the memory point 7 chosen, the electrical state is zero.

  The potential Vcc is therefore brought to the midpoint 59. The depleted transistor 56 then receives on its gate an order RW at 'Petat one (ie V), on a first main electrode the voltage Vcc in cc coming from the midpoint 59, and on the other main electrode a voltage VT coming from the connection 71 by the depleted transistor 52. If VT is different from Vcc, the surface of the transistor 56 is calculated so that it has a resistance such that the voltage VT is applied to the gate 2 of the transistor 1. The role of the transistors 56 is to avoid the establishment of a path between a very high write, read or verification potential and the normal supply of the memory Vcc (often of the order of 5 volts). It is for this reason that here they are at the limit of conduction. This read voltage makes it possible to read the state of the charges trapped in the floating gate 4. A current generator then delivers in the bit line 5. The sensor 13 detects, or does not detect, a drop in current linked to the setting in conduction of the transistor 1. The information which it raises is then sent on a data bus 60. For the word lines not selected by the decoder 11, the midpoints 59 of the transistors 54 and 55 are brought to the potential of the mass. The transistors 56 conduct: they receive RW at one on their grid. Unselected word lines are brought to ground: the transistors of the memory points assigned to them do not

are not excited.

  The verification operation requires a Ver command at a zero state and an RW command at a one state. An AND gate 61 which receives these two orders then delivers a zero state on the connection 57. The change in value of the order Ver with respect to the previous case causes the switch 47 to toggle. The voltage VTi is now available at the midpoint 50 connected on connection 71. Everything goes as for writing, except that VTI replaces Vpp. If memory point 7 was programmed without a trapped load, the current in sensor 13 must vary: this is normal. On the other hand if the transistor I was programmed with trapped charges, even by applying VTI to it, the current in the sensor 13 should not vary. If the current in the sensor 13 varies, it is because an insufficient number of charges had been trapped. We can use this reading information contrary to the expected information, to prevent any use

memory.

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Claims (9)

  1. Read only memory (6) electrically programmable of the memory point type (7) with transistor (1) with floating gate (4), and matrix accessible by lines (5) and columns (9), comprising means (10 , 11) to apply to these rows and columns potentials representative of information to be recorded in the points or representative of read control (13) of the recorded information, characterized in that it includes integrated means (14, 47) to apply to these rows and columns verification potentials whose levels (VTi) are intrinsically fixed.   2. Memory according to claim I characterized in that the   integrated means include means (18) for producing potentials calibrated tiels.   3. Memory according to any one of claims I or 2   characterized in that the means for applying potentials comprise lines (S), called bit lines, connected firstly to the outputs (12) of a line decoder (10), secondly to   information sensors (13), and thirdly to primary connections   floating gate transistors (8), and columns (9), called word lines, connected firstly to the outputs (58) of a decoder   column (11), secondly to the control grids (2) of the transistors   floating gate tors, and thirdly to resistive circuits (52)   application of reading and writing potentials.   4. Memory according to any one of claims 1 to 3   characterized in that the integrated means include a general   multiplier multiplier (14) of Schenkel type.   5. Memory according to any one of claims I to 4   characterized in that the integrated means comprise calibration means provided with a transistor (45) of the same technology as   that of the memory point, receiving on a first main electrode   chip (17) the potential produced by the integrated means, on its control grid a calibrated voltage produced (46) by calibration means, and delivering by its second main electrode (19) the calibrated potential sought.   6. Memory according to claim 5 characterized in that the calibration means comprises an arrangement (41 - 43) in cascade   of transistors in technology (FAMOS) identical to that of the tran-   memory point sistor, these transistors being crossed by a saturation current.   7. Memory according to any of claims 1 to 6   characterized in that it comprises means (47) for switching potentials to apply.   8. Memory according to any one of claims I to 7   characterized in that it includes selection means (61 -47)   to allow the application of different potentials.   9. Memory according to claim 3 characterized in that the word lines are connected to the outputs of the column decoder via a validation circuit (54-59) receiving on the one hand the column addresses of the points and of somewhere else. a validation order (RW-Ver) to drain the currents applied by the resistive chip (52).