JPS62245673A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To manufacture an FET assuring the operational breakdown strength without increasing the occupied space by a method wherein a low concentration drain region in a low concentration drain LDD structure is buried in the depth direction of a wafer to be connected to the high concentration drain region in the wafer. CONSTITUTION:A P type Si substrate 21 is isolated by means of a thick oxide film to form a gate oxide film 22 on an active region; the threshold value of gate oxide film 22 is adjusted by implanting B ions; P added polysilicon 23, a thermal oxide film 24 and an Si3N4 are laminated to be patterned to form a gate electrode; and the substrate 21 is also removed by etching as deep as around 0.25mum. The substrate 21 is inclined to make an oblique angle of 30 deg. to an ion incident axis to implant P ions and form an n<->layer 26. The n<->layer 26 is covered with a thermal oxide film 27 leaving a step difference side only by RIE. Next, As added n<+>polysilicon layers 28 are formed to make the etching depth of substrate 21 the actual length of low concentration drain. Finally, the Si layers 28 are covered with a PSG 29 to form an Al electrode 30 for completion. In such a constitution, a fine and highly reliable IGFET can be manufactured.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor active device that is a component of ultra-high-power semiconductor devices, and in particular to an insulated gate field effect transistor ( (hereinafter referred to as MOS transistor).

[Conventional technology]

MOS transistors have been miniaturized at a rate of 0.6 to 0.7 times every three years, with the aim of increasing the operating speed and the degree of integration. However, the resulting drop in breakdown voltage has gradually become a problem that cannot be ignored in a system environment where the power supply voltage is constant. In particular, the reliability degradation phenomenon caused by hot carriers generated in the high electric field region near the drain junction is serious and is a factor that limits miniaturization.

Various device structures have been proposed to alleviate the drop in breakdown voltage caused by miniaturization. Among them, the one currently playing the most important role is the low concentration drain structure (L
jghtly Doped Drain, commonly known as L S
S p construction).

This structure is disclosed in Directory Patent No. 738280 (filing date: 1972).
It was first proposed in I.E.E., Transactions on Electron Devices, E.D. 29 (1982), pp. 590-596 (TRRR, Trans.
Electron I)ev, 1ces, ED-
29 (1982), p p 590-596), its usefulness and practical feasibility at the ultra-high and ST levels were demonstrated.

FIG. 2 is a cross-sectional view showing the manufacturing process of the LDr' structure. Here, the case of an n-channel device will be explained as an example. p-type silicon semiconductor substrate 11F,
After forming a gate oxide film 12 and a gate electrode 13, an n-type impurity region 14 which will become a low concentration drain is formed by an ion implantation process, as shown in FIG. 2(a). Subsequently, an 8>Ox film is deposited on the entire surface of the wafer by chemical vapor deposition, and anisotropic etching is performed on this to form a gate electrode, as shown by symbol 15 in FIG. 2(b). 5j02 on the side of 13. Etching of the film leaves a residue. When high-concentration ion implantation is performed using this etching residue as a mask, the n÷ type impurity region 1 becomes a high-concentration drain.
6 is formed offset from the gate electrode 13 in a self-aligned manner, and as a result, a DD tank structure is realized in which the channel region is in contact with the lightly doped drain. 1 remaining etching
5 serves to determine the space between the gate electrode wA13 and the heavily doped drain (n-type impurity region) 16.

It is called a side wall spacer.

In the T,nD structure, the voltage drop near the drain junction occurs dispersedly in the lightly doped drain region 14, so that the concentration of the electric field is relaxed and the withstand voltage is improved. 4) However, since the lightly doped drain region 14 also acts as a parasitic series resistance, its impurity profile and planar length (i.e., the distance between the gate electrode and the heavily doped drain) should be optimized and precisely controlled. This is essential in achieving both high voltage resistance and performance, and putting it into practical use at the super- and ST-level.

In the 1.3 μm level T, Ona structure, the surface concentration of the low concentration drain region is set to IXl,Q”(7)-8, the junction depth is set to 0.3 μm, and the planar length is set to 0.2 μm. By doing this, the current drive capability is kept to about 10% lower f than that of normal high concentration drain lateral movement, while
v's withstand voltage direction'').

In addition, by using the manufacturing process steps described above, it is possible to suppress variations between elements in terms of withstand voltage and performance to within a practical range. This is because the impurity profile of the lightly doped drain region is precisely controlled by the ion implantation technique and the subsequent heat treatment process, and its planar length is also determined in a self-aligned manner by the length of the sidewall spacer.

As a result of the above, the 1.3 μm l, 1]1) structure is currently in practical use at the VLSI level, and enables 5V power supply operation, which is impossible with a highly doped drain structure.

[Problem that the invention seeks to solve]

With the above conventional technology, it is not possible to reduce the surface concentration of the low concentration drain region to below approximately 8X1.017m-8. Therefore, in order to proceed with further miniaturization beyond the 1 to 3 μm level currently in practical use, There was a problem that there was a trade-off between the operating voltage and the area occupied by the device.

The reason why the surface concentration of the low concentration drain region cannot be lowered to about 8×10171-8 or less is due to the characteristic deterioration phenomenon caused by hot carriers, as explained below.
) This is because the deterioration mode specific to D becomes apparent, and the reliability (that is, the operating voltage) deteriorates considerably.

In the T, DI structure, as the surface concentration of the lightly doped drain region decreases, the hot carrier injection region into the oxide film moves from the channel portion to the lightly doped drain side.

Above the low-concentration drain region, there is an S t 02 spacer (kite wall spacer) with a high trap density formed by chemical vapor deposition, so if the surface concentration is reduced too much, the 1-wrap charge here will rapidly increase. will increase. This )-wrap charge pinches the lightly doped drain region and increases parasitic series resistance, causing deterioration in current drive capability. The above is ■, D
This is a characteristic deterioration mode specific to the D structure.

As miniaturization progresses, it is necessary to increase the planar length of the lightly doped drain region in order to ensure its operational breakdown voltage without lowering its concentration. For example, in order to enable 5V power supply operation with a 0.5 μm level r, nn structure, the planar length of the lightly doped drain region must be 0.4 to 0.5 μm.
It must be about m. This value is clearly unbalanced when comparing the gate lengths, and significantly impairs the effect of reducing the area occupied by the device due to miniaturization.

An object of the present invention is to provide a high breakdown voltage structure of a MOS transistor that can ensure operating breakdown voltage without sacrificing the area occupied by the MOS transistor.

[Means for solving problems]

The above object is achieved by embedding the lightly doped drain region in the ■,nn structure in the depth direction of the wafer and connecting it to the heavily doped drain region inside the wafer. 1st
The figure is a cross-sectional view showing its structural features.

In FIG. 1, a lightly doped drain region 5 in contact with the channel at the end of the gate electrode 3 is buried in the depth direction of the wafer and is internally connected to a heavily doped drain region 6. Since the oxide film 4 is buried in contact with the lightly doped drain region 5, carriers flowing through the channel proceed along the region 5 in the depth direction and flow into the heavily doped drain region 6 at the bottom of the oxide film 4. Therefore, the buried depth of the oxide film 4 corresponds to the planar length of the lightly doped drain region in the conventional (1, r)D structure.

Note that it is important to form the oxide film 4 by a thermal oxidation method. This is compared to using chemical vapor deposition method.
This is because a high quality film with a significantly low trap density can be obtained.

[Effect]

The feature of the present invention is that, as shown in FIG. 1, the lightly doped drain region 5 inserted between the channel of the MOS transistor and the heavily doped drain is buried in the depth direction of the wafer. This buried depth corresponds to the planar length of the lightly doped drain region in the conventional LDD structure, so by increasing the depth, it is possible to improve the operating voltage without sacrificing the device occupied area. Become.

Another feature of the present invention is that the buried oxide film 4 provided to allow current to flow in the depth direction along the lightly doped drain region can be formed by a thermal oxidation method.

The oxide film formed by the thermal oxidation method has a significantly lower trap density in the film than the film formed by the chemical vapor deposition method, such as the sidewall spacer of the conventional LDD structure sidewall. You can get two effects. One is that it becomes possible to lower the concentration of the low concentration drain region 5 to about 1×10 17 (7) −8 without worrying about the above-mentioned pinch effect. This means that voltage resistance design at the submicron level can be freely performed from both the "length" and "concentration" of the low concentration drain region. Another effect is.

Even if a certain amount of hot carriers are generated in the low concentration drain region, deterioration of device characteristics can be suppressed to a smaller extent than in the conventional Dn structure. This alleviates the trade-off between breakdown voltage and current drive capability, which is the fate of high breakdown voltage structures using low concentration trains.

It means that it will be improved.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 3 to 5.

In FIG. 3, the number 21 indicates a semiconductor substrate, which is a p-type (1,00) silicon wafer with a specific resistance of 10 Ω·m. This board 21. , h, a thick oxide film element isolation region was formed by selective oxidation, and then a gate oxide film 22 was formed in the active region (the element isolation region is not shown in FIG. 3). The thickness of the oxide film in the element isolation region was 600 nm, and the thickness of the gate oxide film was 1.8 nm.

In order to control the threshold voltage Vth, boron (B) ions are implanted through the gate oxide film 22, and then a polycrystalline silicon film 23 is deposited by chemical vapor deposition, and this is doped with phosphorus (P) in a POCQ s atmosphere. went. B ion is 60
1 with acceleration energy of keV. OX 1012ions
/ I typed only cxK. This resulted in a threshold voltage of approximately 0.8 . Moreover, the film thickness of polycrystalline silicon is 31.
0 nm, and the sheet resistance after phosphorus doping was 30Ω/hole.

The surface of polycrystalline silicon 23 is thermally oxidized to form a thin oxide film 2.
After growing 4, a silicon nitride film 25 was formed by chemical vapor deposition. The film thicknesses of the oxide film 24 and the silicon nitride film 25 were 30 nm and 50 nm, respectively. continue,
Using photo-etching and dry etching techniques, a silicon nitride film of 25 degrees and an oxide film of 24 degrees were formed. Polycrystalline silicon film 23. Gate oxidation, -
' Patterning H22 to form a gate electrode 1
1) After that, the silicon substrate 21 was also etched in a different direction. The gate length after patterning was 0.8 .mu.m, and the anisotropic etching of the silicon substrate 21 was carried out almost according to that dimension, and the depth was 0.25 .mu.m. [Figure 3 (a)]
.

Next, the silicon substrate is tilted with respect to the ion incident axis,
By implanting phosphorus (P) ions while rotating, n-
A type low concentration impurity region 26 is formed. Ion implantation was performed with the silicon substrate tilted by 30', the acceleration energy was 60 k eV, and the implantation amount was 9 x 1.
．． O12i, ons/cxK. At this time, the phosphorus concentration on the vertically etched side surface of the silicon substrate was 7.
X 1 o"m-8 [Fig. 3(b)].

After growing a 35 nm oxide film on the surface of the silicon substrate using the thermal oxidation method, the oxide film is anisotropically etched using a dry etching method, and the thermal oxide film is etched only on the side surfaces of the silicon substrate steps. The remaining 27 were formed. This etching residue will eventually become an oxide film buried in contact with the low concentration drain region [FIG. 3(C)].

Next, polycrystalline silicon doped with a large amount of arsenic (A s ) is selectively deposited on the bottom surface of the silicon substrate that is not covered with an oxide film, and an n+ type high-concentration impurity, which will become the high-concentration drain of the MOS transistor, is deposited. A region 28 was formed. As diffused from polycrystalline silicon into the silicon substrate goes around to the bottom of the buried oxide film 27, as shown in FIG.
) is the effective length of the lightly doped drain region [FIG. 3(d)].

Finally, an interlayer insulating film made of phosphosilicate glass 29.

The manufacturing process was completed by forming contact holes and aluminum electrode wiring 30 [FIG. 3(e)].

The completed device with a gate length of 0.8 μm has a hot carrier withstand voltage of 6.5V (maximum operating voltage that can satisfy long-term reliability) while suppressing the current drive capability drop to 15% due to the highly doped drain structure. We were able to realize this. Since the hot carrier breakdown voltage of the high concentration drain structure is 3V, the performance decreases by 1.5% and the voltage is 3.5V.
This means that an increase in pressure resistance of 100% was obtained.

On the other hand, the conventional technology with a gate length of 0.8 μm■, 1〕■〕
In the structure, we were able to obtain a hot carrier breakdown voltage of 6.5 V by setting the planar length of the lightly doped drain region with a surface concentration of 1.018(1)-8 to 0.4 μm. On the other hand, the occupied area increases significantly, and the current driving ability for the highly doped drain structure also decreases.
It reached just under %. The structure of the present invention has excellent characteristics as a basic device at the 0.8 μm level in that the current drive capability is only slightly reduced and no extra area is required for a lightly doped drain. There is.

FIG. 4 shows the relationship between current drive capability and hot carrier breakdown voltage in a high voltage MOS transistor.

It can be seen that the trade-off between the two is improved by the present invention compared to the prior art T and DD structures.

FIG. 5 shows the relationship between the surface concentration and hot carrier breakdown voltage under the condition that the length of the lightly doped drain region is constant. Prior art ■, r) In the n structure, the surface concentration is 101
When it reaches the order of 7(7)'8, the inherent characteristic deterioration mode becomes noticeable and the hot carrier withstand voltage decreases. In contrast, in the present invention, the lower the surface concentration is, the higher the hot carrier breakdown voltage can be (at least up to 1×1017(7)-8), which shows that there is a large degree of freedom in breakdown voltage design. .

〔Effect of the invention〕

According to the present invention, it is possible to improve the trade-off between operating breakdown voltage and current drive capability, which was the fate of the prior art T, T) n structure, and to avoid an increase in the device occupation area due to the low concentration train region. I can do it. This has the effect of making it possible to operate on a 5V power supply while achieving high integration and high performance of submicron level MO8, ■, and ST.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MOS transistor structure according to the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process steps of a prior art structure, and FIG. 3 is a cross-sectional view showing an embodiment of the present invention. The manufacturing process [1] Figure 4 shows the present invention and the prior art. current yIt
Characteristic diagram showing the relationship between dynamic capacity and hot carrier breakdown voltage, 5th
The figure is a characteristic diagram showing the relationship between the surface concentration of the low concentration drain region and the low pressure of hot carriers in the T and D n structures of the present invention and the prior art. DESCRIPTION OF SYMBOLS 1... First conductivity type semiconductor substrate, 2... Gate oxide film, 3... Gate electrode, 4... Buried oxide film, 5...
- Second conductivity type low-a degree impurity region, 6... Second conductivity type high concentration impurity region, 11... p-type semiconductor substrate, 12.
...Gate oxide film, 13...Goo 1~electrode, 14...
- n-type low concentration impurity region, 15... side wall spacer, 16... n-type high concentration impurity region, 21.
... p-type semiconductor substrate, 22 ... gate oxide film, 23.
...Polycrystalline silicon gate electrode, 24...Silicon oxide film, 25...Silicon nitride film, 26...N-type 1
('A degree impurity region, 27... recessed oxide film, 28
...r1+ type high concentration impurity region, 29...phosphosilicate glass film, :30...aluminum shoulder 2 figure (l-H+) n- made Yi B tt p type + Fu A to low T good /4 Infertile; Beno 2 Sa”°-to Nishi-in 4hi 15 Sun Idoman-I
t/s, he'-s Figure 3

Claims (1)

[Claims] 1. Between the channel region on the first conductivity type semiconductor substrate and the first drain region consisting of the second conductivity type semiconductor region, the resistivity is lower than that of the first conductivity type semiconductor substrate. and an insulated gate field effect transistor having a second drain region made of a second conductivity type semiconductor region having a higher resistivity than the first drain region, wherein the second drain region is formed in the first conductivity type semiconductor substrate. A semiconductor device characterized in that the semiconductor device is buried in the depth direction of the substrate from the surface and connected to a first drain region inside the substrate. 2. Providing a gate insulating film on the semiconductor substrate, providing a gate electrode on the gate insulating film, providing an etching-resistant film on the gate electrode, and etching the semiconductor substrate using the etching-resistant film as a mask. a step of introducing an impurity into the entire etched surface; a step of thermally oxidizing the surface into which the impurity has been introduced; a step of etching leaving a side wall portion of the oxide film formed by the thermal oxidation; 1. A method for manufacturing a semiconductor device, comprising the step of stacking a highly conductive semiconductor thereon.