JPH03156976A - Semiconductor and manufacture thereof - Google Patents
Semiconductor and manufacture thereofInfo
- Publication number
- JPH03156976A JPH03156976A JP29668789A JP29668789A JPH03156976A JP H03156976 A JPH03156976 A JP H03156976A JP 29668789 A JP29668789 A JP 29668789A JP 29668789 A JP29668789 A JP 29668789A JP H03156976 A JPH03156976 A JP H03156976A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- insulating film
- concentration impurity
- diffusion region
- impurity diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- 239000012535 impurity Substances 0.000 claims description 48
- 238000009792 diffusion process Methods 0.000 claims description 41
- 239000000758 substrate Substances 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 12
- 238000005468 ion implantation Methods 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 239000013078 crystal Substances 0.000 claims description 7
- 238000002955 isolation Methods 0.000 claims description 7
- 230000000630 rising effect Effects 0.000 claims description 4
- 150000002500 ions Chemical class 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 2
- 239000012212 insulator Substances 0.000 abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 13
- 229910052710 silicon Inorganic materials 0.000 description 13
- 239000010703 silicon Substances 0.000 description 13
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 9
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 4
- 229910052801 chlorine Inorganic materials 0.000 description 4
- 239000000460 chlorine Substances 0.000 description 4
- 125000006850 spacer group Chemical group 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000002844 melting Methods 0.000 description 2
- 230000008018 melting Effects 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- WKBOTKDWSSQWDR-UHFFFAOYSA-N Bromine atom Chemical compound [Br] WKBOTKDWSSQWDR-UHFFFAOYSA-N 0.000 description 1
- KZBUYRJDOAKODT-UHFFFAOYSA-N Chlorine Chemical compound ClCl KZBUYRJDOAKODT-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- GDTBXPJZTBHREO-UHFFFAOYSA-N bromine Substances BrBr GDTBXPJZTBHREO-UHFFFAOYSA-N 0.000 description 1
- 229910052794 bromium Inorganic materials 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000002784 hot electron Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- -1 phosphorus ions Chemical class 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-AKLPVKDBSA-N silicon-31 atom Chemical compound [31Si] XUIMIQQOPSSXEZ-AKLPVKDBSA-N 0.000 description 1
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置、特に半導体素子内の導電性領域の
構造とその製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a structure of a conductive region in a semiconductor element and a method for manufacturing the same.
近年、シリコン半導体集積回路の高集積化や高速化に伴
ってゲート電極におけるゲート長の短縮が盛んに行われ
ているが、ゲート長が短縮するに従って半導体素子にＬ
ＤＤ（Ｌｉｇｈｔｌｙ Ｄｏｐｅｄ Ｄｒａｉｎ）構造
が用いられるようになってきた。例えば、斉藤和之等に
より１ゞ新構造短チャネルＭＯ３ＦＥＴ”電子通信学会
総合全国大会ｉ＋ １９７８． ｐｐ、２〜１０におい
て発表された。第２図はＬＤＤ構造の半導体素子を示す
略図である。図において、１１はＰ型シリコン基板、１
２は素子分離絶縁膜、１３はゲート絶縁膜、１４は閾値
制御不純物、１５はゲート電極、１６は低濃度不純物拡
散領域、１７はサイドスペーサー（絶縁膜）、１８は高
濃度不純物拡散領域である。In recent years, with the increasing integration and speed of silicon semiconductor integrated circuits, the gate length of gate electrodes has been frequently shortened.
A DD (Lightly Doped Drain) structure has come into use. For example, Kazuyuki Saito et al. presented 1゜New Structure Short Channel MO3FET at IEICE General Conference i+ 1978.pp, 2-10. Figure 2 is a schematic diagram showing a semiconductor element with an LDD structure. , 11 is a P-type silicon substrate, 1
2 is an element isolation insulating film, 13 is a gate insulating film, 14 is a threshold control impurity, 15 is a gate electrode, 16 is a low concentration impurity diffusion region, 17 is a side spacer (insulating film), and 18 is a high concentration impurity diffusion region. .
■、ＤＤ槽構造半導体素子を製造する際、低濃度不純物
拡散領域を形成するため絶縁性物質で形成されるサイド
スペーサーが必要であるが、従来は第２図に示すように
、サイドスペーサー１７はシリコン基板１１の表面に形
成しているため、サイドスペーサー１７は低濃度不純物
拡散領域１６の横ｌ」に相当する幅のものが必要となり
、その設置スペースが広くなってしまい、サイドスペー
サーが素子の微細化の妨げとなる。(2) When manufacturing a semiconductor device with a DD tank structure, side spacers made of an insulating material are required to form a low concentration impurity diffusion region. Conventionally, as shown in FIG. 2, side spacers 17 are Since it is formed on the surface of the silicon substrate 11, the side spacer 17 needs to have a width equivalent to 1" horizontally of the low concentration impurity diffusion region 16, and the installation space becomes large. This impedes miniaturization.
本発明の目的は」１記問題点を解消した半導体装置及び
その製造方法を提供することにある。An object of the present invention is to provide a semiconductor device and a method for manufacturing the same that solves the problem mentioned above.
上記目的を達成するため、本発明の半導体装置において
は、導電性領域が高濃度不純物拡散領域とゲート電極近
傍の低濃度不純物拡散領域とによって構成される半導体
装置において、前記高濃度不純物拡散領域と前記低濃度
不純物拡散領域とを前記ゲート電極より隔絶する絶縁膜
を、前記ゲート電極の側壁に沿って立上る前記拡散領域
の界面に沿わせて有するものである。To achieve the above object, in a semiconductor device of the present invention, in a semiconductor device in which a conductive region is constituted by a high concentration impurity diffusion region and a low concentration impurity diffusion region near the gate electrode, the high concentration impurity diffusion region An insulating film separating the low concentration impurity diffusion region from the gate electrode is provided along an interface of the diffusion region rising along a sidewall of the gate electrode.
また、本発明の半導体装置は、素子分離絶縁膜間に位置
する半導体基板の素子形成領域表面」二にゲート絶縁膜
を形成する工程と、前記ゲート絶縁膜上にゲート電極を
形成する工程と、前記ゲート電極をマスクとしてエツチ
ング加工することにより、ゲート電極部分を除いた半導
体基板の素子形成領域表面を所定深さ位置まで掘下げる
工程と、前記ゲート電極の側壁を含み、前記エツチング
加工によるエツチング側壁に絶縁膜を形成する工程と、
前記絶縁膜に沿う半導体基板の素子形成領域表面にイオ
ン注入による低濃度不純物拡散領域の形成を行う工程と
、エツチング加工により、ゲート電極の側壁及び半導体
基板の掘下げられた領域３
の側壁にのみ前記絶縁膜を残す工程と、前記半導体基板
の掘下げられた領域内で単結晶の結晶成長を行い、その
単結晶にイオン注入して高濃度不純物拡散領域を形成す
る工程とを含む製造方法によって得られる。Further, the semiconductor device of the present invention includes a step of forming a gate insulating film on the surface of the element formation region of the semiconductor substrate located between the element isolation insulating films, and a step of forming a gate electrode on the gate insulating film. etching the surface of the element formation region of the semiconductor substrate excluding the gate electrode portion by etching the gate electrode as a mask; etching the etched sidewalls including the sidewalls of the gate electrode; a step of forming an insulating film on the
A step of forming a low concentration impurity diffusion region by ion implantation on the surface of the element formation region of the semiconductor substrate along the insulating film and an etching process are performed to form a low concentration impurity diffusion region only on the side wall of the gate electrode and the side wall of the dug region 3 of the semiconductor substrate. Obtained by a manufacturing method including a step of leaving an insulating film, and a step of growing a single crystal in the dug region of the semiconductor substrate and implanting ions into the single crystal to form a high concentration impurity diffusion region. .
半導体素子内の導電性領域を形成する高濃度不純物拡散
領域と低濃度不純物拡散領域の界面一部に絶縁膜を有す
ることにより、ドレイン部での高電界が緩和されホット
エレクトロン問題が解消し、ＬＤＤ構造の半導体素子と
同等の特性が得られ、しかも、前記絶縁膜のスペースを
可及的極小にすることが可能となり、素子の微細化が図
れるという利点がある。By having an insulating film on a part of the interface between the high concentration impurity diffusion region and the low concentration impurity diffusion region that form the conductive region in the semiconductor element, the high electric field in the drain region is alleviated, the hot electron problem is solved, and the LDD This structure has the advantage that characteristics equivalent to those of a semiconductor element can be obtained, and the space of the insulating film can be made as small as possible, allowing miniaturization of the element.
〔実施例］ 以下、本発明の一実施例を図面を用いて説明する。〔Example] An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例を示す模式的断面図である。FIG. 1 is a schematic cross-sectional view showing one embodiment of the present invention.
図において、本発明に係る半導体装置において−
は、素子分離絶縁膜２，２に囲まれたＰ型シリコン基板
ｌの素子形成領域表面にゲート絶縁膜３を介してゲート
電極６が形成してあり、ゲート絶縁膜３に連らなる絶縁
膜７がゲート電極６の側壁を覆うとともに、その下端が
Ｐ型シリコン基板１の表面凹部１ａ内に延設しである。In the figure, in the semiconductor device according to the present invention, a gate electrode 6 is formed on the surface of an element forming region of a P-type silicon substrate l surrounded by element isolation insulating films 2, 2, with a gate insulating film 3 interposed therebetween. An insulating film 7 continuous to the gate insulating film 3 covers the side walls of the gate electrode 6, and its lower end extends into the surface recess 1a of the P-type silicon substrate 1.
さらに、基板ｌの凹部１ａの底部及び絶縁膜７の立」ユ
リ部内側に沿って低濃度不純物拡散領域８が形成され、
低濃度不純物拡散領域８及び絶縁膜７並びに素子分離絶
縁膜２によって取囲まれた基板ｌの凹部１ａ内に高濃度
不純物拡散領域９が形成しである。４はパンチスルー防
止不純物、５は閾値制御不純物である。Further, a low concentration impurity diffusion region 8 is formed along the bottom of the recess 1a of the substrate l and the inside of the vertical ridge of the insulating film 7,
A high concentration impurity diffusion region 9 is formed in the recess 1a of the substrate 1 surrounded by the low concentration impurity diffusion region 8, the insulating film 7, and the element isolation insulating film 2. 4 is a punch-through prevention impurity, and 5 is a threshold control impurity.
この構成により、本発明は高濃度不純物拡散領域９と低
濃度不純物拡散領域８をゲート電ｆｆ１６より隔絶する
絶縁膜７を、ゲート電極６の側壁に沿って立」二る両拡
散領域８，９の界面に沿って有することとなる。したが
って、本発明によれば、シリコン基板ｌの表面のうちゲ
ート電極６を除いた部分に形成した凹部１ａの立上り側
壁に沿って絶縁膜７を配置して低濃度不純物拡散領域８
を形成するに必要な長さを」二下方向で確保することが
できることとなり、該絶縁膜７の横方向寸法を可及的極
小として素子の微細化が可能となる。With this configuration, the present invention allows the insulating film 7 that isolates the high-concentration impurity diffusion region 9 and the low-concentration impurity diffusion region 8 from the gate electrode ff16 to form both diffusion regions 8, 9 that stand along the sidewalls of the gate electrode 6. along the interface. Therefore, according to the present invention, the insulating film 7 is disposed along the rising sidewall of the recess 1a formed on the surface of the silicon substrate 1 excluding the gate electrode 6, and the low concentration impurity diffusion region 8
The length necessary for forming the insulating film 7 can be secured in the two downward directions, and the lateral dimension of the insulating film 7 can be minimized as much as possible, making it possible to miniaturize the element.
第３図（ａ）、（ロ）、［Ｆ］）、 （ｄ）は本発明の
半導体装置の製造方法を工程順に示した模式図である。FIGS. 3(a), (b), [F]), and (d) are schematic diagrams showing the method for manufacturing a semiconductor device of the present invention in order of steps.
第３図（ａ）において、Ｐ型シリコン基板２１上にシリ
コン酸化膜からなる素子分離絶縁膜２２を形成し、続い
て基板２１の素子形成領域表面にゲート絶縁膜２３を形
成する。次に、イオン注入法を用いてパンチスルー防止
不純物２４としてボロンを注入する。続いて、閾値制御
不純物２５としてイオン注入法を用いてボロンの注入を
行う。次に、燐を熱拡散法により拡散したポリシリコン
からなるゲート電極２６をゲート絶縁膜２３上にドライ
エツチング法を用いて加工形成する。次に、第３図（ハ
）において、導電性領域となるシリコン基板２１の素子
形成領域表面を破線２７より２８の矢印まで塩素のＲＩ
Ｅ技術を用いて１５００人掘下げる。続いて第３図（ｃ
）において、導電性領域の高濃度不純物拡散領域と低濃
度不純物拡散領域を隔絶する絶縁膜２９としてＣＶＤ法
を用いてシリコン窒化膜を基板２１の掘下げられた凹部
２１ａの底部及び立上り側壁並びにゲート電極２４の側
壁上に１５０人堆積形成し、続いてシリコン基板２１の
表面に４５度の角度から燐のイオン注入を行い低濃度不
純物拡散領域３０を絶縁膜２９に沿って形成する。次に
、第３図（イ）において、ＣＦ４ガスを用いた［Ｅ技術
を用い前記堆積したシリコン窒化膜３０の全面エツチン
グを行いゲート電極側壁及び塩素のドライエツチング法
を用いて掘下げた領域の側壁のみにシリコン窒化膜２９
を残す。続いて５ｉｔ（４とＨＣＱを用いたシリコンの
選択エピタキシャル法を用いて高濃度不純物拡散領域と
なる領域に３１の矢印まで１５００人のシリコンの結晶
成長を行い、続いてイオン注入法を用いて結晶成長した
単結晶シリコン３１に燐のイオン注入３２を行い高濃度
不純物拡散領域３３を形成することにより第１図の構造
を得る。In FIG. 3(a), an element isolation insulating film 22 made of a silicon oxide film is formed on a P-type silicon substrate 21, and then a gate insulating film 23 is formed on the surface of the element formation region of the substrate 21. Next, boron is implanted as a punch-through prevention impurity 24 using an ion implantation method. Subsequently, boron is implanted as a threshold control impurity 25 using an ion implantation method. Next, a gate electrode 26 made of polysilicon in which phosphorus is diffused by a thermal diffusion method is formed on the gate insulating film 23 by using a dry etching method. Next, in FIG. 3(c), the surface of the element formation region of the silicon substrate 21, which will become a conductive region, is treated with chlorine RI from the broken line 27 to the arrow 28.
Use E technology to dig down to 1,500 people. Next, Figure 3 (c
), a silicon nitride film is deposited using the CVD method as an insulating film 29 separating the high concentration impurity diffusion region and the low concentration impurity diffusion region of the conductive region, on the bottom and rising side walls of the recess 21a of the substrate 21, and on the gate electrode. Then, phosphorus ions are implanted into the surface of the silicon substrate 21 at an angle of 45 degrees to form a low concentration impurity diffusion region 30 along the insulating film 29. Next, in FIG. 3(A), the entire surface of the deposited silicon nitride film 30 is etched using the [E technique using CF4 gas, and the side walls of the gate electrode and the side walls of the dug region are etched using a chlorine dry etching method. Only silicon nitride film 29
leave. Next, a silicon selective epitaxial method using 5IT (4 and HCQ) was used to grow 1,500 silicon crystals up to the arrow 31 in the region that would become the high concentration impurity diffusion region, and then ion implantation was used to grow the crystal. The structure shown in FIG. 1 is obtained by performing phosphorus ion implantation 32 into the grown single crystal silicon 31 to form a high concentration impurity diffusion region 33.
以上実施例では、ゲート電極は燐を熱拡散したポリシリ
コンを用いたが、ゲート電極として用いることができる
低抵抗材料であれば燐拡散を行ったポリシリコンに限ら
ず、例えば高融点金属や高７
融点金属とのポリサイド構造でも構わない。また、導電
性領域となる領域を塩素のＲＩＥ技術を用いて掘下げた
が、異方的なエツチング形状が得られれば塩素のＲＩＥ
に限らず、例えば臭素を用いたＲＩＥや塩素ガスを用い
たＥＣＲによるエツチングが有望である。また、低濃度
不純物拡散領域を形成する際、燐の斜めイオン注入を用
いて不純物の導入を行っているが、側壁に不純物が導入
されれば斜めイオン注入に限らず、例えばＰＳＧ （燐
ガラス）を高濃度不純物拡散領域と低濃度不純物拡散領
域を隔絶する絶縁膜２９に用い熱処理を行えば燐の斜め
イオン注入を行ったときと同等の効果が得られる。In the above embodiments, polysilicon with thermally diffused phosphorus was used for the gate electrode, but polysilicon with phosphorus diffused therein may be used as long as it is a low resistance material that can be used as the gate electrode, such as a high melting point metal or a high 7 A polycide structure with a melting point metal is also acceptable. In addition, we used chlorine RIE technology to dig down the area that would become the conductive region, but if an anisotropic etching shape could be obtained, chlorine RIE
For example, etching by RIE using bromine or ECR using chlorine gas is promising. In addition, when forming a low concentration impurity diffusion region, impurities are introduced using oblique ion implantation of phosphorus, but if impurities are introduced into the sidewall, oblique ion implantation is not limited to, for example, PSG (phosphorus glass). If this is used for the insulating film 29 separating the high-concentration impurity diffusion region and the low-concentration impurity diffusion region and heat treatment is performed, an effect equivalent to that obtained by performing oblique ion implantation of phosphorus can be obtained.
さらに、低濃度不純物拡散領域の不純物は燐を用いてい
るが、砒素を用いても実施できる。また、高濃度不純物
拡散領域の形成にシリコンの選択エピタキシャル成長を
行った後、燐のイオン注入を行い形成しているが、結晶
成長を行いながら不純物を導入するドープトエピタキシ
ャル成長も有望である。Furthermore, although phosphorus is used as the impurity in the low concentration impurity diffusion region, arsenic may also be used. In addition, although high concentration impurity diffusion regions are formed by selective epitaxial growth of silicon and then ion implantation of phosphorus, doped epitaxial growth, in which impurities are introduced while crystal growth is being performed, is also promising.
〔発明の効果］
８−
以上のように本発明によれば、ゲート長が短縮されるに
従い発生した半導体素子特性の劣化を回復することがで
き信頼性を向上できる。また、半導体素子の微細化が図
れる利点がある。[Effects of the Invention] 8- As described above, according to the present invention, it is possible to recover from the deterioration of semiconductor device characteristics that occurs as the gate length is shortened, and to improve reliability. Further, there is an advantage that semiconductor elements can be miniaturized.
第１図は本発明における半導体装置の構造を示す模式的
断面図、第２図は従来例を示す模式図、第３図（ａ）、
■、 （ｃ）、 （ｄ）は本発明の製造工程を説明する
模式図である。
１、ＩＩ、２１・・・Ｐ型シリコン基板２．１２．２２
・・・素子分離絶縁膜
３．１３．２３・・・ゲート絶縁膜
４．２４・・・パンチスルー防止不純物５．１４．２５
・・・閾値制御不純物
６．１５．２６・・・ゲート電極
７．２９・・・高濃度不純物拡散領域と低濃度不純物拡
散領域を隔絶する絶縁膜FIG. 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to the present invention, FIG. 2 is a schematic view showing a conventional example, FIG. 3(a),
(2), (c), and (d) are schematic diagrams illustrating the manufacturing process of the present invention. 1, II, 21...P-type silicon substrate 2.12.22
...Element isolation insulating film 3.13.23...Gate insulating film 4.24...Punch-through prevention impurity 5.14.25
...Threshold control impurity 6.15.26...Gate electrode 7.29...Insulating film separating the high concentration impurity diffusion region and the low concentration impurity diffusion region
Claims (2)
近傍の低濃度不純物拡散領域とによって構成される半導
体装置において、前記高濃度不純物拡散領域と前記低濃
度不純物拡散領域とを前記ゲート電極より隔絶する絶縁
膜を、前記ゲート電極の側壁に沿って立上る前記拡散領
域の界面に沿わせて有することを特徴とする半導体装置
。(1) In a semiconductor device in which the conductive region is composed of a high concentration impurity diffusion region and a low concentration impurity diffusion region near the gate electrode, the high concentration impurity diffusion region and the low concentration impurity diffusion region are separated from the gate electrode. A semiconductor device comprising: an insulating film extending along an interface of the diffusion region rising along a sidewall of the gate electrode.
成領域表面上にゲート絶縁膜を形成する工程と、前記ゲ
ート絶縁膜上にゲート電極を形成する工程と、前記ゲー
ト電極をマスクとしてエッチング加工することにより、
ゲート電極部分を除いた半導体基板の素子形成領域表面
を所定深さ位置まで掘下げる工程と、前記ゲート電極の
側壁を含み、前記エッチング加工によるエッチング側壁
に絶縁膜を形成する工程と、前記絶縁膜に沿う半導体基
板の素子形成領域表面にイオン注入による低濃度不純物
拡散領域の形成を行う工程と、エッチング加工により、
ゲート電極の側壁及び半導体基板の掘下げられた領域の
側壁にのみ前記絶縁膜を残す工程と、前記半導体基板の
掘下げられた領域内で単結晶の結晶成長を行い、その単
結晶にイオン注入して高濃度不純物拡散領域を形成する
工程とを含むことを特徴とする半導体装置の製造方法。(2) Forming a gate insulating film on the surface of the element formation region of the semiconductor substrate located between the element isolation insulating films, forming a gate electrode on the gate insulating film, and etching using the gate electrode as a mask. By processing,
a step of digging down the surface of the element formation region of the semiconductor substrate excluding the gate electrode portion to a predetermined depth; a step of forming an insulating film on the side wall etched by the etching process including the side wall of the gate electrode; and a step of forming an insulating film on the etched side wall by the etching process. By forming a low concentration impurity diffusion region by ion implantation on the surface of the element formation region of the semiconductor substrate along the
A step of leaving the insulating film only on the sidewalls of the gate electrode and the sidewalls of the sunken region of the semiconductor substrate, growing a single crystal within the sunken region of the semiconductor substrate, and implanting ions into the single crystal. A method of manufacturing a semiconductor device, comprising the step of forming a high concentration impurity diffusion region.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296687A JP2705254B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1296687A JP2705254B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor device and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03156976A true JPH03156976A (en) | 1991-07-04 |
| JP2705254B2 JP2705254B2 (en) | 1998-01-28 |
Family
ID=17836782
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1296687A Expired - Lifetime JP2705254B2 (en) | 1989-11-15 | 1989-11-15 | Semiconductor device and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2705254B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5598021A (en) * | 1995-01-18 | 1997-01-28 | Lsi Logic Corporation | MOS structure with hot carrier reduction |
| US5675164A (en) * | 1995-06-07 | 1997-10-07 | International Business Machines Corporation | High performance multi-mesa field effect transistor |
| US5828103A (en) * | 1994-08-29 | 1998-10-27 | United Microelectronicws Corp. | Recessed lightly doped drain (LDD) for higher performance MOSFET |
| JP2003526943A (en) * | 2000-03-13 | 2003-09-09 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for forming source / drain regions having deep junctions |
| US7687854B2 (en) * | 2003-08-19 | 2010-03-30 | Magnachip Semiconductor, Ltd. | Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode |
| CN105027291A (en) * | 2013-03-29 | 2015-11-04 | 英特尔公司 | Transistor architecture having extended recessed spacer and source/drain regions and method of making same |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245673A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS6373770A (en) * | 1986-09-16 | 1988-04-04 | Fuji Photo Film Co Ltd | Picture inversion method |
| JPS6473770A (en) * | 1987-09-16 | 1989-03-20 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
-
1989
- 1989-11-15 JP JP1296687A patent/JP2705254B2/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62245673A (en) * | 1986-04-18 | 1987-10-26 | Hitachi Ltd | Semiconductor device and manufacture thereof |
| JPS6373770A (en) * | 1986-09-16 | 1988-04-04 | Fuji Photo Film Co Ltd | Picture inversion method |
| JPS6473770A (en) * | 1987-09-16 | 1989-03-20 | Fujitsu Ltd | Semiconductor device and manufacture thereof |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5828103A (en) * | 1994-08-29 | 1998-10-27 | United Microelectronicws Corp. | Recessed lightly doped drain (LDD) for higher performance MOSFET |
| US5598021A (en) * | 1995-01-18 | 1997-01-28 | Lsi Logic Corporation | MOS structure with hot carrier reduction |
| US5663083A (en) * | 1995-01-18 | 1997-09-02 | Lsi Logic Corporation | Process for making improved MOS structure with hot carrier reduction |
| US5675164A (en) * | 1995-06-07 | 1997-10-07 | International Business Machines Corporation | High performance multi-mesa field effect transistor |
| JP2003526943A (en) * | 2000-03-13 | 2003-09-09 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for forming source / drain regions having deep junctions |
| JP4889901B2 (en) * | 2000-03-13 | 2012-03-07 | アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド | Method for forming source / drain regions having deep junctions |
| US7919380B2 (en) | 2003-08-19 | 2011-04-05 | Magnachip Semiconductor, Ltd. | Method of manufacturing a transistor in semiconductor device having a gate electrode located between the trenches formed in low-concentration regions of the source and drain regions including high-concentration regions formed at the bottom of the trenches |
| US7687854B2 (en) * | 2003-08-19 | 2010-03-30 | Magnachip Semiconductor, Ltd. | Transistor in a semiconductor substrate having high-concentration source and drain region formed at the bottom of a trench adjacent to the gate electrode |
| CN105027291A (en) * | 2013-03-29 | 2015-11-04 | 英特尔公司 | Transistor architecture having extended recessed spacer and source/drain regions and method of making same |
| KR20150138166A (en) * | 2013-03-29 | 2015-12-09 | 인텔 코포레이션 | Transistor architecture having extended recessed spacer and source/drain regions and method of making same |
| JP2016514905A (en) * | 2013-03-29 | 2016-05-23 | インテル・コーポレーション | Transistor architecture having extended recess spacer and multiple source / drain regions and method of manufacturing the same |
| US9786783B2 (en) | 2013-03-29 | 2017-10-10 | Intel Corporation | Transistor architecture having extended recessed spacer and source/drain regions and method of making same |
| GB2527214B (en) * | 2013-03-29 | 2020-06-17 | Intel Corp | Transistor Architecture having extended recessed spacer and source/drain regions and method of making same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2705254B2 (en) | 1998-01-28 |
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