JP2003526943A - Method for forming source / drain regions having deep junctions - Google Patents

Abstract

(57) The present invention is directed to a method of forming source / drain regions (31) in a semiconductor device. In one embodiment, the method includes forming a gate stack (17) on a semiconductor substrate (12), and forming a recess (24) in the substrate (12) proximate to the gate stack (17). And forming an implantation process (30) and implanting dopant atoms into the bottom surface (27) of the recess (24). The method includes the steps of forming a layer of epitaxial silicon (32) in the recess (24) and a second ion implantation process (38), doping at least the epitaxial silicon (32) in the recess (24). Forming the doped region (33) and performing an annealing process to activate the implanted dopant atoms.

Description

Detailed Description of the Invention

[0001]

【Technical field】

The present invention is generally directed to the field of semiconductor processing, and more specifically to methods of forming source / drain regions in semiconductor devices.

[0002]

[Background technology]

There is a constant trend in the semiconductor industry to increase the overall performance and operating speed of integrated circuit devices such as microprocessors and memory devices. Consumer demand for increasingly fast computer and electronic devices has fueled this trend. Due to this demand for higher speeds, the size of semiconductor devices such as transistors has been constantly reduced. That is, many components of a typical field effect transistor (FET), such as channel length, junction depth, gate dielectric thickness, etc., are reduced. For example, all other things being equal, the smaller the channel length of the transistor, the faster the operation of the transistor. Therefore, there is a tendency to reduce the size or scale of typical transistor components to constantly improve the device performance and overall speed of transistors as well as integrated circuit devices incorporating such transistors.

As described above, with the tendency to constantly improve the performance of the transistor, it is necessary to investigate all aspects of the device operation in order to improve the device performance. For example, it is necessary to reduce the leakage current that may occur each time a semiconductor element such as a transistor is “on” or “off”. One factor that tends to increase these leakage currents is having source / drain junctions that are not deep enough. Typically, contacts containing metal suicides such as cobalt suicides are formed on the source / drain regions to facilitate electrical connection of the conductive lines to the source / drain regions, ie contact resistance using the metal suicide regions. Reduce. Junctions are generally understood to be at times when the concentration of N-type dopant atoms and the concentration of P-type dopant atoms are approximately equal, but if this depth is not sufficient,
Leakage current may occur when the device is either "on" or "off". Therefore, it is generally desirable to form source / drain regions with deep junction depths rather than shallow depths.

In general, the source / drain regions may be formed by various techniques. For example, the source / drain regions may be formed by performing a number of ion implantation processes in which various dopant atoms are implanted in the semiconductor substrate. The initial ion implantation process may be performed to form a relatively shallow and wide implant in the substrate. Then, conventional sidewall source / drain implants may be performed at a relatively high dopant concentration after the sidewall spacers are formed adjacent the gate stack,
Do deeper than the first wide injection. Another implantation process, typically referred to as a co-implantation process, may then be performed to obtain a deeper bond. However, due to the lateral diffusion of these deeper junctions, the junction depth cannot be deeper than about 1500Å in conventional process flows.

Another problem associated with source / drain regions is capacitance. It is generally desirable to reduce the capacitance created by the source / drain regions to improve device performance. This capacitance must be charged and discharged every operating cycle when the transistor is "on" or "off". As a result, an RC time delay related to signal propagation is caused over the entire element, and in addition, power consumption by the element during operation is increased. In general, it would be desirable to have a source / drain region with a more gradual dopant concentration profile that reduces the capacitance of the source / drain region.

The present invention is directed to a method of solving, or at least reducing, some or all of the above problems.

[0007]

DISCLOSURE OF THE INVENTION

The present invention is directed to a method of forming source / drain regions in a semiconductor device. In one embodiment, the method includes forming a gate stack on a semiconductor substrate and forming an indent in the substrate adjacent the gate stack, the indent having a bottom surface, the method comprising: Further, the method includes performing a first ion implantation process in the bottom surface of the recess to form a first doped region. The method comprises the steps of forming a layer of epitaxial silicon within the recess and performing a second ion implantation process to form a second doped region within at least a portion of the epitaxial silicon layer within the recess. , And annealing the first and second doped regions.

The present invention may be understood by reference to the following description in conjunction with the accompanying drawings. In the drawings, like reference numbers identify like elements.

While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the drawings and will herein be described in detail. However, the following description of specific embodiments is not intended to limit the invention to the particular forms disclosed, conversely, the intent of the invention as defined by the appended claims. It should be understood that all variations, equivalents, and alternatives that fall within the spirit and scope are to be included.

[0010]

[Modes for Carrying Out the Invention]

Embodiments of the present invention will be described below. In the interest of clarity, not all features of an actual implementation are described in this specification. In the development of any such actual implementation, implementation-specific in order to achieve a developer's specific goals, such as alignment with different system-related and business-related constraints for each implementation. It will be understood, of course, that many decisions must be made.
Further, it will be appreciated that such development efforts are complex and time consuming, but routine work for one of ordinary skill in the art having the benefit of this disclosure.

Next, the present invention will be described with reference to FIGS. 1 to 9. Although various regions and structures of a semiconductor device are shown in the drawings as having extremely precise and sharp configurations and profiles, those skilled in the art will in fact see these regions and structures in the drawings. Admit it is not as precise. Moreover, the relative sizes of the various features shown in the figures may be expanded or reduced as compared to the feature sizes of the manufactured device. However, the attached drawings are included to describe and explain illustrative examples of the present invention.

In general, the present invention is directed to a process of forming source / drain regions in a semiconductor device. As will be readily apparent to those of ordinary skill in the art upon a thorough reading of this specification, this method may be implemented in a variety of techniques such as NMOS, PMOS, CMO.
It can be applied to S and the like, and can be easily applied to various elements including a logic element, a memory element, etc., but is not limited to this.

A partially formed semiconductor device 10 is shown in FIG. First, a shallow trench isolation 15 including, for example, silicon dioxide, is formed in the semiconductor substrate 12. The semiconductor device 10 includes a gate dielectric layer 14 formed on the surface 13 of the semiconductor substrate 12 and a gate electrode layer 16 formed on the gate dielectric layer 14. The semiconductor substrate 12 may include various materials, such as silicon with a layer of epitaxial silicon (not shown) formed thereon.

The materials that make up the gate dielectric layer 14 and the gate electrode layer 16 may vary as a matter of design choice. For example, gate dielectric layer 14 may include silicon dioxide and gate dielectric layer 16 may include polycrystalline silicon (polysilicon).
In addition, these layers are a variety of known techniques for forming such layers,
For example, thermal growth, chemical vapor deposition (“CVD”), physical vapor deposition (“PVD”).
, Plasma enhanced chemical vapor deposition (“PECVD”), sputtering and the like. Therefore, the manner in which the gate dielectric layer 14 and the gate electrode layer 16 are formed, in addition to the particular materials of construction, should not be considered limiting of the present invention, unless specifically stated in the appended claims. . In one embodiment, gate dielectric layer 14 comprises a layer of thermally grown silicon dioxide having a thickness in the range of approximately 15-30 Å (1.5-3 nm) and gate electrode layer 16 is a deposition process. Formed of about 1000-3000 liters (0.1-0.3 μm) of polysilicon.

Next, as shown in FIG. 2, the gate electrode layer 16 and the gate dielectric layer 14 are patterned to include the gate electrode 16 A and the gate dielectric 14 A.
7. This patterning may be accomplished by performing one or more etching processes, eg, anisotropic reactive ion etching processes. However, note that both the gate dielectric layer 14 and the gate electrode layer 16 need not be patterned at the same time. That is, the gate stack 17
May consist solely of the patterned gate electrode layer 16 for all or a substantial portion of the processing operations described herein.

Thereafter, as indicated by arrow 19, an ion implantation process is performed to form self-aligned, doped regions 20 in the substrate 12 for the exemplary NMOS device. This doped region 20 is approximately 200-1000 Å (0.02-0.1μ
It may have a thickness in the range m). The dopant atoms to be added by the implant process 19 may vary depending on the particular device in the configuration. For example, for the example NMOS device shown in FIG. 2, the dopant atoms may include arsenic or phosphorus. For PMOS devices, the dopant material may include boron or the like. In an exemplary implant process for an NMOS device, the ion implant process 19 is implanted at an energy in the range of about 1-10 keV, about 0.1-.
It contains 1.0 × 10 ¹⁵ / cm ² (pieces) of phosphorus ions.

Next, as shown in FIG. 3, a plurality of sidewall spacers 22 are formed adjacent to the side surfaces 23 of the gate stack 17. The sidewall spacers 22 result from the formation of a suitable layer of spacer material, such as silicon dioxide, silicon oxynitride, on the device shown in FIG. 3, followed by an anisotropic etching process. It may be configured to produce sidewall spacers 22. Note that although one sidewall spacer 22 is shown in FIG. 3, multiple sidewall spacers may be formed adjacent each side 23 of the gate stack 17.

Next, as shown in FIG. 4, a plurality of depressions 24 having a bottom surface 27 at a preselected depth 25 are formed in the substrate 12 adjacent or proximate to the gate stack 17. In the embodiment shown in FIG. 4, the recess 24 is formed outside the sidewall spacer 22. Of course, in situations in which multiple sidewall spacers are formed adjacent each side 23 of the gate stack 17, the recess 24 may be formed outside of the outermost sidewall spacers. The recess 24 may be formed by various techniques. For example, the recess 24 may be formed by performing an anisotropic reactive ion etching process. During this process, gate electrode 16A may be partially removed, as shown in FIG. The depth 25 of the recess 24 may vary as a matter of design choice. In one embodiment, the depth 25 of the recess 24 is about 500-1500Å (0.05-0.15 μm).
) Is the range. Note that during the process of forming the recess 24, some or all of the doped region 20 that extends beyond the sidewall spacer 22 may be removed.

Thereafter, as shown in FIG. 5, an implantation process 30 is performed to form a bottom surface 27 of the recess 24.
Dopant atoms are implanted therein, thereby forming a doped region 28 in the region defined by the recess 24. The doped region 28 is approximately 200-800Å
It may have a thickness in the range of (0.02-0.08 μm). In addition to the particular dopant atom selected, the concentration of that atom may vary as a design choice, depending on the particular technology involved. For example, for the exemplary NMOS device, the ion implantation process 30 may have an energy level of about 0.
The implantation may include 2-2.0 × 10 ¹⁴ / cm ² (pieces) of phosphorus ions.

As shown in FIG. 6, an epitaxial silicon region 32 is then formed in the recess 24 in the substrate 12 and on the gate electrode 16 A. Epitaxial silicon region 32 may be selectively formed such that epitaxial silicon is not formed on sidewall spacers 22 that include, for example, silicon dioxide. The thickness of the epitaxial region 32 may correspond approximately to the depth 25 of the recess 24.

Next, as shown in FIG. 7, another ion implantation process 38 is performed on the device to form a doped region 33 in at least a portion of the epitaxial silicon region 32 formed in the recess 24. Of course, the dopant atoms need not be limited to the epitaxial region 32 only. As with other ion implantation processes, the dopant material, concentration, and energy level of the implantation process may vary as a design choice. In one embodiment, the ion implantation process 38 may include about 1-5 × 10 ¹⁵ / cm ² arsenic ions and the energy level may be in the range of about 10-30 keV. This results in source / drain regions 3 including doped regions 33, doped regions 28, and doped regions 20, as FIG. 7 shows.
1 occurs. Although an example of a process flow for forming a source / drain region including three doped regions using three separate ion implantation processes has been described herein, the present invention has few ion implantation steps. , And / or may be used in a process flow with less doped regions.

A heat treatment or anneal process is then performed to activate the dopant atoms in the various doped regions 20, 28 and 33 to repair any damage to the silicon lattice structure due to the various ion implantation processes described above. After this anneal process is performed, the dopant atoms in doped regions 20, 28 and 33 are driven or moved. The resulting structure is generally shown in FIG. For example, as a result of the anneal process, some of the remaining portion of doped region 20 is driven slightly below side 23 of gate stack 17. In addition, some of the doped regions 33 are
You may be driven under 2. This heat treatment may be performed by various techniques, such as a rapid thermal anneal process. In one embodiment, the heat treatment is about 9
Including a rapid thermal anneal (“RTA”) process at a temperature in the range of 00-1200 ° C. for a time in the range of about 10-30 seconds. Of course, the above-mentioned one-time RTA
Instead of performing the process, multiple annealing steps may be performed at various stages of the manufacturing process.

Next, as shown in FIGS. 8 and 9, a conventional salicide process is performed to form a metal silicide region on the element shown in FIG. More specifically, as shown in FIG. 8, a layer 60 of refractory metal is formed on the device. Refractory metal layer 60 may include various refractory metals such as cobalt, titanium, etc.
For example, it may be formed by deposition. In one embodiment, the refractory metal layer 60 is
It contains about 100 liters of cobalt formed by the deposition process. After that, the conventional salicide treatment is performed, and the refractory metal layer 60 is covered with the source / drain regions 31.
It is converted into a metal silicide region 61 formed above and a metal silicide region 62 formed above the gate electrode 16A. The metal silicide regions 61 and 62 provide better electrical contact with the source / drain regions 33 and the gate electrode 16A.

The particular embodiments disclosed above are illustrative only, and the invention can be modified and practiced in different, but equivalent, manners that will be apparent to those of ordinary skill in the art who have the benefit of this teaching. Furthermore, no limitations are intended to the details of construction or design herein shown, other than as described in the claims below. It is therefore evident that the particular embodiments disclosed above may be altered or modified and all such variations are considered within the scope and spirit of the invention. Accordingly, the protection sought herein is as set forth in the claims below.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a partially formed semiconductor device.

FIG. 2 is a diagram showing a patterning operation performed on the device of FIG. 1 to define a gate stack on a semiconductor substrate.

FIG. 3 is a cross-sectional view showing that a sidewall spacer is formed adjacent to the gate stack in the device shown in FIG.

FIG. 4 is a cross-sectional view showing that the device shown in FIG. 3 is formed with a recess adjacent to a sidewall spacer in a substrate.

5 is a cross-sectional view showing that the device shown in FIG. 4 was subjected to an ion implantation process to form a doped region in a region defined by a depression.

6 is a cross-sectional view showing that a plurality of epitaxial silicon regions are formed on the device shown in FIG.

7 is a cross-sectional view showing that an ion implantation process is performed on the device shown in FIG.

8 is a cross-sectional view showing that a layer of refractory metal is formed on the device shown in FIG.

9 is a cross-sectional view showing that a portion of the refractory metal layer of the device shown in FIG. 8 has been converted into a metal silicide region.

[Procedure for Amendment] Submission for translation of Article 34 Amendment of Patent Cooperation Treaty

[Submission date] June 10, 2002 (2002.10)

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be amended] Claims

[Correction method] Change

[Contents of correction]

[Claims]

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Claims (17)

[Claims] 1. A method of forming source / drain regions 31 in a semiconductor device comprising the step of forming a gate stack 17 on a surface of a semiconductor substrate 12, said gate stack 17 having a plurality of sidewalls 23. The method further includes forming a recess 24 in the substrate 12 adjacent the gate stack 17, the recess 24 having a bottom surface 27, and the method further comprising a bottom surface 27 of the recess 24. Performing a first ion implantation process 30 therein to form a first doped region 28; forming a layer of epitaxial silicon 32 within the recess 24; and a second ion implantation process 38. And forming a second doped region 33 in at least a portion of the epitaxial silicon 32 formed in the recess 24. Steps and, and a step of annealing said first and second doped regions, how. 2. At least one sidewall spacer 22 is provided on the gate stack 1.
The method of claim 1, further comprising forming adjacent to the sidewall 23 of 7. 3. The substrate 1 prior to forming the recess 24 in the substrate 12.
Further comprising forming a third doped region 20 in the second
The method of claim 1, wherein a portion of the doped region 20 of is removed by the formation of the recess 24. 4. The step of forming a gate stack 17 on the surface of the semiconductor substrate 12 includes the step of forming a gate stack 17 including a layer of patterned polysilicon on the semiconductor substrate, the gate stack 17 comprising a plurality of gate stacks. Side wall 2
The method of claim 1, having 3. 5. The substrate 1 prior to forming the recess 24 in the substrate 12.
Forming a third doped region 20 in the substrate ² before forming the depressions 24 in the substrate 12 may include about 0.1-1.0 × 10 ¹⁵ / cm ² ions. A third ion implantation process 19 is performed at a dopant concentration in the range of 1 to 10 keV and an energy level in the range of about 1-10 keV to form a third doped region 20 in the substrate 12. The method described. 6. The step of forming a recess 24 in the substrate 12 adjacent the gate stack 17 and having a bottom surface 27 comprises the step of forming a recess in the substrate 12 adjacent the gate stack 17 and having a bottom surface 27. The method of claim 1 including the step of etching 24. 7. A first ion implantation process 30 within the bottom surface 27 of the recess 24.
And forming the first doped region 28 includes about 0.2-2.
Dopant concentration in the range of 0 × 10 ¹⁴ / cm ² ions and about 5-15 k
The method of claim 1 including the step of performing a first ion implantation process in the bottom surface 27 of the recess 24 to form a first doped region 28 at an energy level in the range of eV. 8. The method of claim 1, wherein the step of forming a layer of epitaxial silicon 32 in the recess 24 comprises depositing a layer of epitaxial silicon 32 in the recess 24. 9. The step of performing a second ion implantation process 38 to form a second doped region 33 in at least a portion of the epitaxial silicon 32 formed in the recess 24 is about 1-5. A second ion implantation process 38 was performed with a dopant concentration in the range of 10 ¹⁵ ions / cm ² (ions) and an energy level in the range of about 10-30 keV to remove the epitaxial silicon 32 formed in the recess 24. The method of claim 1, comprising forming a second doped region 33 within at least a portion. 10. Annealing the first and second doped regions 28, 33 includes performing one rapid thermal anneal process.
The method of claim 1. 11. The step of annealing the first and second doped regions 28, 33 comprises performing a plurality of rapid thermal anneal processes.
The method of claim 1. 12. The step of annealing the first and second doped regions 28, 33 comprises one rapid thermal anneal at a temperature in the range of about 900-1200 ° C. for a time in the range of about 10-30 seconds. The method of claim 1 including the step of performing a process. 13. A step of forming a gate stack 17 on a semiconductor substrate 12, said gate stack 17 having a plurality of sidewalls 23, and further performing a first ion implantation process 19 within said substrate 12. Forming a first doped region 20; forming at least one sidewall spacer 22 adjacent to the sidewall 23 of the gate stack 17; adjoining the gate stack 17 in the substrate 12. Forming a recess 24, the recess 24 having a bottom surface 27, and further performing a second ion implantation process 30 in the bottom surface 27 of the recess 24 to provide a second doped region 28. Forming a layer of epitaxial silicon 32 in at least the recess 24, and a third ion implantation Performing a process 38 to form a third doped region 33 in at least a portion of the epitaxial silicon 38 formed in the recess 24; and the first, second, and third doped regions 33. Annealing the region. 14. In the substrate 12, a first ion implantation process 19 is performed.
Forming the first doped region 20 at about 0.1-1.0 x 10 ¹⁵ / Cm²Dopant concentration in the range of (number of) ions and a range of about 1-10 keV.
Performing a first ion implantation process 19 at an energy level of
14. The method of claim 13 including forming a first doped region 20 therein.
the method of. 15. A second ion implantation process 3 in the bottom surface 27 of the recess 24.
0 to form the second doped region 28 is about 0.2-2.
． Dopant concentration in the range of 0 × 10 ¹⁴ / cm ² ions and about 5-15
14. The method of claim 13 including the step of performing a second ion implantation process 30 in the bottom surface 27 of the recess 24 to form a second doped region 28 at an energy level in the keV range. 16. The step of performing a third ion implantation process 38 to form a third doped region 33 in at least a portion of the epitaxial silicon 32 formed in the recess 24 is about 1-5. A third ion implantation process 38 is performed with a dopant concentration in the range of 10 ¹⁵ ions / cm ² (ions) and an energy level in the range of about 10-30 keV to remove the epitaxial silicon 32 formed in the recess 24. Third doped region 33 at least in part
15. The method of claim 14 including the step of forming. 17. The step of annealing the first, second, and third doped regions comprises a rapid thermal process at a temperature in the range of about 900-1200 ° C. for a time in the range of about 10-30 seconds. 15. The method of claim 14 including the step of performing an annealing process.