JPS62245465A - Long packet transmitter receiver - Google Patents

Abstract

PURPOSE:To expand the memory space of transmit and receive data and to transmit and receive a long packet with indeterminate length b providing plural external address registers on the output side of a DMAC. CONSTITUTION:The plural external address registers 11-14 are provided between the output side of the direct memory access controller (DMAC) and an address bus. Each address table 21 is provided with four counters for controlling the table and those counters indicate UDB (user data block) address to be accessed by purposes. Consequently, the address space is expanded and the plural address registers, i.e. fixed-length buffers are chained and used to utilize a memory for transmit and receive data effectively.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transmitting/receiving device, and particularly to a long packet transmitting/receiving device suitable for transmitting and receiving long packets.

[Conventional technology]

Figure 6 shows, for example, the magazine "1 Transistor Technology" 1985.
FIG. 1 is a hardware (hereinafter abbreviated as H/W) configuration diagram of a conventional data transmitting/receiving device shown in November (CQ Publishing).

In the figure, 1 is a CPU, 2 is a direct memory access control device ([)irect Memory Ac
cessController (hereinafter abbreviated as DMAC), 3 is a multi-protocol serial control device (M
ulti-Pr.

tocol @ 5erial (”ontrolle
r, hereinafter abbreviated as NPSC), 4 is transmission data, 5
is the received data, and 6.7 is the data line. Further, 8 is an address bus, 9 is a data bus, and 10 is an interrupt controller.

Next, the operation will be explained. First, the transmission data 4 and the reception data 5 are stored in a memory area within this system, and the DMAC 2 directly accesses this memory area to send the transmission data 4 to another system. Data 5 is stored in this memory area. The MPSC 3 converts the protocol of serial data sent onto the data line 7 from another system to this system, and passes it to the DMAC 2 as data that can be accessed by this system. Then, DMAC'2 stores this passed data in a memory area within the system as received data 5. DMAC2 directly accesses the transmission data 4 according to instructions from CPU1 and transmits it to tMPsc3.
give it to MPSC3 converts this data into serial data.

It is sent onto the data line 7. However, for convenience of explanation, data lines 6 and 7 are shown separately; however, these may be the same transmission line used for transmission and reception in a time-sharing manner; The data line 6 and the receiving data line 7 are paired together and called one data line.

In FIG. 6, DMAC2 and MPSC3 are DMAC
Each of the same LSIs 1 has two devices each having a function as an MPSC and a function as an MPSC, and these are called devices for two tube channels. CPLll is DMAC2
and MPS C3 control, but 2 channel DMA
C function, that is, controls channel 1 and channel 2 to enable data transmission and reception. 2 channels of DMAC and 2 channels of MPS on 1 data line
If equipped with a C3 pipe, simultaneous transmission and reception will be possible by separating the data line and receiving and receiving money.

[Problem that the invention seeks to solve]

Conventional long packet transmitting/receiving devices are configured as described above, so when you want to further expand the DMAC address space, or after transmitting/receiving data of undefined length (1 to long packet length), If you want to use it as effectively as possible, there are six problems, such as limited memory capacity.

This invention was made in order to solve the problems mentioned above, and is a direct memory access control device.
Address space expansion is handled by providing multiple external address registers between the (DMAC) output and the address bus, and by subdividing the data buffer for sending and receiving long packet data. ◇ [Means for solving the problems] The long packet transmitting and receiving device according to the present invention first has a hardware configuration in which output from a DMAC is obtained. The address to be sent is extended by an external circuit of an external address register, and data buffers are segmented to enable transmission and reception using the plurality of buffers according to the length of the data to be transmitted and received.

[For production]

The long packet transmitting/receiving device in this invention is a DMAC
The address space is expanded by providing a plurality of external address registers on the output side, and by chaining and using the plurality of address registers and a large number of fixed-length buffers, effective use of the memory for transmitting and receiving data is achieved.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, the same parts as in FIG. 6 are indicated by the same reference numerals. In FIG. 1, 11 to 14 are external address registers (measurement length buffer) RO% R5. Next, the operation will be explained. First, FIG. 2 is a format diagram showing an example of a UDB (user data block) address table for transmitting and receiving buffer management used in the present invention, where 22 is the UDB address, 21 is the UDB
It is a friend table that collects 22tM addresses, and is tentatively called a chain control management table (hereinafter simply abbreviated as table).
The table 21 is provided for each channel of the DMAC 2, and as shown in FIG.
Since there are two ACs, four tables 21 are provided.

Each table 21 is provided with four counters for managing all of the tables, each of which has the following counters:
The UDB address 22 to be accessed for each purpose is shown. That is, individually V-8TART, V-DMA, V-C
”UT, V-USED.
-8TART is the beginning of the sending/receiving data, register R8~
, (10 to 13) to indicate the UDB address 22, V-DMA is the DMAC2 of that channel.
tJDB (user data,
V-CUT is a friend counter that prevents the buffer chain from running out of control.If the sent/received data is within N7777 minutes, V-CUT=V-8TART.
It may be set as +(N-1) (modM).

When this address is reached, all the requested data transfers will be completed and no buffer chain operation will be possible from now on. A user·
A counter indicating that the data block (data block) has already been transferred indicates that these UDBs may be unprocessed in the system. This means that you should not accidentally sect this UDB address again and rewrite the unprocessed data.

When supplying new send/receive buffers, the UDB here
Just set it to the address and count up the V-USED value by 1. V-USED=V-USED
+ 1 (mod M).

Next, interrupts between MPSC3 and DMA C2 will be explained using an example of reception operation. Figure 3 shows MPSC3 to CPU1
This is a flowchart showing the processing at 9 o'clock when an interrupt is entered. In the figure, 300 to 311 indicate each step. Step 301 determines whether the DMA (?2) has completed the TC (meaning the end of one UDB transfer operation), and selects YES.
If so, set the flag in step 302 and DMAC2
(This flag indicates that there is a possibility that an interrupt may occur.) If the answer is No, the process moves to step 303. M.P.
Since the S C3 has an error checking function, there is no need to store data in which an error has been detected in the reception buffer. -8TARTt
After returning to V-DMA, the determination in step 303 is YES.
If so, step 305 is entered. Note that if there is one remaining 9 in the transmission/reception buffer, the answer to step 303 is No. In step 305, V-DMA+1 @V-8TA
RT and V-DMA, and in step 306 V-DMA
+N, l! : V-USED and t comparison 2, V-DMA+
If N is smaller than V-USED, it means that there is room in the receive buffer and it is possible to chain N UDBs consecutively (ready), so in step 308 V-8TAR is sent.
Let T+(N-1)eV-CUT. Ma7tV-DMA
If +N is greater than or equal to V-USED, move to (busy) stick 307 and 5v-8TART+11jv-CUT (!
: Chain only one UDB. Next step 30
9, the UDB address register R indicated by V-8TART
Write in 8～. Then, in step 310, the DMAC
The process is reset to a state where the 2tl reception buffer length can be transferred and ends. Such processing is performed for the OCT and each counter for each channel.

In the example shown in FIG. 3, it is determined in step 306 that long packets up to a maximum of N buffers can be received when ready.
During a busy period, frames are received up to one buffer, and when there is only one buffer remaining, no reception processing is performed.

Figure 4 is a flowchart showing the processing when there is a TC end interrupt from DMAC'2 to C'PUI.
0 to 405 indicate each step, step 30 in FIG.
If the flag set in step 2 exists, the 7 lag is reset in step 405.

If V-DMA"FV-CtJT and the flag are not set, the V-DMAI value is incremented by 1 in step 403. Then, in step 404, the V-DMAI value is incremented by 1.
Write to A's UDB address gold register Ro~.

Also, Figure 5 shows the data format for interfacing with other software packages, and each user data block (UDB) has a package interface block (p I B ),
interface by adding a header (buffer chaining method). That is, the value of the chain code of the package interface block (PIB) indicates whether or not the buffer chain has ended.

For example, the chain code x'oo' indicates the end of the chain; Of the N buffers up to V-CUT, which is the counter that suppresses the value, the buffers from V-8TART to the accessed counter V-DMA are notified, and the buffers from V-DMA+1 to v-CUTE are reused. Tsumashi,
Set V5TART←V-DMA+1.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of external address register tubes are provided on the output side of the DMAC.
Since the memory space for transmitting and receiving data is expanded, long buckets of undefined length can be transmitted and received at high speed, and an inexpensive 87W configuration that is efficient in terms of memory capacity can be achieved.

[Brief Description of the Drawings] Fig. 1 is a hardware configuration diagram showing an embodiment of the invention;
Figure 2 is an explanatory diagram of a table for setting UDB addresses for transmitting and receiving buffer management, Figure 3 is an explanatory flowchart for managing the table in Figure 2, and Figure 4 is an explanatory diagram of a table for setting UDB addresses for transmitting and receiving buffer management.
UDB) 70-chart for table management at the end of use, FIG. 5 shows a data format diagram for interfacing with other software packages, and FIG. 6 shows a conventional hardware configuration diagram. In the figure, 1 is a CPU, 2 is a direct φ memory access controller (DMAC), 3 is a multi-protocol serial controller (MPSC), 6 and 7 are transmit/receive data, 8 is an address bus, and 11 to 14a external It is an address register. Figure 3 Figure 5 S "vfu!" U]

Claims (1)

[Claims] In a long packet transmitting/receiving device that transmits and receives serial data by controlling a multiprotocol serial controller and a direct memory access controller by a CPU, there is a connection between the output side of the direct memory access controller and an address bus. A feature is that by providing multiple external address registers in between and expanding the address space of the direct memory access controller, long packets can be divided into multiple transmit/receive buffers and transferred within the system. A long packet transmitting/receiving device.