JPS62242366A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62242366A JPS62242366A JP8575286A JP8575286A JPS62242366A JP S62242366 A JPS62242366 A JP S62242366A JP 8575286 A JP8575286 A JP 8575286A JP 8575286 A JP8575286 A JP 8575286A JP S62242366 A JPS62242366 A JP S62242366A
- Authority
- JP
- Japan
- Prior art keywords
- gate electrode
- drain
- source
- oxide film
- face
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims description 7
- 230000015556 catabolic process Effects 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000010354 integration Effects 0.000 description 3
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はＭＯＳトランジスタに関し、特に、ソースおよ
びドレインがゲート酸化膜を介してゲート電極と重なる
ようにくい込んでも特性劣化が生じないようにした半導
体装置に関する。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a MOS transistor, and in particular to a semiconductor whose characteristics do not deteriorate even when the source and drain are buried so that they overlap with the gate electrode through a gate oxide film. Regarding equipment.
従来のＭＯＳトランジスタとして、例えば、第３図に示
すものがある。このＭＯ３Ｉ−ランジスタは、基板１３
上にソースおよびドレイン１４が形成されており、ゲー
ト酸化膜１２にゲート電極１１が位置してトランジスタ
素子を構成しており、各トランジスタ素子を分離するた
めに素子分離領域１６が形成されている。As a conventional MOS transistor, there is one shown in FIG. 3, for example. This MO3I-transistor has a substrate 13
A source and a drain 14 are formed thereon, a gate electrode 11 is located on the gate oxide film 12 to constitute a transistor element, and an element isolation region 16 is formed to isolate each transistor element.
このＭＯＳトランジスタによれば、微細加工を行ってゲ
ート電極１１を細くしてＬＳＩの高性能化および高集積
化を図っている。According to this MOS transistor, fine processing is performed to make the gate electrode 11 thinner, thereby achieving higher performance and higher integration of the LSI.
しかし、従来のＭＯＳトランジスタによれば、ゲート電
極での自己整合によりソースおよびドレイを形成すると
、第３図に示すように、その深さＤを大きくして電気抵
抗の低減を図ろうとすると、ゲート電極へのくい込み量
Ｐが大きくなるため、ゲート電極とソースおよびドレイ
ン間の容量が増加して性能低下を招き、かつ、ソ−スお
よびドレイン間の間隔が小さくなって耐圧が低下すると
いう不都合がある。この間隔が小さくなるということは
、実効ゲート幅が小さくなることであり、前述の高集積
化と相俟ってますますゲート電極が細くなることになる
。However, according to the conventional MOS transistor, if the source and drain are formed by self-alignment at the gate electrode, as shown in FIG. 3, if the depth D is increased to reduce the electrical resistance, the gate electrode Since the penetration amount P into the electrode increases, the capacitance between the gate electrode and the source and drain increases, leading to a decrease in performance, and the distance between the source and drain decreases, resulting in a decrease in breakdown voltage. be. When this interval becomes smaller, the effective gate width becomes smaller, and together with the above-mentioned higher integration, the gate electrode becomes thinner and thinner.
本発明は上記に鑑みてなされたものであり、ソースおよ
びドレインを所定の深さに形成した場合でもゲート電極
へのくい込みを抑えて性能および耐圧の低下を防ぐため
、ゲート電極のゲート酸化膜と対面し、かつ、ソースお
よびドレインと重なる部分を酸化膜で構成し、ゲート電
極での自己整合によってソースおよびドレインを形成す
るための幅を大にできるようにした半導体装置を提供す
るものである。The present invention has been made in view of the above, and in order to prevent the source and drain from digging into the gate electrode and to prevent the performance and breakdown voltage from deteriorating even when the source and drain are formed to a predetermined depth, the gate oxide film of the gate electrode is The object of the present invention is to provide a semiconductor device in which the portions facing each other and overlapping with the source and drain are made of an oxide film, and the width for forming the source and drain can be increased by self-alignment at the gate electrode.
以下、本発明の半導体装置を詳細に説明する。Hereinafter, the semiconductor device of the present invention will be explained in detail.
第１図は本発明の一実施例を示し、第３図と同一の部分
は同一の引用数字で示したので重複する説明は省略する
が、ゲート１１はゲート酸化膜１２と対面し、かつ、ソ
ースおよびドレイン１４の端部に重なる部分を酸化膜１
５で構成されている。FIG. 1 shows an embodiment of the present invention, and the same parts as in FIG. 3 are indicated by the same reference numerals, so redundant explanation will be omitted, but the gate 11 faces the gate oxide film 12, and An oxide film 1 is formed on the portions overlapping the ends of the source and drain 14.
It consists of 5.
第２図はゲーＩ・電極１１の部分を拡大して示したもの
で、ゲート電極１１は、ゲート酸化膜１２と対面する反
対側に幅Ｚの面と、ゲート酸化膜１２と対面する側に幅
Ｙの面を有し、更に、・ゲート酸化膜１２と対面し、か
つ、ソースおよびドレイン１４と重なる部分Ｘを酸化膜
１５で構成されている。FIG. 2 is an enlarged view of the gate I electrode 11. The gate electrode 11 has a width Z on the opposite side facing the gate oxide film 12, and a side with a width Z on the side facing the gate oxide film 12. It has a surface with a width Y, and a portion X that faces the gate oxide film 12 and overlaps with the source and drain 14 is made of an oxide film 15.
第２図より明らかなように、Ｚ＝Ｙ＋２Ｘとなり、ｘ、
ｙ、ｚΦ値はＭＯＳトランジスタの性能に合わせて設定
されれば良い。As is clear from Figure 2, Z=Y+2X, and x,
The y and zΦ values may be set according to the performance of the MOS transistor.
本発明のＭＯ３Ｉ−ランジスタは上述した構成を有する
ため、ゲート電極工１の実効幅はＹとなるのに対し、ゲ
ート電極１１での自己整合によって形成されるソースお
よびドレイン１４に対しては、幅Ｚの面が有効に作用す
るため、前述の深さＤを大にすることができる。従って
、深さＤを所定の値にとったとき、ソースおよびドレイ
ン１４とゲート電極１１との間には酸化膜１５が位置す
るため、容量の増加はなく、また、ソースおよびドレイ
ン１４の間隔は幅Ｚの面によってそれほど短縮すること
がないため、耐圧低下は生じない。一方、高集積化に対
しては、幅Ｙの面が効いてくるので、それを阻害するこ
とはない。Since the MO3I-transistor of the present invention has the above-described configuration, the effective width of the gate electrode 1 is Y, whereas the width of the source and drain 14 formed by self-alignment in the gate electrode 11 is Y. Since the Z plane acts effectively, the aforementioned depth D can be increased. Therefore, when the depth D is set to a predetermined value, the oxide film 15 is located between the source and drain 14 and the gate electrode 11, so there is no increase in capacitance, and the distance between the source and drain 14 is Since the width Z is not so shortened by the plane, no reduction in breakdown voltage occurs. On the other hand, since the width Y is effective for high integration, it does not hinder this.
以上説明した通り、本発明の半導体装置によれば、ゲー
ト電極のゲート酸化膜と対面し、かつ、ソースおよびド
レインと重なる部分を酸化膜で構成したため、ゲート電
極での自己整合によってソースおよびドレインを形成す
る実効幅を大にでき、ソースおよびドレインを所定の深
さに形成した場合でもゲート電極へのくい込みを抑えて
性能および耐圧の低下を防ぐことができる。As explained above, according to the semiconductor device of the present invention, since the portion of the gate electrode that faces the gate oxide film and overlaps with the source and drain is composed of an oxide film, the source and drain can be separated by self-alignment at the gate electrode. The effective width to be formed can be increased, and even when the source and drain are formed to a predetermined depth, digging into the gate electrode can be suppressed, thereby preventing a decrease in performance and breakdown voltage.
第１図は本発明の一実施例を示す断面図。第２図は第１
図の要部拡大図。第３図は従来の半導体装置を示す断面
図。
符号の説明FIG. 1 is a sectional view showing one embodiment of the present invention. Figure 2 is the first
Enlarged view of the main part of the figure. FIG. 3 is a sectional view showing a conventional semiconductor device. Explanation of symbols
Claims (1)
ート酸化膜を介して形成されたソースおよびドレインを
有したＭＯＳトランジスタにおいて、 前記ゲート電極は、前記ゲート酸化膜と対面し、かつ、
前記ソースおよびドレインと重なる部分を酸化膜で構成
したことを特徴とする半導体装置。[Claims] A MOS transistor having a source and a drain formed on both sides of a gate electrode located on a surface of a gate oxide film with the gate oxide film interposed therebetween, wherein the gate electrode faces the gate oxide film. And,
A semiconductor device characterized in that a portion overlapping with the source and drain is formed of an oxide film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8575286A JPS62242366A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8575286A JPS62242366A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242366A true JPS62242366A (en) | 1987-10-22 |
Family
ID=13867587
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8575286A Pending JPS62242366A (en) | 1986-04-14 | 1986-04-14 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242366A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834817A (en) * | 1988-09-08 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with a shaped gate electrode |
-
1986
- 1986-04-14 JP JP8575286A patent/JPS62242366A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5834817A (en) * | 1988-09-08 | 1998-11-10 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with a shaped gate electrode |
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