JPS62242262A - Computer system - Google Patents
Computer systemInfo
- Publication number
- JPS62242262A JPS62242262A JP8635886A JP8635886A JPS62242262A JP S62242262 A JPS62242262 A JP S62242262A JP 8635886 A JP8635886 A JP 8635886A JP 8635886 A JP8635886 A JP 8635886A JP S62242262 A JPS62242262 A JP S62242262A
- Authority
- JP
- Japan
- Prior art keywords
- input
- cpu
- ioc
- computer system
- output control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 235000010678 Paulownia tomentosa Nutrition 0.000 description 1
- 240000002834 Paulownia tomentosa Species 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、複数の中央処理装置（以下ＣＰＵと呼ぶ）
が共通の入出力装置に対して制御を行なう計算機システ
ムに関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention is directed to a plurality of central processing units (hereinafter referred to as CPUs).
This relates to a computer system that controls common input/output devices.
第２図は従来の入出力装置が共用される計算機システム
の構成を示す図であり、図においてｌは１台目のＣＰＵ
、２は２台目のＣＰＵ、３．４は夫々１合口のＣＰＵに
内蔵された第１．第２人出力制御装置（以下ｒｏｃとい
う）、５．６は２台目のＣＰＵに内蔵されたＩＯＣ，７
はＩＯＣとそれに接続される入出力装置（以下ＩＯとい
う）８゜９間のケーブルを切り換える入出力装置共用装
置（以下１０共用装置という）である。Figure 2 is a diagram showing the configuration of a conventional computer system in which input/output devices are shared;
, 2 is the second CPU, and 3.4 is the first CPU built in each CPU. 2nd person output control device (hereinafter referred to as ROC), 5.6 is an IOC built in the second CPU, 7
is an input/output device shared device (hereinafter referred to as 10 shared device) that switches the cable between the IOC and the input/output devices (hereinafter referred to as IO) 8.9 connected thereto.
次に動作について説明する。１台目のＣＰＵＩに内蔵さ
れたｌ０Ｃ３，ｌ０Ｃ４がそれぞれの制プル内信号群を
接続する。このときの切換制御を行なう■０共用装置７
はリレー、電子リレー、あるいはコネクタ等により実施
する。２台目のＣＰＵ２に内蔵されたＩＯ５，ＩＯ６が
そのそれぞれの制御対象となる入出力装置１０８，１０
９と接続したいときも上記と同様な動作で接続する。Next, the operation will be explained. l0C3 and l0C4 built into the first CPUI connect the respective control pull signal groups. ■0 shared device 7 that performs switching control at this time
is implemented by relays, electronic relays, connectors, etc. IO5 and IO6 built into the second CPU 2 are input/output devices 108 and 10 to be controlled respectively.
If you want to connect to 9, connect using the same operation as above.
以下、複数金目のＣＰＵも上述と同様な動作で接続する
。Thereafter, multiple CPUs are connected in the same manner as described above.
従来の入出力装置共用装置７は以上のように構成されて
いるので、複数のＣＰＵ内にＩＯＣを内蔵しなければな
らず不経済であるという問題点があった。この発明は上
記のような問題点を解消するためになされたもので、複
数のＣＰＵに対して１つのＩＯＣ″″？！ｒｏを共用で
きる計算機システムを得ることを目的とする。Since the conventional input/output device sharing device 7 is configured as described above, there is a problem in that the IOC must be built into a plurality of CPUs, which is uneconomical. This invention was made to solve the above-mentioned problems. One IOC"" for multiple CPUs? ! The purpose of this invention is to obtain a computer system that can share ro.
この発明に係る計算機システムは制御対象と′なる１０
（入出力装置）８．９に対応してｌ０Ｃ（入出力制御装
置り１１．１２を夫々設け、上記各１０ＣＩＩ、１２を
複数のＣＰＵＩ、２から共用可能に選択接続する切換手
段７０を備えたものである。The computer system according to the present invention has 10 objects to be controlled.
(Input/output device) 10C (input/output control device 11.12) was provided corresponding to 8.9, and a switching means 70 was provided for selectively connecting each of the above 10CII and 12 to a plurality of CPUIs and 2 so that they could be shared. It is something.
切換手段７０は、１０８．９を制御するｌ０Ｃ１１，１
２が複数のＣＰＵＩ、２から共用可能となるよう切換え
る。このため、複数のＣＰＵＩ。The switching means 70 controls the l0C11,1
2 is switched so that it can be shared by multiple CPUIs. For this reason, multiple CPUIs.
２内に夫々ｌ０ＣＩＩ、１２を設けることがなくハード
ウェア構成の経済化が図れる。It is not necessary to provide 10CII and 12 in 2, so that the hardware configuration can be made more economical.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図において、１は１台目のＣＰＵ、２は２台目のＣ
ＰＵ、７０は入出力装置■０共用装置（切換手段）、８
．９はＩＯＣに接続される１０゜１１．１２は上記ＩＯ
共用装置７０に内蔵された１０Ｃである。In Figure 1, 1 is the first CPU, 2 is the second CPU
PU, 70 is input/output device■0 Shared device (switching means), 8
．． 9 is connected to IOC 10° 11.12 is the above IO
10C built into the shared device 70.
このような構成からなる本発明の計算機システムにおい
ては、１台目のＣＰＵＩに１０８，１０９を接続すると
きそれぞれのｌ０Ｃ１１，ｌ０Ｃ１２のＣＰＵとの接続
バスをＴｏ共用装置７０により、１台目のＣＰＵＩのバ
スに接続する。このときの切換制御はリレー、電子リレ
ー、あるいはコネクタ等などの切換素子からなる■０共
用装置で行なう。２台目（７）ＣＰＵ２に１０８，１０
９を接続するとき、ｌ０ＣＩＩ、ｌ０Ｃ１２とＣＰＵ間
の接続バスをｉｏ共用装置の切換えにより２台目のＣＰ
Ｕ２のバスに接続する以降、複数金目のＣＰＵも上述と
同様な動作で選択的に接続する。In the computer system of the present invention having such a configuration, when connecting the CPUs 108 and 109 to the first CPU, the To sharing device 70 connects the connection buses with the CPUs of the respective l0C11 and l0C12 to the first CPU connect to the bus. Switching control at this time is performed by a shared device consisting of switching elements such as relays, electronic relays, or connectors. 2nd unit (7) 108,10 for CPU2
9, the connection bus between l0CII, l0C12 and the CPU can be connected to the second CPU by switching the IO shared device.
After connecting to the U2 bus, multiple CPUs are also selectively connected in the same manner as described above.
なお、上記実施例ではｒＯｃ、ｌ０ＣＩＩ。In addition, in the above example, rOc and l0CII.
１２をＣＰＵ１．２外に設けて構成したが、１０Ｃ，ｌ
０Ｃ１１，１２がＣＰＵＩ、２に固定的に内蔵されてい
る場合、それらＩＯＣを他のＣＰＵから共用して選択的
に接続するよう構成しても良く、上記実施例と同様の効
果を奏する。12 was provided outside the CPU 1.2, but 10C,l
When the 0Cs 11 and 12 are fixedly built into the CPUs 2, the IOCs may be shared by other CPUs and connected selectively, and the same effects as in the above embodiment can be obtained.
以上のようにこの発明によれば、複数のＣＰＵ（中央処
理装置）からｌ０Ｃ（入出力制御装置）を共用できるよ
う構成したので、従来複数のＣＰＵに対応するＩＯＣが
１装置で構成できるためシステム全体が安価となり、ま
たＩＯＣの減少による信頼性の向上が図れるという効果
がある。As described above, according to the present invention, the IOC (input/output control unit) can be shared by multiple CPUs (central processing units). The overall cost is reduced, and the reliability can be improved by reducing the number of IOCs.
第１図はこの発明の一実施例による計算機システムを示
す構成図、第２図は従来の計算機システムを示す構成図
である。
１．２・・・ＣＰＵ （中央処理装置）、７０・・・Ｉ
Ｏ共用装置（切換手段）、８．９・・・１０．１０（入
出力装置）、１１．１２・・・ｒＯｃ、ＩＯＣ（入出力
制御装置）。
なお、図中同一符号は同一または相当部分を示す。
代理人 大 岩 増 雄（ばか２名）第 １
図
１ ； ＣＰｔＪ （甲天見狸装置）
２；１０共周攻置（切１文九手股）
８１９； １０． ｔｏ （入７７１ｉ’り１’ｌ、＋
２； ＩＯＣ，工Ｏｃ（入ｅビ１力缶り−ｑｖｘ ）
＠２図
手続補正書（０如
昭和 年 月 日
１、事件の表示 特願昭６１−８６３５８号
圃２、発明の名称
計算機システム
３、補正をする者
事件との関係 特許出願人
住 所 東京都千代田区丸の内二丁目２番３号名
称 （６０１）三菱電機株式会社代表者志岐守哉
４、代理人
、１
５、補正の対象
発明の詳細な説明の欄。
６、補正の内容
（１）明細書第５頁第３行目乃至第８行目「なお、・−
・−−−−−・効果を奏する。」とあるのを削除する。
以上FIG. 1 is a block diagram showing a computer system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional computer system. 1.2...CPU (central processing unit), 70...I
O shared device (switching means), 8.9...10.10 (input/output device), 11.12...rOc, IOC (input/output control device). Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 idiots) 1st
Figure 1; CPtJ (Kotenmi tanuki device) 2; 10 co-surrounding attack (kiri 1 mon 9 hands) 819; 10. to (enter 771i'ri1'l, +
2; IOC, Engineering Oc (enter ebi 1 power canri-qvx)
@Diagram 2 Procedural Amendment (0 Showa Year, Month, Day 1, Case Indication Patent Application No. 86358, 1983)
Field 2, Invention name computer system 3, Relationship with the amended person case Patent applicant address 2-2-3 Marunouchi, Chiyoda-ku, Tokyo Name (601) Moriya Shiki 4, Representative of Mitsubishi Electric Corporation Agent, 15. Column for detailed explanation of the invention subject to amendment. 6. Contents of the amendment (1) Page 5 of the specification, lines 3 to 8, ``Please note...
・------・Produces an effect. ” will be deleted. that's all
Claims (1)
え、上記各入出力制御装置を夫々制御する複数の中央処
理装置から成る計算機システムにおいて、 上記入出力制御装置を入出力装置に対応して設け、上記
入出力制御装置に対して上記複数の中央処理装置を選択
的に接続して各中央処理ユニットから上記入出力制御装
置を共用可能とする切換手段を備えたことを特徴とする
計算機システム。[Scope of Claims] A computer system comprising a plurality of input/output control devices that control input/output devices, and a plurality of central processing units that respectively control each of the input/output control devices, A switching means is provided corresponding to the input/output device and selectively connects the plurality of central processing units to the input/output control device so that each central processing unit can share the input/output control device. A computer system characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8635886A JPS62242262A (en) | 1986-04-15 | 1986-04-15 | Computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8635886A JPS62242262A (en) | 1986-04-15 | 1986-04-15 | Computer system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62242262A true JPS62242262A (en) | 1987-10-22 |
Family
ID=13884667
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8635886A Pending JPS62242262A (en) | 1986-04-15 | 1986-04-15 | Computer system |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62242262A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4495829B2 (en) * | 1999-04-29 | 2010-07-07 | シーメンス ビルディング テクノロジーズ、インコーポレーテッド | Actuator with timer-controlled power switching device |
-
1986
- 1986-04-15 JP JP8635886A patent/JPS62242262A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4495829B2 (en) * | 1999-04-29 | 2010-07-07 | シーメンス ビルディング テクノロジーズ、インコーポレーテッド | Actuator with timer-controlled power switching device |
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