JPS62241352A - Package for ic - Google Patents
Package for icInfo
- Publication number
- JPS62241352A JPS62241352A JP61084720A JP8472086A JPS62241352A JP S62241352 A JPS62241352 A JP S62241352A JP 61084720 A JP61084720 A JP 61084720A JP 8472086 A JP8472086 A JP 8472086A JP S62241352 A JPS62241352 A JP S62241352A
- Authority
- JP
- Japan
- Prior art keywords
- marks
- package
- zips
- mark
- main body
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract description 5
- 238000000465 moulding Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54406—Marks applied to semiconductor devices or parts comprising alphanumeric information
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/544—Marks applied to semiconductor devices or parts
- H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
- H01L2223/54486—Located on package parts, e.g. encapsulation, leads, package substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明はプラスチックZIG ZAG INLINE
! PACKAGE (ジグ ジグ インライン パ
ッケージ)型集積回路(以下ZIPと称す)のパッケー
ジに関するものである。[Detailed Description of the Invention] [Industrial Application Field] This invention relates to plastic ZIG ZAG INLINE.
! This invention relates to a package for a PACKAGE (zig in-line package) type integrated circuit (hereinafter referred to as ZIP).
板上に高密度に実装した状態を表わした図である。FIG. 3 is a diagram showing a state in which the devices are mounted on a board with high density.
図において、1はIC本体(ZIP単体)、2はリード
部、3は型名等の識別を行うためのマーり、3aはマー
ク部5は実装用の基板、6は高密度に実装されたZIP
である。In the figure, 1 is the IC body (ZIP alone), 2 is the lead part, 3 is the mark for identifying the model name, etc. 3a is the mark part 5 is the board for mounting, 6 is the high-density mounting ZIP
It is.
このような従来のZIPでは型名等の識別を行うための
マークは、ZIP本体の側面にのみインクにより印刷さ
れていた。In such conventional ZIPs, marks for identifying the model name and the like are printed with ink only on the side surfaces of the ZIP body.
従来のZIPでは、本体側面にマークがあるために、第
2図のように、基板上にZIPが高密度に実装された場
合は、上部からのマークの識別が非常に困難であるとい
う問題点があった。Conventional ZIPs have marks on the side of the main body, so when ZIPs are densely mounted on a board as shown in Figure 2, it is very difficult to identify the marks from above. was there.
この発明は上記のような問題点を解消するためになされ
たもので、ZIPを高密度に実装した場合でも、マーク
の識別を容易に行うことができるICパッケージを得る
ことを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide an IC package in which marks can be easily identified even when ZIPs are densely mounted.
この発明に係るICパッケージは、その側面だけでなく
側面以外の面にもマークを形成したものである。The IC package according to the present invention has marks formed not only on its side surfaces but also on surfaces other than the side surfaces.
この発明においては、そのパッケージ本体の側面だけで
なく側面以外の面にもマークを形成したから、ZIPを
高密度に実装した場合にもZIPφマークの識別を容易
にできる。In this invention, since the mark is formed not only on the side surface of the package body but also on surfaces other than the side surface, the ZIPφ mark can be easily identified even when ZIPs are densely mounted.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図は本発明の一実施例によるICパッケージの外形
を示し、図において、1はIC本体、2はリード部、3
は側面のマーク部3aに形成されたマーク、4は側面以
外の面のマーク部4aに形成されたマークである。FIG. 1 shows the external shape of an IC package according to an embodiment of the present invention. In the figure, 1 is an IC main body, 2 is a lead part, and 3
4 is a mark formed on the mark portion 3a on the side surface, and 4 is a mark formed on the mark portion 4a on a surface other than the side surface.
このマーク4は、ICパッケージのモールド金型にIC
の型名等を凸面または凹面で作ることにより、パッケー
ジのモールド時に凹面または凸面のマークが作られる。This mark 4 is placed on the mold of the IC package.
By making the model name etc. on a convex or concave surface, a concave or convex mark is created when the package is molded.
このように本実施例ではマークがパッケージの本体側面
だけでなくそれ以外の面にも形成されているので、ZI
Pが基板上に高密度に実装された場合においても基板上
部からZIPのマークを容易に識別できる。In this way, in this example, the mark is formed not only on the side surface of the main body of the package but also on other surfaces, so that the ZI
Even when P is mounted on a board with high density, the ZIP mark can be easily identified from the top of the board.
なお上記実施例では、側面以外のマークをモールド金型
によって作る方法を示したが、これは従来通りのインク
による印刷や、レーザービームによる加工によって行っ
てもよい。In the above embodiment, a method for forming marks other than the side marks using a mold was shown, but this may be done by conventional ink printing or laser beam processing.
以上のように、この発明によれば、ZIPのマークを本
体側面及び該側面以外の面に形成したので、ZIPが基
板上に高密度に実装された場合においても基板上部から
ZIPのマークを容易に識別できるという効果がある。As described above, according to the present invention, the ZIP mark is formed on the side surface of the main body and on surfaces other than the side surface, so even when the ZIP is mounted on the board with high density, the ZIP mark can be easily marked from the top of the board. It has the effect of being able to be identified.
第1図はこの発明の一実施例によるZrPの外形図、第
2図は従来のZIPの外形及びZIPを基板上に高密度
に実装した状態を示す図である。
図において、lはIC本体、2はリード部、3は本体側
面のマーク、4は本体側面以外の面に作られたマーク、
3a、4aはマーク部である。
なお図中同一符号は同−又は相当部分を示す。FIG. 1 is an outline diagram of ZrP according to an embodiment of the present invention, and FIG. 2 is a diagram showing the outline of a conventional ZIP and a state in which the ZIP is densely mounted on a substrate. In the figure, l is the IC body, 2 is the lead part, 3 is a mark on the side of the main body, 4 is a mark made on a surface other than the side of the main body,
3a and 4a are mark parts. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
積回路のパッケージにおいて、上記パッケージの本体側
面及び該側面以外の面にマークを形成したことを特徴と
するICパッケージ。(1) An IC package of a plastic zigzag in-line package type integrated circuit, characterized in that a mark is formed on a side surface of the package body and on a surface other than the side surface.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61084720A JPS62241352A (en) | 1986-04-11 | 1986-04-11 | Package for ic |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61084720A JPS62241352A (en) | 1986-04-11 | 1986-04-11 | Package for ic |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62241352A true JPS62241352A (en) | 1987-10-22 |
Family
ID=13838515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61084720A Pending JPS62241352A (en) | 1986-04-11 | 1986-04-11 | Package for ic |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62241352A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS646050U (en) * | 1987-06-30 | 1989-01-13 |
-
1986
- 1986-04-11 JP JP61084720A patent/JPS62241352A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS646050U (en) * | 1987-06-30 | 1989-01-13 |
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