JPS62239244A - Instruction execution supervisory equipment - Google Patents

Abstract

PURPOSE:To shorten the time required for detecting abnormalities in terms of a device supervising the delay caused by a processor when it executes an instruction by supervising the state of executing the instruction with different instruction execution times as references. CONSTITUTION:It is assumed that first a signal XF is generated when an ADD1M starts execution, after which the reading of the counter 3 is decremented in synchronization with a clock signal CK. The output signal CT of the counter 3 indicates '0' when the execution of the instruction ends. When the execution of a next instruction starts, the number of maximum steps in accordance with the type of instruction is set again. If an error signal ER is outputted when the value of the signal CT is below '0', an error signal generator 4 can deal with the error right after the microprogram with the maximum number of steps is executed. Thus an abnormal action time can be shortened, and the instruction execution can be surely supervised.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an instruction execution monitoring device used in a data processing device.

〔overview〕

The present invention provides a device for monitoring abnormalities in the execution of instructions by a processor, which reduces the time required to detect an abnormal situation by monitoring the execution state of each instruction based on the different execution times for each instruction. It has been made possible to do so.

[Conventional technology]

Conventionally, this type of instruction execution monitoring device treats the process as abnormal if the execution of the next instruction does not start after a certain amount of time has elapsed from the start of execution of a machine language instruction, regardless of the type of instruction. was going on.

[Problem that the invention seeks to solve]

In such conventional instruction execution monitoring devices, it is necessary to set the above-mentioned fixed time to a time that is equal to or longer than the execution time of the instruction that takes the longest execution time among all executable machine language instructions. Therefore, if an abnormal operation occurs during the execution of an instruction with a short execution time and the next instruction cannot be executed, the abnormal operation continues for a relatively long time until the abnormal situation is detected. Ta.

Furthermore, in the case of machine language instructions that involve sending and receiving data to and from an input/output device, the range of time required to send and receive data increases depending on the status of the input/output device, so the above-mentioned fixed time must be set to be particularly long. There were certain drawbacks.

SUMMARY OF THE INVENTION The present invention aims to eliminate such drawbacks and to provide an instruction execution monitoring device that can shorten the time required to detect an abnormal situation.

[Means for Solving the Problems] The present invention provides an instruction execution monitoring device that monitors the execution status of instructions in which the number of microprogram steps required for execution of instructions by a processor on means including an input/output device differs depending on the type of instruction. a storage means for storing the number of steps for each instruction; and a counting means for storing the number of steps related to this instruction each time execution of an instruction is started, and increasing or decreasing the number of steps at a predetermined rate with respect to this held value'. , a control means for generally prohibiting counting of this counting means, and when the count value of this counting means reaches a predetermined value and the next instruction has not been started, a signal indicating this state is generated. The present invention is characterized by comprising a signal generating means for generating a signal.

It is desirable that the control means be effective when data is exchanged between the processor and the input/output device.

[For production]

For each machine language instruction executed by the processor, the maximum number of steps of the microprogram other than the part that executes the transmission and reception of this data is stored in a storage means, and the maximum number of steps is output when execution of the machine language instruction starts. . The output of the storage means is held in the counting means at the start of execution of the machine language instruction, and then held in synchronization with the start of steps other than the data transmission/reception part with the input/output device in the machine language instruction microprogram. Increase or decrease a value by a fixed percentage and print the result. Based on the output of the counting means, the signal generating means detects a state in which the next instruction is not started even after the maximum number of steps necessary for executing the microprogram is executed from the start of instruction execution, and generates a signal representing this state. is displayed to the processor as an abnormal situation.

Here, counting is prohibited by the control means during the period of data transmission/reception with the input/output device, thereby making it possible to ignore periods with many uncertain factors.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be explained based on the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. A processor (hereinafter referred to as CPU 6) 1 executes machine language instructions using a microprogram, and executes one or more abnormalities! It has a function to process this situation if a signal representing imaginary is input, and it has an instruction code signal PD representing the type of machine language instruction, an instruction execution start signal XF representing the state in which execution of the instruction has started, and a step of the microprogram. A clock signal (J is output at the time of switching. Read-only memory (hereinafter referred to as ROM) 2 calculates the maximum number of microprogram steps required to execute this instruction based on the instruction code signal PD from the CPUI. The counter 3 outputs a step number data signal NST representing the number of steps.The counter 3 can set the initial value of the output at the time of starting counting.In this embodiment, the step number data signal NST from the ROM 2 is used as this initial value. This occurs when the instruction execution start signal XF is output from the CPU 1.The error signal generator 4 receives the output signal CT of the counter 3.
Based on this, an error signal ER is generated indicating that the number of steps in instruction execution exceeds the maximum required limit. Memory 5 stores machine language instructions and operand data, and sends a data signal DT representing the machine language instruction or operand data to CPUI based on address signal AD from CPU1. The input/output device 6 is used by the CPU in accordance with instructions from a microprogram when the CPU executes machine language instructions for controlling human output.
It is assumed that the data signal 10DT is transmitted and received, and when data is sent from the input/output device 6 to the CPU 1, it is necessary to manually input the data to the input/output device 6. Also, signal 10
M is output while the CPUI is transmitting/receiving data with the input/output device 6, and suppresses the counting operation of the counter 3. Signal ACK is a signal output when input/output device 6 notifies CPtJl that data transmission/reception has been completed.

Next, the operation of the apparatus shown in FIG. 1 will be explained in two cases.

For example, when the CPU 1 adds a certain machine language instruction that does not involve input/output control, for example, the data in the - register (hereinafter referred to as R1) in the CPU 10 and the operand data read from the memory 5, the result is added to R1. The instruction to hold in (
Hereinafter referred to as ADDIM. ) starts execution. An execution flowchart of the microprogram at this time is shown in FIG. Assuming that the ADDIM command ends in 5 steps as shown in Figure 2, at this time, if the signal PD represents ADDIM, the output signal NST of ROM2 will represent ``5'' in decimal number. . First, a signal XF is generated at the start of execution of ADDIM, and this value is set in the counter 3. If the value of the counter 3 is then decremented by "1" in synchronization with the clock signal CK, the output signal CT of the counter 3 will display the numerical value "O" at the end of the instruction execution. Thereafter, with the start of execution of the next instruction, the value of the maximum number of steps based on the type of instruction is set again. In the error signal generator 4,
Error signal ER when signal C70 value is below rOJ
If it is outputted, error handling can be performed immediately after executing the maximum number of steps of the microprogram necessary for executing ADD IM. In this case,
Is the CPUI sending an error signal El? It is assumed that the system has a function to immediately start error handling in response to an input.

Next, the CPU issues machine language instructions that involve input/output control, for example,
Command to read data from input/output device 6 to R1 (hereinafter referred to as
It's called LDRIIO. ) starts execution. A flowchart of the microprogram execution at this time is shown in FIG.

At this time, if the signal PD represents LDRIIO and the signal NST represents decimal [4], LD
This value is set in counter 3 at the start of execution of RIIO. Thereafter, the value of the counter 3 decreases in synchronization with the signal CK, but does not decrease and maintains its value when it is waiting to read data from the input/output device 6 at the second step from the start of execution of LDRIIO. This is because the input from the input/output device 6 is performed manually, and the number of loop executions becomes large and uncertain, and this period is not included in the maximum number of steps. Therefore, the decrementing operation of the counter 3 is restarted only after the signal ^CK is input from the input/output device 6 and the next step starts to be executed. After that, the signal C70 value is “
If the error signal ER is output when the value falls below "0", an abnormal situation can be detected even when the LDR1)0 instruction is executed.

In this way, depending on the type of machine language instruction, the maximum number of microprogram steps required to execute that instruction is set at the start of instruction execution, and after the set number of microprogram steps have been executed, the next machine If the execution of the word command is not started, it is considered that an abnormal situation has occurred, and a process can be performed to deal with it. Further, when detecting this abnormal situation, it is possible to ignore the time required for events with many uncertain factors such as data and human intervention of human intervention.

〔Effect of the invention〕

As explained above, the present invention uniquely handles abnormal situations for each type of machine language instruction when the next instruction is not executed after the execution of a microprogram with the maximum number of steps required for execution of the machine language instruction. This can be done immediately after executing the microprogram with the maximum number of steps required, and data transmission and reception with input/output devices, which have many uncertainties, can be ignored, so the duration of abnormal operation can be shortened and guaranteed. This has the effect of being able to monitor instruction execution.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram showing the configuration of an apparatus according to an embodiment of the present invention. 2 and 3 are flowcharts showing the operation of the embodiment device. 1... Processor (CPU), 2... Read-only memory (ROM), 3... Counter, 4...
Error signal generator, 5... memory, 6... input/output device.

Claims (2)

[Claims] (1) In an instruction execution monitoring device that monitors the execution state of instructions in which the number of steps of a microprogram required for execution of an instruction by a processor to means including an input/output device varies depending on the type of instruction, a memory that stores the number of steps for each instruction. The number of steps involved in this instruction is maintained for each method and instruction execution start,
A counting means for increasing or decreasing counting at a predetermined rate with respect to this held value, a control means for generally prohibiting counting by this counting means, and a control means for generally prohibiting counting by this counting means; 1. An instruction execution monitoring device comprising: signal generating means for generating a signal indicating an unstarted state when the instruction is in an unstarted state. (2) The instruction execution monitoring device according to claim (1), wherein the control means is effective during data transmission and reception between the processor and the input/output device.