JPS63101937A - Instruction execution monitoring device - Google Patents

Abstract

PURPOSE:To shorten a time required for the transmission/execution of data by executing abnormal state processing for various kinds of machine word instructions immediately after the passage of each maximum execution time required. CONSTITUTION:A memory stores data indicating the maximum execution time required for the execution of respective instructions other than I/O control instructions out of machine word instructions to be executed by an CPU1 and data indicating the maximum value of a residual time obtained by subtracting the time required for the transmission/reception of data to/from an I/O device 6 from the time required for the execution of the I/O control instructions, and when the CPU1 starts the execution of a machine word instruction, outputs the data indicating the maximum value in accordance with the kind of the instruction. If the succeeding instruction is not executed even after the passage of the maximum time required for the execution of the machine word instruction, the abnormal event processing is executed immediately after the passage of the maximum execution time independently required for each kind of the machine word instruction, so that the transmission/reception of data to/from the I/O device having many uncertain elements can be neglected.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an instruction execution monitoring device in a data processing device.

(Prior Art) Conventionally, this type of instruction execution monitoring device detects that the next instruction must be executed after a certain period of time, which is unrelated to the type of instruction, has elapsed from the start of execution of a machine language instruction. It was assumed that this was an abnormal operation and the corresponding processing was executed.

(Problems to be Solved by the Invention) In the conventional instruction execution monitoring device described above, the execution time of the instruction that takes the longest execution time among all the machine language instructions that can be executed during the above fixed time is An equal or longer time must be set, and if an abnormality occurs during the execution of an instruction with a short execution time and the next instruction cannot be executed, an abnormal situation will be detected. The disadvantage is that the abnormal operation continues for a relatively long period of time.

In addition, in the case of machine language instructions that involve sending and receiving data to and from an input/output device, the range of time required for sending and receiving data increases depending on the status of the input/output device, so the above fixed time should be set particularly long for that purpose. There is a drawback that it is necessary.

An object of the present invention is to provide unique methods for each type of machine language instruction to treat the situation as an abnormal situation when the next instruction is not executed even after the maximum time required for executing the machine language instruction has elapsed. It is an object of the present invention to provide an instruction execution monitoring device which eliminates the above-mentioned drawbacks by executing the instruction immediately after the maximum necessary execution time has elapsed, and which eliminates the need to set a particularly long time for sending and receiving data.

(Means for Solving the Problems) An instruction execution monitoring device according to the present invention includes a CPU, one or more I/O devices, a memory, a counter, and a signal generator. .

The CPU executes a plurality of machine instructions including input/output control commands, and processes situations when signals representing one or more abnormal situations t- are input.

The single or plural I/O devices are for transmitting and receiving data to and from the CPU according to instructions from the CPU when the CPU executes input/output control instructions.

Among the machine language instructions executed by 0PUK, the memory stores data representing the maximum execution time required for execution of each instruction other than input/output control instructions, and for input/output control instructions, From the time required for execution
Data representing the maximum time remaining after excluding the time required for sending and receiving data with the O device is stored, and when the CPU starts executing a machine language instruction, the maximum value is set according to the type of instruction. This is for outputting the data represented.

The counter retains the output of the memory at the start of execution of a machine language instruction, and thereafter updates the retained value at regular intervals except when data is sent to and received from the I/O device during execution of the machine language instruction. , and outputs the result by incrementing or decrementing at a constant rate, and when transmitting/receiving data, directly outputs the value held at the time of starting the data transmission/reception.

Based on the output of the counter, the signal generator detects a state in which the next instruction is not started even after the required maximum execution time has elapsed, in addition to data transmission and reception from the start of execution, and sends a signal representing this state to the CPU for abnormality. It is intended for input in the form of an error signal as a situation.

(Example) Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of an instruction execution monitoring device according to the present invention. In FIG. 1, l is the CPU,
2 is a ROM 13, a counter, 4 is a signal generator, 5 is a memory, and 6 is an I/O device.

0PUI is a processor that executes machine language instructions and has a function of processing the abnormal situation if a signal representing one or more abnormal events is input, and includes an instruction code signal PD representing the type of machine language instruction; It outputs an instruction execution start signal XF representing a state t in which execution of an instruction has started, and a clock signal OK having a constant period.

The ROM 2 is a read-only memory, and based on the instruction code signal FD from the CPU 1, outputs a step number data signal N5Ti representing the maximum number of microprogram steps required to execute the above instruction.

The counter 3 is a counter that can set an initial value of output at the time of starting counting. In FIG. 1, the step number data signal NET from ROM2 is used as the initial value, and when the signal XF is output from 0PU1, the signal NET
is initialized. The signal generator 4 is a signal generator that generates an error signal ER based on the output signal OT from the counter 3, which indicates that the number of instruction execution steps exceeds the required maximum. The memory 5 is a memory that stores machine language instructions and operand data, and based on the address signal AD from 0PUI, the data signal DTt-CPU1 representing the machine language instruction or operand data is stored.
Send to.

The I/O device 6 is an input/output device that sends and receives data signals 10DT to and from 50PU1 according to instructions from 0PU1 when 0PUI executes machine language instructions for input/output control, and handles all data I/O. When sending from O device 6 to CPU 1, I
Assume that it is necessary to input data into the /O device 6 on demand. Further, the signal is output while data is being exchanged between the IOMVi CPU1 and the I/O device 6, and the counting operation of the counter 3 is suppressed.

The signal AOK is output when the I/O device f16 notifies the 20PU1 that the data transmission/reception has been completed.

Next, regarding the operation of the instruction execution monitoring device shown in FIG.
Let's explain with an example.

Example 1: 0PUI is a machine language instruction that does not involve input/output control, for example, the data stored in one register (hereinafter referred to as R1) in 0PUI is added to the operand data read from memory 5. It is assumed that execution of an instruction (hereinafter referred to as an ADDIM instruction) to hold the result in R1 is started. At this time, if there is no abnormality in the device, the execution of the ADDIM command will be completed in 5 microseconds, and the cycle of the OK signal will be 1 microsecond.

At this time, when the signal PD represents the ADDIM instruction, if the output code NST of ROM2 is made to represent 5 in the /O base, when the execution of the ADD 1M instruction starts, i
No. XF is generated and the above value is set in the counter 3. After that, the value of counter 3 changes to 1 in synchronization with the clock signal OK.
If the output signal OT of counter 3 is decremented by
displays the number 1 or 0 at the end of instruction execution, and then, when the execution of the next instruction starts, the value of the maximum number of steps is set again for that instruction type.

If the signal generator 4 is configured to output the error signal ER when the first shift of the signal OT falls below 0,
Error handling can be performed immediately after the microprogram has been executed for the maximum number of steps necessary to execute the ADDIM instruction.

In this case, it is assumed that the CPU 1 has a function to immediately start error processing even when the error signal gR is input.

Example 2: CPU l executes machine language instructions that involve input/output control, such as I/O
It is assumed that execution of the command (hereinafter referred to as the LD_IIO command) to input data ta into the data storage unit 1 shown in Example 1 from the O device 6 is started.

At this time, the parts other than sending and receiving data with 0PUI are 4
It shall end in microseconds. Signal FD is LDRI
If the signal NET is made to represent 47 in the /O base when it represents an IO command, the above value is set in the counter 3 as in Example 1 at the start of execution of the LDR1/O command.

After that, the value of counter 3 is decremented in synchronization with the OK signal, as in Example 1, but in the middle of executing the LDRIIO command, I/O
When waiting for data to appear from the O device 6, the value is held without being decremented.

Since the input from the I/O device 6 is performed manually, the execution time for that part is long and uncertain, so the value of the counter 3 is held and this period should not be included in the required maximum execution time. become.

Therefore, the decrementing operation of the counter 3 is restarted only after the signal AOK is input from the I/O device 6 and the data reading is completed.

After that, as in Example 1, if the error signal ER is output when the value of the signal OT falls below Ot, the LDR
It is also possible to detect an abnormal situation in the case of executing an IIO mission.

Here, the period of the signal OK is assumed to be 1 microsecond as in Example 1.

With this, the maximum instruction execution time required to execute an instruction according to the type of machine language instruction is set at the start of instruction execution, and even after the execution time represented by the set value has elapsed, the next machine If the execution of the word command is not started, it is assumed that an abnormal situation has occurred, and the process corresponding to n1 can be executed. When detecting this abnormal situation, the time required for events with many uncertain elements, such as inputting data through manual intervention, can be ignored.

(Effects of the Invention) As explained above, according to the present invention, even after the maximum time required to execute a machine language instruction has elapsed, if the next instruction is not executed, processing is performed as an abnormal situation. By immediately executing each type of machine language instruction after its own maximum required execution time has elapsed, it is possible to ignore the transmission and reception of data to and from input/output devices, which have many uncertainties. There is a coming.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of an instruction execution monitoring device according to the present invention.

Claims (1)

[Claims] a CPU for executing a plurality of machine language instructions including input/output control instructions and for processing a situation when a signal representing one or more abnormal situations is input;
When the PU executes the input/output control command, the CP
one or more I/O devices for transmitting and receiving data to and from the CPU according to instructions from the CPU;
Among the machine language instructions executed by U, data representing the maximum execution time required for execution is stored for each instruction other than the input/output control instruction, and for the input/output control instruction, Data representing a maximum value of the remaining time after subtracting the time required for sending and receiving data with the I/O device from the time required for execution is stored, and execution of the machine language instruction is started by the CPU. and a memory for outputting data representing the maximum value according to the type of the instruction, and an output of the memory is held at the start of execution of the machine language instruction, and then the I /O When not transmitting or receiving data to/from the device, the held value is incremented or decremented at a constant rate at a fixed period and the result is output; when the data is transmitted/received, the data is A counter for directly outputting the value held at the time of the start of the transmission/reception of the data, and a counter for directly outputting the value held at the time of the start of the transmission/reception of the data, and a counter for directly outputting the value held at the time of the start of the data transmission/reception, and a counter for directly outputting the value held at the time of the start of the data transmission/reception. detects a state in which the instruction of CP is not started, and sends a signal representing that state to
1. An instruction execution monitoring device comprising: a signal generating device for inputting an abnormal situation in the form of an error signal to U.