JPS62237741A - Laminated semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the occupying area of a shift flip-flop and to improve the testing efficiency of a laminated semiconductor integrated circuit by forming and laminating a scanning circuit for testing in a scanning system a circuit to be tested on a semiconductor layer different from the circuit to be tested. CONSTITUTION:Data input/output units 11a-16a having relation to the normal operations of inner circuits 1a-1c contained in a circuit 1 to be tested are formed in the circuit 1. Test pattern input/output units 11b-16b for receiving a test pattern is formed in a scanning circuit 2 irrespective of the normal operations of wirings and the circuits 1a-1c for connecting in series shift flip- flops 11-16 at scan test mode time. The scan-in terminal Si and scan-out terminal SO of the shift flip-flop in the circuit 1 are connected with wirings or the shift input or output terminal of the flip-flop in the circuit 2 via the contact hole.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a stacked semiconductor integrated circuit, and more particularly to a structure of a semiconductor integrated circuit including a scan circuit for detecting a failure in a combinational circuit.

[Prior Art] When testing the operation of a combinational logic circuit in a large-scale semiconductor integrated circuit, a scan method is normally employed. This scanning method scans a test pattern into a memory element (flip-flop), operates a combinational circuit using the scanned-in test pattern, and then scans out the information and compares it with the test pattern. , to determine whether or not there is a failure in the combinational circuit.

FIG. 3 is a diagram showing a schematic configuration of a conventional semiconductor integrated circuit employing a scanning method. In FIG. 3, signal lines for setting the operation mode and clock signal lines for operating the flip-flops are omitted to avoid complication of the drawing.

The semiconductor integrated circuit has three internal circuits 1a and lb.

1c, and shift flip-flops 11-16 for testing the operation of internal circuits 1a-1c in a scanning manner. Shift flip-flops 11 to 13 are provided between the output section of the first internal circuit 1a and the input section of the second internal circuit 1b. Shift flip-flops 14 to 16 are provided between the output section of the second internal circuit 1b and the manual section of the third internal circuit 1c. The input section of the first internal circuit 1a is connected to input terminals 21, 22, and 23. The output portion of the third internal circuit 1c is connected to output terminals 24, 25°26. Each of the shift flip-flops 11 to 16 is
It includes a data input/output section (for example, 11a) and a test pattern input/output section (for example, 11b). The input terminal of the test pattern input section 11b of the shift flip-flop 11 is connected to the scan-in terminal Sl, and the output terminal of the test pattern input/output section 16b of the shift flip-flop 16 is connected to the scan-out terminal SO. The shift flip-flops 11 to 16 are connected in series with flip-flops (not shown in FIG. 3) included therein in the scan test mode to form a shift register.

FIG. 4 is a diagram showing an example of a specific configuration of shift flip-flops that can be connected in series in the scan test mode. In FIG. 4, the shift flip-flop is
When used as a normal flip-flop, that is, the circuit portion 50a serves as a data path during normal operation.
and a circuit portion 5Qb required for connecting shift flip-flops in series to form a scan canvas in the scan test mode.

The first circuit portion 50a includes an AND gate 31 that receives a signal applied through the data input terminal 37 and a complementary inversion signal of the signal applied through the shift mode setting terminal 35, and outputs the logical product. , an OR gate 33 that receives signals from an AND gate 31 and an AND gate 32 (described later), performs a logical sum, and outputs the result, and a clock terminal 36.
operates in response to a clock signal applied via the OR
It is composed of a flip-flop 34 that stores the output of the gate 33, and a data output terminal 39 that receives the output of the flip-flop 34.

The second circuit portion 50b performs an AND operation between the test pattern data applied via the shift input terminal 38 and the signal applied via the shift mode setting terminal 35, and performs an OR operation.
It is composed of an AND gate 32 which is applied to a gate 33, and a shift output terminal 40 which receives the output of a flip-flop 34.

In the above configuration, one shift flip-flop is
The data input terminal 37 and the shift input terminal 38 are used as input terminals, and the data output terminal 39 and the shift output terminal 40 are used as input terminals.
is configured as the output terminal. That is, the data input terminal 37 receives data from the internal circuit, and the shift input terminal 38 is connected to the scan-in terminal Sl or the shift output terminal of the preceding shift flip-flop. The data output terminal 39 transmits data to the next stage internal circuit, and the shift output terminal 40 transmits information to the next stage shift input terminal or scan out terminal SO.

When the shift flip-flop is operated normally, if the signal level applied to the shift mode setting terminal 35 is fixed at "L", the shift flip-flop accepts only data applied from the data input terminal 37, and inputs the shift input signal. Ignore data given from terminal 38. That is, data applied via data input terminal 37 is transmitted to data output terminal 39 and shift output terminal 40.

When a shift register is constructed by connecting shift flip-flops in series and operated as a scan register, the signal level applied to the shift mode setting terminal 35 is set to H'.
If it is fixed to , the shift flip-flop accepts only data applied through the shift input terminal 38 and ignores data applied from the data input terminal 37. That is, in this case, signal data applied via shift input terminal 38 is transmitted via flip-flop 34 to data output terminal 39 and shift output terminal 40. That is, when testing the internal circuits of a semiconductor integrated circuit by scanning, the signal level applied to the shift mode setting terminals of all shift flip-flops is set to "H".

Next, normal operation and scan test operation will be explained with reference to FIGS. 3 and 4. When testing the internal circuits of the large-scale integrated circuit shown in FIG. Next, a predetermined test pattern is applied from the scan-in terminal Sl, and the shift flip-flops 11 to 1 connected in series are connected in series.
6, the data pattern is observed and compared with the test pattern, and the shift flip-flops 11-16 are operating normally and each shift flip-flop 11-16 is confirmed.
Check that it is connected correctly.

Next, when testing the operation of the first internal circuit IA, first the signal level of the shift mode setting terminal 35 is set to "L", and a predetermined test pattern is applied from the input terminals 21, 22, and 23. The first internal circuit 1a has input terminals 21 to 23
It operates normally in response to data given through the shift flip-flops 11 to 13, and outputs the result of the operation. Flip-flop 34 in shift flip-flops 11-13 stores the given data. Next, when an "H" signal is applied to the shift mode setting terminal 35, the data in the flip-flop 34 is transferred in response to the clock signal applied via the clock terminal 36, and the The data is read from the scan out terminal SO via the campus. By comparing and observing the read data pattern and the test pattern, it is determined whether the first internal circuit 1a is operating normally.

When testing the operation of the second internal circuit 1b, first connect the shift mode setting terminal 35 of the shift flip-flop with “
A signal of H" is applied to enable the shift input terminal 38.

Next, a predetermined test pattern is applied via the scan-in terminal Sl, and this test pattern is stored in the shift flip-flops 11-13. Next, the signal level of the shift mode setting terminal 35 is set to "L", and the signal level of the data input terminal 37 is set to "L".
At the same time, the data stored in each flip-flop 34 is supplied to the first internal circuit 1b for normal operation. The operation results of the second internal circuit 1b are stored in each of shift flip-flops 14-16. Next, the signal level of the shift mode setting terminal 35 is set to “H”.
”, and each shift flip-flop 14 uses the scan path formed by the shift flip-flops 14 to 16.
Scan out the data stored in ~16 to terminal SO
The data pattern is observed and compared with a test pattern to determine whether the second internal circuit 1b is operating normally.

When performing an operation test on the third internal circuit 1c, a test pattern is applied from the scan-in terminal Sl to the shift flip-flop 14 in the same way as the test operation described above.
~16, and supplies the stored data to the third internal circuit 1c to operate normally.The operation result data of the third internal circuit 1c is read out via the small power terminals 24, 25, and 26. is compared with the test pattern, and the third internal circuit 1
It is determined whether the operation of c is normal or abnormal. In the above test operation, the data transfer operation in each shift flip-flop is controlled by a clock signal applied to the clock terminal 36.

[Problems to be solved by the invention] Conventional semiconductor integrated circuits are configured as described above,
When incorporating a scan type test circuit into the circuit,
Since the scan path is limited by the layout of the semiconductor integrated circuit, it is not possible to design the scan path freely, which reduces design efficiency. At the same time, it becomes difficult to realize a combination of internal circuits with high test efficiency. There was a problem that efficiency decreased.

In addition, shift flip-flops require a logic circuit to switch between normal operation mode and scan test mode, so there is a limit to how much space they can occupy.
This has been a major obstacle in improving the degree of integration of semiconductor integrated circuits.

Therefore, an object of the present invention is to eliminate the above-mentioned problems and reduce the area occupied by a shift flip-flop.
An object of the present invention is to provide a semiconductor integrated circuit equipped with a scan type test circuit with high test efficiency.

[Means for Solving the Problems] The stacked semiconductor integrated circuit according to the present invention has a test circuit consisting of a shift flip-flop circuit that is configured to perform at least a scan path and a scan operation unrelated to the normal operation of the internal circuit. The circuit is formed in a semiconductor layer different from the semiconductor layer in which the internal circuit, which is the circuit to be tested, is formed and stacked.

[Function] The stacked semiconductor integrated circuit according to the present invention is configured such that at least a part of the test circuit is formed in a semiconductor layer different from the semiconductor layer in which the circuit under test is formed. Test circuits can be configured freely and efficiently without any restrictions.

[Embodiments of the invention] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a stacked semiconductor integrated circuit according to an embodiment of the present invention. In FIG. 1, a circuit under test (internal circuit) 1 and a circuit for testing the circuit under test 1 by a scan method (hereinafter simply referred to as a scan circuit) 2 are formed on different semiconductor layers and are compensated for. Ru. That is, data input/output portions 11a to 16a of the shift flip-flops 11 to 16 that are related to the normal operation of internal circuits 1a to 1c included in the circuit under test 1 are formed within the circuit under test 1.

On the other hand, wiring made of aluminum, for example, for connecting the shift flip-flops 11 to 16 in series during the scan test mode, and a test pattern input/output portion for receiving test patterns, which are not directly related to the normal operation of the internal circuits 1a to IC. 11b to 16b are scan circuits 2
is formed.

The scan-in terminal SI and scan-out terminal SO of the shift flip-flop in test circuit 1 are connected to the wiring in scan circuit 2 or the shift input terminal or shift output terminal of the shift flip-flop through contact holes (dashed lines in FIG. 1). be done.

FIG. 2 is a diagram showing a specific configuration of the shift flip-flop shown in FIG. 1. In FIG. 2, a data input/output portion 50a of the shift flip-flop is formed within the circuit under test 1, and a test pattern input/output portion 50a is formed within the circuit under test 1.
b is formed within the scan circuit 2. The data input/output portion 50a and the test pattern input/output portion 50b are connected through a contact hole (broken line in the figure).

The data input/output portion 50a has a data input terminal 37 and an AN
D gate 31, OR gate 33 and flip-flop 34
and a data output terminal 39. The test pattern (shift data) input/output portion 50b includes an AND gate 32, a shift input terminal 38, and a shift output terminal 40. The flip-flop 34 is configured to be shared by the data input/output section 5Qa and the test pattern input/output section 50b.

Shift setting terminal 35 and clock terminal 36 are provided in data input/output circuit 50a.

The circuit configuration itself of the shift flip-flop shown in FIG. 2 is the same as that of the conventional shift flip-flop shown in FIG. The operation is similar.

In the above embodiment, the scan circuit is formed in one semiconductor layer, but the scan circuit may be formed in n semiconductor layers.

In this case, n or more scan path patterns can be set, making it possible to improve test efficiency.

Further, in the above embodiment, the configuration in which the AND gate 32 and the test pattern output terminal 40 are provided in the scan circuit 2 has been described, but any configuration can be used as long as it is similar to the configuration shown in FIG. But it goes without saying that it's a good thing.

[Effects of the Invention] As described above, according to the present invention, the scan circuit for testing the circuit under test using the scan method is formed on a different semiconductor layer from the circuit under test and is configured by stacking layers. can be designed without being restricted by the layout of the circuit under test, which increases design efficiency and allows the combination of internal circuits to be freely selected, making it possible to realize a scan path with high test efficiency. , it is possible to obtain a highly integrated semiconductor integrated circuit that can be efficiently tested using the scanning method.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a schematic configuration of a stacked semiconductor integrated circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing the configuration of a shift flip-flop included in a test circuit in a stacked semiconductor 4&multilayer circuit according to an embodiment of the present invention. FIG. 3 is a diagram showing a schematic configuration of a semiconductor integrated circuit equipped with a conventional scan type test circuit. FIG. 4 is a diagram showing the configuration of a shift flip-flop included in the test circuit. In the figure, 1 is the circuit under test, 2 is a scan circuit (scan type test circuit), 1a to 1c are internal circuits, 1
1 to 16 are shift flip-flops, 11a to 16a are data output portions of the shift flip-flops, llb to
16b is a test pattern input/output portion of the shift flip-flop, 50a is a data input/output circuit of the shift flip-flop, and 50b is a test pattern output circuit of the shift flip-flop. In addition, in the figures, the same reference numerals indicate the same or corresponding parts. Figure 2 Figure 4 Procedural amendment band (spontaneous) October 3, 1939 1, Indication of the case: Japanese Patent Application No. 61-82617 2, Name of the invention: Laminate Semiconductor Integrated Circuit 3, Person making the amendment: Representative: Shiki Moriya 4, Agent 5゜ Figure 1 6 of the drawings subject to the amendment and Figure 1 of the drawings containing the amendments are as attached. that's all

Claims (2)

[Claims] (1) A stacked semiconductor integrated circuit consisting of a three-dimensional circuit formed by three-dimensionally stacking semiconductor layers on which a semiconductor circuit is formed, the three-dimensional circuit comprising a first circuit that performs normal operation; a semiconductor circuit; and a test circuit coupled to the first semiconductor circuit for performing an operation test of the first semiconductor circuit in a scanning manner, at least a part of the test circuit being connected to the first semiconductor circuit. A stacked semiconductor integrated circuit characterized in that it is formed in a semiconductor layer different from a semiconductor layer in which a semiconductor circuit is formed. (2) The test circuit includes a data input/output circuit for exchanging data with the first semiconductor circuit in a normal operation mode, and a data input/output circuit for exchanging test data with the first semiconductor circuit in a scan test mode. It is composed of a scan input/output circuit and a flip-flop that stores the output of the data input/output circuit or the output of the scan input/output circuit, and the data input/output circuit and the scan input/output circuit are formed on different semiconductor layers. A stacked semiconductor integrated circuit according to claim 1.