JPS62234370A - Gto thyristor - Google Patents

Abstract

PURPOSE:To facilitate drawing-out of a large current by a method wherein the outer circumference of a base layer is extended to the same plane as emitter layers and a gate electrode is extended onto that plane and a gate electrode unit which is unified with but electrically insulated from an electrode unit pressed against a main electrode is pressed and contacted with the extension of the gate electrode. CONSTITUTION:The outer circumference of a silicon substrate 1 which has 4 layers of PNPN has a PNP structure and the circumference of a P-type base layer 12 is extended to the same plane as emitter layers 11. Bevel shape formed on the side surface of the lower layers is extended onto the side surface of the outer circumference of the P-type base layer 12. A gate electrode 22 formed on the bottom of a recessed part 13 is connected to a gate elec trode 23 formed on the outer circumference of the P-type base layer 12 through an Al layer 24. As the outer circumference is the gate part, the effective area of cathode is not reduced. A gate contact electrode unit 8 is formed solidly on the outer circumference of a contact electrode unit 3 with an insulator 7. As a lower surface electrode 81 is pressed against the gate electrode 23 on the same plane as cathodes 21, the gate electrode 23 receives the same pressure as the cathodes and is contacted with the electrode layer 81. With this constitution, a large contact area can be obtained and a large current can be drawn out.

Description

[Detailed description of the invention] [Technical field to which the invention pertains]

The present invention provides a GT comprising one main electrode provided on a divided emitter layer and a gate electrode provided on a base layer surrounding the emitter layer, and in which an electrode body is in pressure contact with the main electrode.
Regarding O thyristor.

[Prior art and its problems]

As the current of the GTO thyristor increases, the gate extraction current also increases. The gate structures of conventionally known GTO thyristors include a central gate structure shown in FIG.
There is an outer peripheral wire bonding structure shown in the figure and an intermediate ring structure shown in FIG. In the center gate structure, pnpn
A gate conductor is formed by a disc spring 5 accommodated in a recess 32 provided at the center of a contact body 3 having an electrode layer 31 in pressure contact with a cathode electrode 21 provided on an n emitter layer 11 of a silicon substrate l having four layers. The electrode body 41 at the tip of 4 is p
It is pressed against the center of a gate electrode 22 provided on the base layer 12 or made of a vapor deposited layer. However, in this structure, the contact area of the gate electrode body 41 is very small, making it impossible to draw a large current. In the outer periphery wire bonding structure, the conductor 6 is wire-bonded to the outer periphery of the gate electrode 22, but in wire bonding, the larger the current flowing through the conductor 6, the more the long-term stability is deteriorated due to thermal fatigue. . In the intermediate ring structure,
An annular electrode body 42 embedded in the cathode contact electrode body 3 via an insulating material 33 and connected to the gate conductor 4 is pressed against the annular gate electrode 23 . In this way, the cathode electrode body 3 and the gate electrode body 42 are integrated, and the gate electrode 23
This is excellent in that the cathode electrodes 21 and 21 are pressed together with equal pressure, but since the pattern of the cathode electrode 21 is provided with the annular gate electrode 23 in between, in order to equalize the main current, it is necessary to It is not possible to take up a large area, and in order to extract a large gate current, it is necessary to provide annular gate electrodes in multiple stages, and the structure of the contact electrode body must also be extremely large. jl becomes sloppy.

[Purpose of the invention]

The present invention improves reliability by connecting the gate electrode provided in the base layer with an electrode body that is in pressure contact with the gate electrode, and also makes it possible to draw a large current from the gate by contacting the electrode body with a sufficiently large contact area. The purpose is to provide cyrisk.

[Key points of the invention]

In the present invention, the base layer adjacent to the emitter layer on the upper surface side is extended to the same plane as the emitter layer at the outer periphery, and the gate electrode is extended to the surface thereof, and the gate electrode extension part is attached to the main layer on the emitter layer. The above object is achieved by press-contacting the gate electrode body, which is integrated with the electrode body and is electrically insulated from the electrode body. Furthermore, the bevel formed on the side surface of the semiconductor substrate where the pn junction between both base layers is exposed can be extended to the same plane as the emitter layer together with the base layer, which is effective in improving the breakdown voltage.

[Embodiments of the invention]

FIG. 1 shows an embodiment of the present invention, and parts common to FIGS. 2 to 4 are given the same reference numerals. As is clear from a comparison with FIGS. 2 to 4, the outer periphery of the silicon substrate 1 having four pnpn layers has a pnp structure without 0-layer diffusion so as not to impair the dv/dt withstand capability. Base layer 12 extends to the same plane as n emitter layer 11 . The bevel shape formed on the side surface of the lower layer is extended on the side surface of the outer peripheral portion of the p base layer 12 . Since the outer peripheral portion is also formed as a gate portion in the conventional examples shown in FIGS. 2 to 4, the effective area of the cathode is not reduced. The gate electrode 22, which is attached to the bottom surface of the recess 13 dug from the top surface of the substrate 12, is formed of the p base layer 1.
The gate electrode 23 and the M layer 2 formed on the upper surface of the outer periphery of the M layer 2
Connected by 4. A gate contact electrode body 8 is integrally formed on the outer periphery of the contact electrode body 3 having an electrode layer 31 in pressure contact with the cathode electrode 8i21 via an insulator 7, and the electrode layer 81 on the lower surface thereof is on the same plane as the cathode electrode 21. It is pressed into contact with the gate electrode 23 located at. Therefore gate electric 8i23
contacts the electrode 1Ji81 under a pressure equal to that of the cathode electrode.

【Effect of the invention】

According to the present invention, by extending the gate electrode to the outer periphery of the semiconductor substrate and pressing the electrode body there, the contact area can be increased, and a large current can be drawn out. In addition, by extending the outer periphery of the base layer, where the gate electrode is in pressure contact with the electrode body, to the same plane as the uppermost emitter layer, the gate electrode body can be formed into a plate shape integrally with the electrode body that is in pressure contact with the main electrode. The structure of the Ti body is simple, and the main electrode and the gate electrode are brought into contact with the same pressing force, resulting in improved reliability. As a result, compared to a conventional GTO thyristor of the same size, the gate impedance was significantly reduced and the controllable current increased by about 40%. Additionally, the sides of the base layer are longer when the gate is provided;
By extending the bevel surface to that portion, the effect of improving the forward breakdown voltage between the anode and cathode was obtained. These effects can be similarly obtained in a GTO thyristor in which the gate electrode is provided in the n-base layer, unlike the embodiment.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a silicon substrate and a contact electrode body according to an embodiment of the present invention, and FIGS. 2, 3, and 4 are cross-sectional views of a silicon substrate and a contact electrode body of a conventional GTO SIRISK, respectively. . l: silicon substrate, 11: n emitter layer, 12: 9 base layer, 21: cathode electrode, 22.23: gate electrode,
3: cathode contact electrode body, 7: insulator, 8: gate contact electrode body.

Claims (1)

[Claims] 1) One main electrode is provided on the surface of the emitter layer divided into a plurality of regions, a gate electrode is provided on the surface of the region surrounding the emitter layer region of the adjacent base layer, and the electrode body is in pressure contact with the main electrode. In this case, the base layer extends to the same plane as the emitter layer at the outer periphery, and the gate electrode is extended to the same plane as the emitter layer, and the gate electrode extension part is integral with an electrode body that presses against the main electrode and is electrically insulated therefrom. A GTO thyristor characterized in that the gate electrode body is in pressure contact with the gate electrode body.