JPS62234195A - Liquid crystal display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a liquid crystal display device used as a type of flat panel display.

Conventional technology In recent liquid crystal display devices (LCDs), amorphous Si
Active transistors consist of pairs of semiconductor switches such as thin film transistors (TPT) and liquid crystal elements arranged in a matrix.
A matrix method has been developed.

As shown in FIG. 6, a typical active matrix type liquid crystal display device has m gate drive lines Cz arranged at equal intervals in the vertical direction within the display screen.
Gz, Gz...G1, and n drain drive lines D arranged at equal intervals in the horizontal direction within the display screen.
+, Di, Ds...Pixel display area Llli L+z+L13 corresponding to each intersection of Dn...
...L, 7 is a pixel display area. As shown in FIG. 1, a pair of a semiconductor switch S made of a thin film transistor or the like and a liquid crystal element LC is formed. Each of m gate drives &1c+-c is a gate driver G of m gates.
It is connected to the respective output terminals of D and -GD.

Each of the n drain drive lines DI-D, , is connected to the output terminal of each of the n drain drivers DD, -DD, , and the input terminal of each drain driver is connected to the n switches 81 to 81. Pixel memories LM1, ~L in the first line memory LMI via S, l, respectively.
LM in one or second line memory LM2 of MIn
2 +~LM2. selectively connected to one of l.

As shown in the timing chart of FIG.
Each pixel signal of the first line A appearing above is stored in the corresponding pixel memory L in the first line memory LMI in the order of appearance.
The pixel signals of the second line B appearing on the signal line H are sequentially written in the second line B.
The corresponding pixel memory LM21 in the line memory LMZ of
LM2. , are sequentially written within. In parallel with this writing to the second line memory LM2, the contents of each pixel memory LM1r to LMI11 in the first line memory LMI are written to the switches 81 to S, 1 and the drain driver DD.
, -DDn, and are amplified and transferred all at once onto the drain drive signal lines D1 to Dfi. In synchronization with this, a gate drive signal is output onto the gate drive line G1 by the gate driver GD, and each pixel signal of the first line A is supplied to the liquid crystal element LC via the semiconductor switch S.

Each pixel signal of the third line C appearing on the signal line H is sequentially written into the first line memory LMI. In parallel with this writing to the first line memory LMI, each pixel memory LM 2 + to LM in the second line memory LMZ
2. The content of
n and are amplified and transferred all at once. In synchronization with this, a gate drive signal is outputted onto the gate drive line G2 by the gate driver GD2, and each pixel signal of the second line B is supplied to the liquid crystal element LC via the semiconductor switch S.

Thereafter, in the same manner, pixel signals are written to the first line memory LMI, pixel signals are transferred from the second line memory LM2 onto the drain drive signal line ~D7, and pixel signals are written to the second line memory LM2. The writing of pixel signals and the transfer of pixel signals from the first line memory LMI onto the drain drive signal lines D1 to D7 are alternately repeated.

FIG. 8 is an equivalent circuit diagram showing the electrical coupling relationship between the pixel memory LM, drain driver DD, drain drive signal line, and pixel display area.

The pixel memory LM consists of a sample and hold circuit consisting of a sampling switch SS and a hold capacitor CM, and the liquid crystal element in the pixel display area is connected to the capacitor C.
It is equivalent to L. Also, RD is the drain driver D
This is the output resistance of D.

The capacitance value of the hold capacitor CM is set to a relatively small value so that the charging of the hold capacitor CM due to the closing of the switch SS is completed within the pixel appearance time on the line. On the other hand, the capacitance value of the capacitor Ct is small, about 0 degrees PF, but since the semiconductor switch S is a thin film transistor formed of amorphous Si, etc., the resistance value when conducting is several 100 KΩ. It becomes a large value of about several MΩ. For this reason, it takes a long time to transfer the charge held in the hold capacitor C11 to the capacitor CL equivalent to the liquid crystal element, and conventionally, the drain driver is operated over almost one line of DD.

Note that CD in Figure 8 is an equal capacitor that equalizes the distributed capacitance value between the drain drive line and the ground using a lumped circuit, and although it depends on the width and length of the drive line, it is usually The value is about several tens of PF, which is one to two orders of magnitude larger than the capacitance value of the capacitor CL which is equivalent to the liquid crystal element. Charging the capacitor CD, which is equivalent to this distributed capacitance, results in wasted power consumption, so the challenge is how to reduce this value, especially in portable liquid crystal display devices that use batteries as a power source. It is thought that there is.

Means for Solving the Problems The above-mentioned conventional liquid crystal display device requires two lines of line memory, which poses a problem in that the entire circuit becomes complex and effective.

Furthermore, since the drain driver is operated during each horizontal scanning period, there is a problem that power consumption increases.

Structure of the Invention Means for Solving the Problems A liquid crystal display device according to a first invention that solves the problems of the prior art described above includes a single line memory that holds pixel signals for one line, and a single line memory that stores pixel signals for one line. It is equipped with a drain driver that simultaneously amplifies each of the pixel signals for one line held in the pixel signal line and transfers them to the corresponding pixel signal line within the next horizontal retrace period, and uses the distributed capacitance of the drain drive line to transfer the line memory to the corresponding pixel signal line. By transferring each pixel signal in the LCD to the corresponding liquid crystal element, the circuit size of the line memory can be halved and the operating time of the drain driver can be shortened to a fraction of a fraction.

Further, the liquid crystal display device according to the second invention includes a drain driver that immediately amplifies each of the 1947 pixel signals without going through the line memory and transfers them onto the corresponding pixel signal line, and By transferring the data to the liquid crystal element via the distributed capacitance of the drain drive line, the line memory of the conventional device is omitted and the operation time of the drain driver is reduced to about one in several times.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing a liquid crystal display device according to an embodiment of the first invention together with other parts of the liquid crystal display device.

In this liquid crystal display device as well, as in the conventional device described above, m gate drive lines G, , G, , G3 . . . m x n pixel display areas L+++ L+ arranged at each intersection of 0 drain drive lines D+, Dz, D3...Dn arranged at equal intervals in the horizontal direction.
t+L13...L□ are formed, and each pixel display unit is composed of a pair of a semiconductor switch S made of an amorphous St thin film transistor or the like and a liquid crystal element LC. Also, like the conventional device, m gate drive lines G l
``' Each of G- has m gate driver CDs, ~
It is connected to the respective output terminals of GD and a, and 0
Each of the drain drive lines -D is connected to the output terminal of each of the n drain drivers DD, .about.DDn. These drain drivers DD, ~DD
, is fixedly connected to one of the pixel memories LM, ˜LM,1 within a single line memory LM.

As shown in the timing chart of Figure 2, the signal line H
Each pixel signal to the first line appearing above is stored in the corresponding pixel memory LM in the single line memory LM in the order of its appearance.
+ to LM, are sequentially written. This pixel memory LM
Each pixel signal written within the corresponding drain driver DD+ to DD, simultaneously with the start of the next horizontal retrace period.
The corresponding drain drive lines are simultaneously amplified by 1, -D
,,transferred on. In the capacitors C1 to CDfi, which equalize the ground distributed capacitance of each drain drive line, charging is started by the voltage appearing on the respective drain drive line, ~D.

Capacitor C by the amplified pixel signal of the first line A
Charging of D and wcon ends when the drain drivers DD, ~DD, , transition to a high impedance state with the end of the horizontal retrace period.

The pixel signal group of the second line B that subsequently appears on the signal line H is stored in the line memory L separated from the drain drive line.
The data starts to be sequentially written into the corresponding pixel memories LMI to LM7 in M. In parallel with writing the pixel signal group of the second line B into the line memory LM, the gate driver G D
A gate drive signal is output onto the gate drive line G by r, and each pixel signal of the first line A, which has already been transferred to the drain drive signal line ~D7 and the equivalent capacitor CDI~C0, passes through the semiconductor switch S to the liquid crystal element. begins to be transferred all at once to the capacitor C1 which is equivalent to .

Each pixel signal of the second line B written in the pixel memory LM is transferred to the corresponding drain driver D within the next horizontal retrace period.
. While being amplified by I-DI and fi, it is simultaneously transferred onto the corresponding drain drive line -D.

The pixel signals of the second line B are transferred to all drain drivers DD at the end of the horizontal retrace period.

The process ends when ~DDn transitions to a high impedance state. Subsequently, writing of each pixel signal of the third line C to the pixel memories LM, -LM is started. This third
In parallel with writing to line memory LM on line C, a gate drive signal is outputted onto gate drive line G2 by gate driver GD2, and drain drive signal '4iAD,
-D, the pixel signals of the second line B, which have already been transferred to the equivalent capacitor CnI''C, begin to be supplied all at once to the corresponding liquid crystal element LC via the semiconductor switch S.

Thereafter, in the same way, in the single line memory LM, the writing of pixel signals over one line and the transfer onto the drain drive line over the next horizontal retrace period are repeated, and on the drain drive line, the pixel signals are transferred from the line memory LM. Transfer of the completed pixel signal to the liquid crystal element is repeated.

FIG. 3 is an equivalent circuit diagram showing the electrical coupling relationship between the pixel memory LM, drain driver DD, drain drive signal line, and pixel display area. Similar to the conventional device, the pixel memory LM is constituted by a sample and hold circuit consisting of a sampling switch SS and a hold capacitor CH, and the liquid crystal element in the pixel display area is equivalent to a capacitor CL. Further, Rtl is the output resistance of the drain driver DD.

The hold capacitor C of the pixel memory LM is set so that the charging of the hold capacitor C1l due to the closing of the sampling switch SS is completed within the pixel appearance time on the line.
The capacity of □ is set to a relatively small value. The voltage value held in this hold capacitor CM is transferred onto the drain drive line while being amplified by the drain driver DD which operates over the next horizontal retrace period. Since the semiconductor switch S is closed during the horizontal retrace period, the voltage appearing on the drain drive line charges the capacitor C0, which is equivalent to the distributed capacitance existing between the drain drive line and the ground point. will be started. The capacitance value of this equivalent capacitor Co is a large value of about several tens of PF, but since the output resistance value R8 of the drain driver DD is a small value of about several hundred Ω, the distributed capacitance is c.
Charging to o ends.

When the input of the next line to the line memory LM is started, the drain driver DD shifts to a high impedance state. In synchronization with this, the semiconductor switch S is made conductive by the gate drive line G, and the equivalent capacitor co + "'
The charge that was charged in C6fi is changed to the corresponding liquid crystal CL all at once.
begins to be transferred to. This charge transfer ends with the end of charging or the end of one line.

FIG. 4 is a block diagram showing a liquid crystal display device according to an embodiment of the second invention together with other parts of the liquid crystal display device.

Also in this liquid crystal display device, gate drive lines GI,
Gz, G3...G1 and n drain drive lines D+, Dz, I)'I...
Dn and pixel display area Lll+ LI2+ Li2
” ” ' Lllllll and gate driver G, -
G, and drain driver DD.

The configuration of ~DD, , is the same as that of the conventional device.

In this example, the drain drivers D D + ~DD
, , are connected directly to the signal line H without going through a line memory, and through one of the drain drivers DD, -DD, which operate only during the appearance period of the drive pulses p1 to p7 synchronized with each pixel signal. Direct drain drive line D1~
The signal is amplified and transferred to the equivalent capacitors C1 to C0 of D0.

That is, as shown in the timing chart of FIG. 5, at the same time as the first pixel signal A1 of the first line A appears,
The gate drive line G1 and drive pulse pl rise to high.

The pixel signal A1 is the drain driver D that is in the operating state.
D, the equivalent capacitor CO of the drain drive line D1
Charge t. Although the semiconductor switch S in the pixel display area Lll is already conductive, its resistance value in the conductive state is about three orders of magnitude larger than the output resistance value of the drain driver DD.

Most of the output current is once charged into the equivalent capacitor C0. The charge once accumulated in the equivalent capacitor CDI is transferred to the drain driver DD by the falling of the driving pulse p.
, continues to be transferred to capacitor C5 for a long time even after transitioning to a high impedance state. The same applies to the subsequent pixel signals A z , A 3 , . . . .

Regarding the pixel signal that appears in the latter half of one line, for example, the final pixel signal Afi, the gate drive line G remains high even during the next horizontal blanking period in order to secure the transfer time from the equivalent capacitor CDI to the capacitor CL. kept in condition. The same applies to the subsequent lines B, C, and so on.

Although the case where the pixel display area is composed of a pair of semiconductor switches and a liquid crystal element has been exemplified above, a structure including a plurality of pairs may be used as a countermeasure against defects.

Effects of the Invention As explained in detail above, the liquid crystal display device of the present invention has the following effects:
Since each pixel signal in the line memory is transferred to the corresponding liquid crystal element using the distributed capacitance of the drain drive line, the circuits related to the line memory can be halved or omitted, making the entire display device cheaper. In addition, since the drain driver is configured to operate only during the horizontal retrace period or during the appearance period of one pixel on each line, the operating time is a fraction of that of a conventional liquid crystal display device that operates over one line.
The time can be reduced to a factor of several hundred, and power consumption can be reduced accordingly.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a liquid crystal display device according to an embodiment of the first invention, and FIGS. 2 and 3 are timing charts and equivalent outputs for explaining the operation of the above embodiment. , FIG. 4 is a block diagram showing the configuration of a liquid crystal display device according to an embodiment of the second invention, FIG. 5 is a timing chart for explaining the operation of the above embodiment, and FIG. 6 is a diagram showing a conventional liquid crystal display device. Block diagrams showing the configuration of the display device, FIGS. 7 and 8
The figure shows the timing diagram to explain the operation of the conventional device mentioned above.
This is a chart and an equivalent circuit. G, -G, ... Gate drive line, D, -D, ...
Drain drive line, L I + "" L l*R...Pixel display area, S...Semiconductor switch consisting of amorphous Si thin film transistor, etc., LC...Liquid crystal element, CD
. ~GDII...Gate driver, DD, ~DD,
・・Drain driver, LMl~LM,l ・・Pixel memory in M in line memory, SS・・Sampling switch, CH・・Hold capacitor, R11・・Output resistance of drain driver DD, CDI~C11fi
...An equivalent capacitor that equates the distributed ground capacitance of the driver drive lines D1 to D7.

Claims (2)

[Claims] (1) In an active matrix liquid crystal display device in which one or more pairs of semiconductor switches and liquid crystal elements are arranged in a matrix for each pixel to be displayed, pixel signals for one line appearing within one horizontal scanning period are held. a line memory; an amplifier that simultaneously amplifies each of the pixel signals for one line held in the line memory and transfers the transferred pixel signals onto the corresponding pixel signal line within the next horizontal retrace period; A liquid crystal display device comprising a vertical scanning circuit that selectively closes only a group of semiconductor switches arranged at a display position over the next horizontal scanning period. (2) In an active matrix liquid crystal display device in which one or more semiconductor switch and liquid crystal pairs are arranged in a matrix for each pixel to be displayed, each pixel signal for one line appearing over one horizontal scanning period is amplified. In the vertical direction, the amplifier that transfers the signal onto the corresponding pixel signal line and the semiconductor switch group arranged at the display position of the transferred pixel signal are selectively closed during this horizontal scanning period and the next horizontal retrace period. A liquid crystal display device comprising a scanning circuit.