JPS62233773A - Automatic operation confirmation test system - Google Patents

Abstract

PURPOSE:To reduce the operation man-hours of an operation confirmation test by testing the operation confirmation of all trouble detecting circuits and alarm generating circuits. CONSTITUTION:An automatic operation confirming circuit 3 sends out pseudo trouble serial data A and a pseudo trouble write clock B to a pseudo trouble generation control circuit 4 under the control of a microprocessor 3 an the pseudo trouble generation control circuit 4 sends out a pseudo trouble generation signal C. A trouble detecting circuit 11 which receives the pseudo trouble detecting circuit 11 when entering a trouble detection state sends out a trouble signal to an alarm generating circuit 12, which sends out an alarm output F corresponding to the trouble signal E on receiving the trouble signal E. When, this alarm output F is sent to the automatic operation confirming circuit 3 and confirms that the alarm output corresponding to previously set pseudo trouble.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an operation test of a fault detection circuit and an alarm generation circuit provided in a system having a function of detecting a fault condition and generating an alarm.

[Conventional technology]

Conventionally, when testing the operation of fault detection circuits and alarm generation circuits installed in systems that have the function of detecting fault conditions and generating alarms, it is necessary to simply generate only actual faults that can be performed manually. We are conducting operation confirmation tests. Furthermore, when checking the alarm output of an alarm generation circuit, the current method is to use a simple jig that displays the alarm output status of the alarm generation circuit, and mainly relies on visual tests by humans. .

[Problem that the invention seeks to solve]

By the way, as mentioned above, in the case of the operation confirmation test of the conventional failure detection circuit and alarm generation circuit.

It is not possible to test the operation of the fault detection circuit and alarm generation circuit due to a fault that simply cannot be performed manually. In addition, in recent years, due to the complexity of the functions within the equipment due to technological advances, the number of fault detection circuits and alarm generation circuits that require i#I operation confirmation tests has continued to increase. If all operations were to be tested manually, there would be a problem in that the number of man-hours required would be enormous.

[Means for solving problems]

The present invention relates to a system having a function of detecting a fault condition and generating an alarm output.

a pseudo fault occurrence control circuit that sends out a pseudo fault occurrence signal;
The pseudo-failure generation circuit and the fixing means are controlled by the microprocessor to cause predetermined pseudo-faults to occur one after another, and each fault state is fixed by the microprocessor. The feature is that the corresponding alarm output is checked.

〔Example〕

The present invention will be explained below with reference to Examples.

Referring to the drawings, a system 1 includes a fault detection circuit 11, an alarm generation circuit 12. It includes an OR gate 2 and a pseudo fault occurrence control circuit 4. The output of the OR gate 2 is connected to the fault detection circuit 11, and one of the inputs of the OR gate 2 is +5
Connected to the v terminal. The other input of the OR gate 2 is connected to a pseudo fault occurrence control circuit 4 composed of a D type flip-flop 41.

When confirming the operation of the fault detection circuit 11 and alarm generation circuit 12, one of the inputs of the OR gate 20 and the pseudo fault occurrence control circuit 4 are connected to an automatic operation confirmation circuit 3 equipped with a microprocessor as shown. Further, the output of the alarm generation circuit 12 is inputted to the automatic operation confirmation circuit 3.

Next, confirmation of the operation of the failure detection circuit 1] and the alarm generation circuit 12 will be explained.

Under the control of the microprocessor 31, pseudo fault serial data A and pseudo fault write clock B are sent from the automatic operation confirmation circuit to the pseudo fault occurrence control circuit 4. Then, the pseudo fault occurrence control circuit 4 sends out a pseudo fault occurrence signal C.

By the way, as shown in Figure 1, a high level (/'5V) is applied to the input of the OR gate 20, and regardless of the input of the pseudo fault occurrence signal C to the OR gate 2, the OR gate 2
always outputs high level. That is, the pseudo fault occurrence signal C is not output to the fault detection circuit 11. next.

When the +5V terminal is grounded under the control of the microprocessor 31 (for example, the +5V terminal is grounded by turning on a switching transistor (not shown) provided in the automatic operation confirmation circuit 3), the input of the OR gate 2 becomes It changes from high level to low level (this change from high level to low level is called the pseudo failure mode switching signal). As a result, a pseudo fault occurrence signal C is sent to the fault detection circuit 11 via the OR gate 2. That is, the OR gate 2 holds the pseudo-failure occurrence signal C, and sends out the pseudo-fault occurrence signal C when it receives the pseudo-failure mode switching signal.

When the fault detection circuit 11 receives the pseudo fault occurrence signal C and enters a fault detection state, it sends a fault signal E to the alarm generation circuit 12. Alarm generation circuit 1 receiving this fault signal E
2 sends out an alarm output F corresponding to this fault signal E. And this alarm output F is the automatic operation confirmation circuit 3.
It is confirmed by the microprocessor 31 that an alarm output corresponding to a preset pseudo failure has occurred.

In this way, by sending out pseudo-failure signals for all fault detection circuits.

The operation of all fault detection circuits can be confirmed in a short time.

〔Effect of the invention〕

As explained above, one aspect of the present invention includes a pseudo-fault occurrence control circuit that sends out a pseudo-fault signal, a fixing means for forcibly fixing a fault detection circuit to a fault state by the pseudo-fault signal, a pseudo-fault occurrence control circuit, and and automatic operation confirmation means including a microprocessor that controls the fixing means to sequentially generate predetermined pseudo-failures in the fault detection circuit and confirms the alarm output corresponding to each fault state. All operation confirmation tests for fault detection circuits and alarm generation circuits can be performed automatically and in an extremely short time. Therefore, the reliability of the fault detection circuit and alarm generation circuit can be improved, and the number of man-hours for testing can be significantly reduced.

[Brief explanation of drawings]

The drawing is a block diagram showing an embodiment of the present invention with some parts omitted. DESCRIPTION OF SYMBOLS 1... System, 2... OR gate, 3... Automatic operation confirmation circuit, 4... Pseudo fault occurrence control circuit, 11.
...Fault detection circuit, 12...Alarm generation circuit, 31
...Microprocessor, 41...D type flip flow knob.

Claims (1)

[Claims] 1. In a system having a function of detecting a fault state and generating an alarm output, a pseudo fault occurrence control circuit that sends out a pseudo fault occurrence signal, and a fixing means for forcibly fixing the fault state using the pseudo fault occurrence signal. The pseudo fault generation circuit and the fixing means are controlled by a microprocessor to sequentially generate predetermined pseudo faults, and the alarm output corresponding to each fault state is checked. Automatic operation confirmation test method.