JPS62233718A - Pulse conversion circuit for resolver - Google Patents

Abstract

PURPOSE:To output a pulse which is smooth on the whole by knowing the number of output pulses in each period and its period time, dividing the period by the number of pulses and thus calculating the time between output pulses, and then outputting the pulses. CONSTITUTION:When an accumulator 130 is cleared to zero with a signal obtained by delaying a differentiation signal, a multiplexer 132 outputs the value of a register 10 (period time) with the output of a status output circuit 131. Consequently, an adding circuit 133 outputs the value of a register 10. The output of the status output circuit 131 is inputted to a pulse train circuit 14 to output a pulse. When the number of output pulses is zero, its output is intercepted by a zero detecting circuit 15. Then, a subtracter circuit 134 subtracts the absolute value (number of output pulses) of a register 7 from the value of the register 10 and sends the result to the accumulator 130, which latches it with a clock signal CK.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pulse conversion circuit for a resolver used for position detection of machine tools, robots, etc.

[Conventional technology]

Conventional pulse conversion circuits of resolvers are known to perform analog processing using a PLL system. However, since it is an analog circuit, there are problems such as temperature fluctuations in the VCO (voltage frequency conversion circuit) and the like, and component precision affecting the output.

On the other hand, there are pulse conversion circuits using the BRM method using digital processing. An example of this is shown in FIG.

In Figure 1, ■ is the ring counter, 2 is the resolver L
Excitation circuit that generates an excitation signal to E, 3 is resolver LE
4 is a register that latches the output of ring counter 1 with a zero-cross signal, 18 is a subtraction circuit that subtracts the value of counter 19 (described later) from register 4, and 20 is a subtraction circuit of the subtraction circuit. The register that latches the value, 21, sets the absolute value of the value to 2.
2 is a circuit for detecting the sign thereof, and 23 is a BRM circuit which outputs a pulse train of the value of the absolute value detection circuit 21.

Reference numeral 19 denotes a counter that goes up and down depending on the output pulse train of the BRM circuit and the output of the code detection circuit. Reference numeral 24 designates a pulse generating circuit for outputting a pulse train similar to that of a pulse encoder from the output of this counter.

Now, assuming that the resolver LE is moving in a certain direction at a certain rotation speed, the register 4 always indicates the current position of the resolver LE by the zero cross signal from the comparator 3.

The number of pulses to be output this time is calculated by a subtraction circuit 18 that subtracts the value of the counter 19 from the value of this register 4. Then, the value is inputted to the BRM circuit 23 through the register 20 and the absolute value detection circuit 21, and outputs a pulse train. The output pulse becomes an amplifier down pulse from the output of the code detection circuit to the counter 19. This B
The drive clock of the RM circuit is determined by the maximum number of pulses to be output and the period of the output.

[Problem that the invention seeks to solve]

By the way, it is generally known that the frequency of the detection signal of the resolver LE changes depending on its rotation speed and rotation direction. Therefore, considering the highest frequency of the detection signal during operation, it is necessary to output a pulse train for the current travel distance within the period at that time. If the BRM cycle is set longer than the above-mentioned cycle, the detection signal frequency will increase depending on the rotation direction during acceleration, so the pulse train that should be output within the cycle will be output next without waiting for all outputs. The value of will be set, and the unoutput portion of the pulse will remain. This pulse is then carried over to the next output. FIG. 2 shows this situation.

As the frequency gradually increases in this way, unoutput pulses accumulate, and there is a risk that the BRM will overflow. Therefore, the period of the BRM circuit must be set short to prevent this from occurring.

However, if pulses are output in such a short period, the detection signal frequency becomes low depending on the direction of rotation, and as shown in FIG. 3, pulses are not output throughout. Such a pulse output is inappropriate as a position loop pulse.

In view of the above points, the present invention provides a pulse conversion circuit for a resolver that outputs smooth pulses throughout.

[Means for solving problems]

In order to solve the above-mentioned problems, the present invention uses a certain clock to count the period of the detection signal that changes depending on the rotating direction and number of rotations of the resolver, and includes a register that represents the double period time, and a register that uses the clock as an arithmetic clock. The device is equipped with a circuit that subtracts the value of each movement distance from the value in the register, and when the result is zero or negative, outputs a pulse and adds the value in the register to the result to perform a similar operation. It is something.

[For production]

As described above, in order to output smooth pulses throughout, the present invention knows the number of output pulses in each period and its period time, and divides the period by the number of pulses to calculate the time between the output pulses. According to this method, a smooth pulse can be output even if the frequency of the detection signal changes.

〔Example〕

FIG. 4 is a block diagram of an embodiment of the present invention, where ■ is a ring counter that counts from 0 to N, and 2 is a ring counter 1.
an excitation circuit that generates an excitation signal from the output of the resolver to the resolver;
17 is a bandpass filter; 3 is a comparator that compares the detection signal from the resolver and generates a zero-cross signal;
4 is a register that latches the output of the ring counter 1 at the rising edge of the zero cross signal from the comparator 3;

When the resolver LE is rotating, the resolver detection signal becomes a signal with a phase shift of sin (wt + θ) with respect to the excitation signal sinwt, and the output of register 1 is latched with the zero cross signal of this signal, and this register 4 always represents the current position of the resolver.

In other words, the resolver can only know the position of the zero-crossing signal every cycle.

Reference numeral 5 denotes a counter that goes up and down according to the output pulse train, and although it is delayed by one cycle, it indicates the momentary position of the resolver LE. The counter 5 counts from 0 to N. The number of pulses to be outputted is determined by a subtraction circuit that subtracts the value of the counter 5 from the register 4 to find the current movement distance, that is, the current number of output pulses and its direction (forward or reverse).

8 is a differentiation circuit that differentiates the rising edge of the zero cross signal with respect to the clock signal CK, and 7 is a subtraction circuit 6 using the differential signal.
This is a register that launches the output of . In other words, the register 7 latches the distance traveled each time.

9 is a counter that is counted by the clock signal CK and reset by the differential signal of the differentiating circuit 8; 10 is the counter 9;
This is a register that latches the output of the differential signal. This register 10 represents the cycle time obtained by counting the cycle of each zero-crossing signal, that is, the detection signal, using the clock signal CK.

11 is a circuit that detects the absolute value of register 7; 12 is a circuit that also detects the sign of register 7; 13 is a circuit that uses clock signal CK as an operation clock to subtract the absolute value of register 7 from the value of register 10; If the value of the accumulator containing the result is zero or negative, the arithmetic circuit outputs the status, adds the value of register 10 to the result, and subtracts the absolute value of register 7 again.

FIG. 5 shows a detailed diagram of this arithmetic circuit, where 130 is an accumulator register that latches the arithmetic result of the subtraction circuit 134 using the clock signal CK, and 131 is a status register that outputs a signal when the value of the accumulator is zero or negative. 132 is a multiplexer that selects the output of register 10 or "O" according to the output of 131; 133 is an adder circuit that adds the output of multiplexer 132 and the output of accumulator 130; 135 is a circuit that delays the differential signal by one clock.

Next, the operation will be explained. First, the accumulator 130 is cleared to "O" by a signal obtained by delaying the differential signal. Then, the multiplexer 132 outputs the value of the register 10 by the output of the status output circuit 131. (This is the periodic time, as mentioned earlier.) As a result, adder circuit 133 outputs the value of register 10. In addition, the output of the status output circuit is output from the pulse train circuit 14.
It will enter and output a pulse.

If the output pulse number is “0”, zero detection circuit 1
5 stops its output. And the subtraction circuit 13
4 subtracts the absolute value of register 7 (which is the number of output pulses) from the value of register 10 and outputs it to accumulator 130, which latches it in response to clock signal CK.

If the value of the accumulator 130 is "positive" at that time, the status output circuit 131 does not output an output this time, so the multiplexer 132 outputs "0". Then, the value of the accumulator 130 is output to the subtraction circuit 134, and the absolute value of the register 7 is subtracted from this value. Similar calculations are then performed for each clock signal CK.

A calculation flowchart for this part is shown in FIG.

Assuming that the values of register 7 and register 10 are 3.10, the pulse output will be as shown in FIG.

The pulse train circuit 14 generates up pulses and down pulses for the counter 5 based on the output of the status output circuit 131 and the output of the sign detection circuit 12.

However, when the value of the subtraction circuit 6 is zero, no pulse is generated due to the output of the detection circuit 15. Reference numeral 16 denotes a pulse generation circuit that generates A-phase, B-phase, and C-phase pulses of the same output as the pulse encoder from the output of the counter 5.

〔Effect of the invention〕

Let us consider when the rotation of the resolver LE is accelerating and the detection signal frequency becomes high or low. First, when the period becomes shorter and shorter, all the pulses cannot be output within that period, and the remaining pulses are passed on to the next period.
In the second cycle, the pulses including the remaining pulses from the previous cycle will be output.

Therefore, there is no overflow due to accumulated pulses, resulting in a pulse train with smooth changes. Also, when the period becomes longer and longer, one pulse is output to B.
Unlike the RM method, pulses are not emitted in a fixed period, but pulses are emitted at intervals that correspond to changes in the period, so even if the period becomes longer, pulses are output throughout.

As mentioned above, although this circuit uses digital processing, it is possible to obtain pulses with smooth changes similar to those processed by analog circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a conventional resolver pulse conversion circuit, FIGS. 2 and 3 are diagrams showing the state of output pulses in the conventional pulse conversion circuit, and FIG. 4 is a block diagram of an embodiment of the present invention. FIG. 5 is a detailed block diagram of the calculation circuit, FIG. 6 is a calculation flowchart, and FIG. 7 is a diagram showing the state of pulse output in the embodiment of the present invention. 1...Ring counter 2...Resolver excitation circuit 3...Comparator 4...Register 5...Up/down counter 6...Subtraction circuit 7...Register 8...Differentiating circuit 9... - Counter O...Register 11...Absolute value detection circuit 12...Sign detection circuit 13...Arithmetic circuit 14...Pulse train circuit 5...Zero detection circuit. 16...Pulse generation circuit F...Band filter 18...Subtraction circuit 19...Up/down counter 20...Register 21...Absolute value detection circuit 22...Sign detection circuit 23...- BRM circuit 24... Pulse generation circuit 25... Delay circuit 130... Achim register 131... Status output circuit 132... Multiplexer 133... Addition circuit 134... Subtraction circuit 135... Delay circuit

Claims (1)

[Claims] A ring counter that counts from 0 to N, and resolver excitation signals sinwt and cos from the ring counter value.
an excitation circuit that generates wt, a comparator that compares the resolver detection signal and outputs a zero-crossing signal, a register that latches the output of the ring counter with this zero-crossing signal, and a counter that goes up and down (from 0 to a subtraction circuit that subtracts the value of this counter from the value of the register to calculate the travel distance, a differentiation circuit that differentiates the zero-cross signal with the clock signal CK, and a count-up circuit with the clock signal CK. A period counter that is reset by this differential output, a period counter register that latches the value of this period counter with the differential output, a register that latches the value of the subtraction circuit with the differential output, and a clock signal CK is operated. As a clock, the absolute value of the travel distance, which is the output of this register, is subtracted from the value of the period counter register, and if the value of the accumulator containing the result is zero or negative, the status is output and the result is added to the period counter register. There is an arithmetic circuit that adds values and subtracts the absolute value of the register again, a pulse train circuit that outputs up and down pulse trains depending on the zero or negative status output of the accumulator value and the sign of the travel distance value, and 1. A pulse conversion circuit for a resolver, comprising a pulse generation circuit for outputting a pulse train similar to that of a pulse encoder from the output of the above-mentioned counter that goes down.