JPH0384463A - Speed detecting circuit - Google Patents

Abstract

PURPOSE:To obtain a conversion signal with high resolution by measuring the output period of an encoder by counters which are provided as many as phases of an out-of-phase multiphase clock and reading a detected speed value out of conversion data on a ROM by using the measured period as an address. CONSTITUTION:A control circuit 7 clears the counters 3 and 4 when the output of the encoder 2 rises, then the counters count the output of a two-phase clock generating circuit 5, and an adder 6 adds their counted values together. The control circuit 7 latches the summed value by the adder 6 when the output of the encoder 2 rises next and the counters 3 and 4 are cleared at the same time and start next counting operation. The latched summed value is processed by a dividing circuit 8 and converted into a detected speed. In this conversion, the latched summed value is supplied as an address to the ROM as the dividing circuit and the detected speed value is read out. This speed value is converted by a D/A converter 9 into an analog speed feedback signal.

Description

[Detailed Description of the Invention] <Industrial Application Field> The present invention relates to an improvement in a speed detection circuit that detects the moving speed of an object to be detected by an encoder from an encoder output that is a phase modulated pulse signal. .

<Conventional technology> In systems that feedback control motor rotation,
As an encoder for rotation detection, phase change r! ! A 0-phase modulation type encoder including a J-type encoder outputs a pulse signal whose phase is modulated by the rotational position of the motor. In this encoder, the frequency of the pulse signal is modulated by the rotation of the motor, so the rotation speed of the motor can be detected by measuring the period of the pulse signal.

A system that uses a phase modulation encoder to feedback control the rotational speed of a robot arm's drive motor requires an F/V converter that measures the frequency of the encoder's detection signal with high resolution and converts it into voltage. .

Conventionally, as an F/V converter, there has been an F/V converter using an analog circuit that combines an integrator and a sample-and-hold circuit.

However, since this F/V converter uses analog components such as an integrating capacitor, it has drawbacks such as not being able to obtain satisfactory temperature characteristics and requiring a large number of adjustment points.

To solve these drawbacks, a digital F/A converter measures the cycle of the encoder output using a counter, converts the measured cycle to a frequency using a microcomputer, and converts this into a voltage using a D/A converter. There was a V converter.

<Problems to be Solved by the Invention> However, in such a digital F/V converter, the resolution of the conversion signal is limited by the period measurement clock generator that can be formed within the gate array that constitutes the F/V converter. Because it is limited by frequency, it is not possible to obtain sufficient resolution.As a result, requantization noise may cause abnormal noise from the motor, and calculation time becomes longer, which increases the delay in speed detection and speed feedback control. There was a problem that the phase margin of the loop was deteriorated.

Here, the requantization noise is the fluctuation of the LSB of the digital input of the D/A converter. When this fluctuation is amplified by a power amplifier connected to the output stage of the D/A converter, an abnormal noise is generated from the motor.

The present invention was made to solve these problems, and it is possible to obtain a high-resolution conversion signal without increasing the clock frequency of the clock generator itself, and to reduce the delay time in speed detection. The purpose is to realize a speed detection circuit.

In this application, a circuit having a function as an F/V converter as described above is referred to as a speed detection circuit.

Means for Solving the Problems> The present invention provides the following advantages: From an encoder output that is a phase modulated pulse signal,
In the speed detection circuit that detects the moving speed of the object to be detected by the encoder, there are N counters, N-phase clocks are applied to these N counters, and each counter is counted at a timing with a phase shift of 360"/N. an N-phase clock generation circuit that adds up the counts of the N counters; and an adder that adds up the counts of the N counters; and after clearing the N(l!l counters) at the rising edge of the pulse signal, and a control circuit that causes the adder to latch the added value at the rising edge of the next pulse signal, and a control circuit that stores the added value and a detection speed value calculated from this added value in correspondence, and stores the added value and the detected speed value calculated from the added value, and A speed detection circuit comprising: a memory from which a detected speed value is read using the value as an address.

In the present invention, a polyphase tarok whose phase is shifted,
The speed is detected by measuring the cycle of the encoder output using a counter provided for the number of phases, and reading the detected speed value from a conversion table written in the ROM using the measurement cycle as an address.

<Example> Hereinafter, the present invention will be explained using the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention.

In the figure, 1 is a motor whose rotational speed is to be detected, 2 is an encoder that detects the rotation of the motor 1 and outputs a detection signal as a phase modulated pulse signal, and 3.4 is a counter.

5 is a two-phase clock generation circuit, which includes a clock generator 51 that generates a clock of a constant frequency, and a clock generator 51 that generates a clock of a constant frequency;
It consists of a flip-flop 52 that divides the frequency to create a two-phase clock.

6 is an adder that adds the counts of two counters 3 and 4 and holds the addition result.

A control circuit 7 generates a reset signal for the counters 3 and 4 and a latch signal for the adder 4 based on the output of the encoder 2.

8 is from the addition value n latched by the adder 6, VEL= (
This is a division circuit that outputs the detected speed VEL obtained by the formula: a/n)-b (2). 0 type a
and b are constants and take different values depending on the motor model.

As the division circuit 8, a ROM is used in which a conversion table is written that associates the added value n with the value of the detected speed VBL obtained from the added value n using the formula 0.

Reference numeral 9 denotes a D/A converter that converts the detected speed VEL read out from the divider circuit 8 from digital to analog. The converted signal becomes a speed feedback signal.

The operation of the speed detection circuit configured in this way will be explained.

FIG. 2 is a time chart of each signal of the speed detection circuit.

(a) The encoder output shown in the figure is input to the control circuit 7.

After the control circuit 7 clears the two counters 3 and 4 at the rising edge of the encoder output, it starts counting.

At this time, the adder 6 adds the counts of the two counters.

Eventually, at the next rising edge of the encoder output, the control circuit 7
causes the adder 6 to latch the added value. At the same time, the two counters are cleared and the next count is started.

Here, the addition value n latched by the adder 6 is input to the division circuit 8, which performs calculations and converts it into the detected speed VEL. In this conversion, the detected speed VEL is read by giving the latched addition value n as an address to the ROM, which is a division circuit.

The input/output relationship of the division circuit 8 is shown in FIG. 3. In the diagram shown in FIG.
4-bit addition value data Ag.

Using A1...A13 as addresses, 14-bit detection speed data D0. D, . . . D13 are read out.

By converting the read detection distance VEL with the D/A converter 9, an analog signal of the detection speed is obtained. This signal becomes the speed feedback signal.

Although the embodiment has been described using two counters and a two-phase clock, a configuration using N counters and N-phase clocks (N is an integer of 3 or more) may also be used.

Effect〉 According to the present invention, the following effects can be obtained.

■Since the cycle of the encoder output is measured using a multiphase clock with a phase shift and a counter provided for the number of phases,
The period can be measured using a clock whose frequency is substantially higher than the frequency of the clock generated by the clock generator. As a result, a high-resolution conversion signal can be obtained without increasing the clock frequency of the clock generator itself.

(2) Since the calculation for determining the detection speed from the measurement period of the encoder output is performed using a conversion table written in the ROM, the calculation time is shortened. This reduces the delay in speed detection and improves the phase margin of the speed feedback control loop.

Additionally, the burden on software is reduced.

[Brief explanation of drawings]

FIG. 1 is an elliptical diagram of one embodiment of the present invention, and FIGS. 2 and 3 are diagrams explaining the operation of the circuit of FIG. 1. 1...Motor, 2...Encoder, 3.4...Counter, 5...Clock generation circuit, 6...Adder,
7... Control circuit, 8... Division circuit, 9... D/A
converter.

Claims (1)

[Claims] From an encoder output that is a phase modulation type pulse signal,
In the speed detection circuit that detects the moving speed of the object to be detected by the encoder, there are N counters, N-phase clocks are applied to these N counters, and each counter is counted at a timing with a phase shift of 360°/N. an N-phase clock generation circuit that causes the N-phase clock generation circuit to perform this operation; an adder that adds the counts of the N counters; and an adder that causes the N counters to count the period of the pulse signal after clearing the N counters at the rising edge of the pulse signal. , a control circuit that causes the adder to latch the added value at the rising edge of the next pulse signal, and a control circuit that stores the added value and the detected speed value calculated from this added value in correspondence, and addresses the latched added value. A speed detection circuit comprising: a memory from which a detected speed value is read out.