JPS622333B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a memory that is read/written in 8-byte units and an 8-byte fetch data
The present invention relates to an alignment control method in a byte machine that has a register, an 8-byte write register, write data of 8 bytes, and a memory reference unit of 8 bytes or less.

FIG. 1 illustrates a buffer storage device to which the present invention is applied, in which FIG. 1A is a diagram explaining an overview of a fetch system, and FIG. . In Figure 1 A and B, 1
is the effective address register, 2 is the buffer memory,
3 is a fetch align circuit, 4 is a fetch data register, 5 is a store align circuit, 6
indicates a write register, FD indicates fetch data, and SD indicates write data.

The buffer memory 2 is, for example, 64K bytes, and an address is assigned to each byte. The reading/writing unit of the buffer memory 2 is 8 bytes. The fetch align circuit 3 is a shifter that shifts the 8-byte fetch data FD read from the buffer memory 2 in byte units in accordance with a shift amount instruction signal. The fetch data register 4 is of 8 bytes, and 8 bytes of data output from the fetch align circuit 3 is set therein.
The write data SD is 8 bytes, and the write register 6 is also 8 bytes. The store/align circuit 5 is also a shifter, and this store/align circuit 5 shifts the write data in byte units according to the shift amount instruction signal. The output of the store/align circuit 5 is set in the write register 6.

The shift amount instruction signal is created based on the effective address and the memory reference byte length, but in the prior art, the circuit for creating the shift amount instruction signal is complicated and requires a considerable amount of time. The memory reference byte length is within 8 bytes.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an alignment control system which eliminates the above-mentioned drawbacks and which allows a shift amount instruction signal to be generated at high speed with a small amount of metal. Therefore, the align control method of the present invention reads 8 bytes of data from the memory from a specified read start address, and uses the read 8 bytes of data according to the read start address, memory reference byte length, and alignment instruction information. Therefore, when aligning with the align circuit and setting in the 8-byte fetch data register, or aligning the 8-byte write data with the align circuit according to the write start address, memory reference byte length, and alignment instruction information. te8
This is an alignment control method used when setting a byte write register, and includes a data conversion means that inputs alignment instruction information and a 3-bit memory reference byte length and outputs 3-bit data, and the data conversion means. an adder that adds the 3 bits output by the means and the least significant 3 bits of the memory access address; a decoder that decodes the output of the adder; and an output of the decoder that is sent to the align circuit as a shift amount instruction signal and the data conversion means is configured to set the data of the byte length specified by the memory reference byte length including the data of the read start address in the fetch data register in a right-justified manner. or if it is specified that the data of the byte length indicated by the memory reference byte length from the right in the 8-byte write data is valid, the 3 bits representing the memory reference byte length are specified. and the alignment instruction information sets the data of the byte length specified by the memory reference byte length including the read start address, with the third byte position of the fetch data register as the limit, or the write data If it is specified that the data of the byte length indicated by the memory reference byte length existing in the left half including the data at the third byte position is valid, the 3-bit data indicating the memory reference byte length The most significant bit of the data is forcibly set to logic "1", and the align instruction information transfers the data of the byte length specified by the memory reference byte length, including the data of the read start address, to the fetch data. - If it is specified that the register is set left-aligned, or that the data of the byte length specified by the memory reference byte length from the left in the write data is valid, it will be "111". It is characterized by being configured to output data. Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 2 shows the structure of a part of the buffer memory 2. As shown in FIG. Note that in the figure, EAR indicates an effective address. FIG. 2 shows one line (64 bytes) of buffer storage, and in reality, it can be considered that a set of such lines are connected in the vertical direction. Six bits, bits 26 to 31 of the effective address, represent the first address within the line at fetch time. In the illustrated example, A, B, C, D, E, F, G,
Data H is stored. Note that each of A to H is 8 bytes of data. When you start reading by specifying the start address "011101" in the line, D, E, F,
8-byte data in G, H, A, B, C format is read.

FIG. 3 shows a time chart during a data fetch. In FIG. 3, B1 is one cycle of buffer access, and B2 is one cycle of buffer access.
2 access cycles, R indicates the register set cycle, and Li indicates the memory reference byte length. The effective address EAR is sent from the instruction control unit, and bits 20 to 31 or 21 to 31 indicate the address within the page. Memory reference byte length
Li is also sent from the instruction control unit and is expressed as a 3-bit decoded signal.
If these 3 bits are L-DEC0, 1, and 2, then L
-DEC0, 1, 2 "000" means that the effective byte length including the data at the start address is 1, and "001" means that the effective byte length is 2. The same applies below. In the memory reference byte length Li,
In addition to the L-DEC0, 1, and 2 signals, write/
There are just 8 bytes (hereinafter referred to as Rj8), right just middle (hereinafter referred to as RjM), and left just (hereinafter referred to as Lj).
Rj8 is fetish data FD when fetish
This means that RjM should be set to the right in the register, and RjM should be set to the right with the position of byte 3 as the limit when fetching. When RjM is rising, the effective byte length is 4
It never exceeds. Lj means that when performing a fetch, the fetch data FD should be set in the register in a left-aligned manner. Rj8, RjM and
Lj will never be on at the same time.

FIGS. 4, 5, and 6 explain alignment during fetching, and FIG. 4 explains Rj8. Figure 4A shows a specific example of Rj8, and as shown in Figure 2, the buffer memory 2
The data is stored in bit 26 of the effective address.
It is assumed that 31 through 31 are "011101" and that the memory reference byte length is "101" (effective byte length 6). As can be seen from FIG. 4A, by shifting the fetch data FD by 3 bytes to the left, 6 bytes of data including data A can be set in the fetch data register 4 right-justified. Note that G and H mean invalid bytes on the register.

FIG. 4B shows the relationship between bits 29 to 31 of the effective address, effective byte length, and shift amount in the case of Rj8. Note that shift means left shift. From Figure 4 B EAR+L=111→S=0 EAR+L=110→S=7 EAR+L=101→S=6 EAR+L=100→S=5 EAR+L=011→S=4 EAR+L=010→S=3 EAR+L=001 →S=2 EAR+L=000→S=1 It can be seen that the equation (1) is satisfied. In addition, in the above formula, EAR
represents bits 29 to 31 of the effective address, L represents the memory reference byte length L-DEC0 to 2, and S represents the shift amount.

FIG. 5 explains RjM. FIG. 5A shows a specific example of RjM. As shown in FIG. 2, data is stored in the buffer memory 2, and bits 26 to 31 of the effective address are "011101".
It is further assumed that the memory reference byte length is "001" (effective byte length 2). As can be seen from Figure 5A, if the fetch data FD is shifted to the left by 3 bytes, 2 bytes of data including data A can be set to the right with the 3 byte position of fetch data register 4 as the limit. I can do it.

FIG. 5B shows the relationship between bits 29 to 31 of the effective address, effective byte length, and shift amount in the case of RjM. Note that the shift indicates a left shift. In the case of RjM, the RjM signal forces the memory reference byte length L-DEC0 to "1" and sets bits 29 to 3 of the effective address.
When 1 is added, the relationship between the addition result and the shift amount shown in equation (1) can be applied as is.

FIG. 6 explains Lj. FIG. 6A shows a specific example of Lj. As shown in FIG. 2, data is stored in the buffer memory 2, and bits 26 to 31 of the effective address are "011101".
It is further assumed that the memory reference byte length is "101" (effective byte length 6). As can be seen from FIG. 6A, by shifting the fetch data FD by 5 bytes to the left, 6 bytes of data including data A can be set to the left. In the case of Lj, the Lj signal forces the memory reference byte length L-DEC0, 1, and 2 to "111".
When bits 29 to 31 of the effective address are added as , the relationship between the addition result and the shift amount shown in equation (1) can be applied as is.

FIG. 7 shows one embodiment of the shift amount instruction signal generation circuit used in the present invention, in which 7 to 9 are OR circuits, 10 is a 3-bit adder, and 11 is an OR circuit.
indicate decoders, respectively. +Lj, +RjM and +L-DEC0 are input to OR circuit 7, and OR
+Lj and +L-DEC1 are input to circuit 8, and OR
+Lj and +L-DEC2 are input to the circuit 9. Note that portions 7 to 9 constitute data conversion means.

Figure 8 shows written data before being stored in buffer memory 2.
This shows the relationship between SD and write data after storage. FIG. 8 shows a case where bits 26 to 31 of the effective address are "011101" and Lj. In the case of store, the meaning of Lj indicates that the valid portion in the write data SD is from the left. That is, in the example of FIG. 8, it is valid from A,
The memory reference byte length or effective bytes at that time is L
If it shows that L including data A
This means that the byte data is valid as write data. Rj8 indicates that the valid portion of the write data is from the right. That is, in the example of FIG. 8, data of L bytes to the left of H including H is valid. RjM means that the valid portion in the SD of write data is to the left of the third byte position. That is, in the example of FIG. 8, this means that L bytes of data including D and to the left of D are valid as write data.

Figures 9 to 11 are respectively at the time of storage.
This explains Rj8, RjM, and Lj. Figure 9 is
A specific example of Rj8 is shown, in which bits 26 to 31 of the effective address are "011101" and the effective byte length is 6 (101). In this case, the write data SD is shifted to the right by 3 bytes and set in the write register 6. Although the explanation will be omitted, the relationship between the effective addresses 29 to 31, effective byte length, and shift amount in the case of store and Rj8 is as shown in FIG. 4B. However, the shift is to the right.

Figure 10 shows a specific example of RjM.
In this example, effective address bits 26 to 31 are "011101" and the effective byte length is 2 (001). In this case, the write data SD is shifted to the right by 3 bytes and set in the write register 6. In the case of store and RjM, the relationship between bits 29 to 31 of the effective address, effective byte length, and shift amount is as shown in FIG. 5B.
However, the shift becomes a right shift.

Figure 11 shows a specific example of Lj,
In this example, effective address bits 26 to 31 are "011101" and the effective byte length is 6 (101). In this case, the write data SD is shifted to the right by 5 bytes and set in the write register 6. In the case of store and Lj, the relationship between bits 29 to 31 of the effective address, effective byte length, and shift amount is as shown in FIG. 6B. However, the shift is a right shift.

Even in the case of store, when Rj8, the relationship in Figure 4 (B) holds true, when RjM, the relationship in Figure 5 (B) holds true, and when Lj, the relationship in Figure 6 (B) holds, so the shift amount instruction in Figure 7 is established. The signal generation circuit can be used as is.

As is clear from the above description, according to the present invention, a shift amount instruction signal can be created at high speed with a small amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an overview of a buffer storage device to which the present invention is applied, FIG. 2 is a diagram showing a partial configuration of the buffer storage, FIG. 3 is a time chart during data fetch, and FIG. 4 Figures 6 to 6 are diagrams explaining the alignment during fetish, and Figure 4 is for Rj8.
Figure 5 is a diagram explaining RjM, Figure 6 is a diagram explaining RjM.
The figure is a diagram explaining Lj, FIG. 7 is a diagram showing one embodiment of the shift amount instruction signal generation circuit used in the present invention, and FIG. Figures 9 to 11 show the relationships between Rj8, RjM, and RjM at the time of storage, respectively.
For explaining Lj, FIG. 9 is a diagram showing a specific example of Rj8, FIG. 10 is a diagram showing a specific example of RjM,
FIG. 11 is a diagram showing a specific example of Lj. 1...Effective address register, 2...Buffer memory, 3...Fetch align circuit, 4...
Fetch data register, 5...Store align circuit, 6...Write register, 7 to 9...
...OR circuit, 10...3-bit adder, 11...
decoder.

Claims (1)

[Scope of Claims] 1. 8-byte data is read from the memory from a specified read-out start address, and the read-out 8-byte data is sent to an align circuit according to the read-out start address, memory reference byte length, and alignment instruction information. 8-byte fetish aligned by
Used when setting the 8-byte write data in the data register, or when aligning the 8-byte write data using the align circuit according to the write start address, memory reference byte length, and alignment instruction information and setting it in the 8-byte write register. This is an alignment control method that inputs alignment instruction information and a 3-bit memory reference byte length, and a data conversion means that outputs 3-bit data, and the 3-bit output from the data conversion means and a memory access an adder for adding the lowest three bits of the address; a decoder for decoding the output of the adder; and means for sending the output of the decoder as a shift amount instruction signal to the align circuit, and the data conversion means. The alignment instruction information sets the data of the byte length specified by the memory reference byte length including the data of the read start address in the above fetch data register in a right-aligned manner, or the 8-byte write data of the above If the data of the byte length indicated by the memory reference byte length from the right in Set the data of the byte length specified by the memory reference byte length including the start address, with the third byte position of the fetch data register as the limit, or set the data of the left half including the data of the third byte position of the write data. If the data of the byte length indicated by the memory reference byte length existing in the memory reference byte length is specified to be valid, the most significant bit of the 3 bits indicating the memory reference byte length is forcibly set to a logical value. 1", and the alignment instruction information sets the data of the byte length specified by the memory reference byte length, including the data of the read start address, in the fetch data register in a left-justified manner, or The feature is that if the data of the byte length specified by the memory reference byte length from the left in the write data is specified as valid, the data "111" is output. Align control method.