JPS6029785A - Memory - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention is applicable to microprocessor systems using large-capacity memory, particularly microcomputer systems having image memory (
The present invention relates to a memory device suitable for use in image processing systems, graph ink microcomputers, video/video index terminal devices, etc.).

"Background Art and its Problems" In a conventional microcomputer system having an image memory, the image memory is accessed by one of the following two methods.

The first method is to place the image memory in the address space of the CPU, and to directly access it from the CPU by mapping two-dimensional addresses of X and Y to the CPU's memory addresses.

The second method is to place an LSI such as an interface circuit or a graphic processor between the CPU and the image memory, and access the LSI by sequentially outputting information such as two-dimensional addresses and image data to the LSI.

The disadvantage of the first method is that it is not possible to realize a large capacity image memory due to the small address space of the CPU. For example, if a CPU with an address space of 64 bytes is used, the address space is (64 bytes - 256 x 256), so (
It can only accommodate an image memory of approximately 256 dots x 256 dots x 8 pits, and there is no memory area left for programs. For this reason, high resolution,
It is not possible to realize a high gradation image memory.

The disadvantage of the second method is that data writing is realized only by executing instructions a plurality of times, so the procedure is complicated, the processing time becomes long, and the burden on the software increases. For example, data writing is performed by the procedure of outputting an X address from the CPU, outputting the next VcY address, and then outputting pixel data.

Furthermore, graph ink processors have certain problems, such as fixed resolution and limited readout units or directions.
Flexible access has been difficult due to limitations in drawing and reading functions.

``Object of the Invention'' The object of the present invention is to provide a memory device that can accommodate a large capacity image memory and does not constrict the program area.

Still, it is an object of the present invention to construct a memory device that has a simple access procedure from a CPU and can flexibly respond to any type of access.

Furthermore, the present invention is a memory device that allows high-speed access in a specific direction.

"Summary of the Invention" The present invention provides a memory device that includes a CPU and a memory having a two-dimensional structure such as an image memory, and is accessed by a CPUK.

Output and launch an address in one of the X direction or Y direction of the memory by one of a read command or a write command, then output an address in the other direction of the memory by the other command, This is a memory device that is accessed by supplying a composite address of the address in the other direction and the latched address in one direction to the memory.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention, in which 1 is a CPU (central processing unit) such as a microprocessor, which executes a read instruction and a write instruction by executing a program. be able to.

However, in FIG. 1, CPU peripheral circuits such as a ROM for expanding programs are omitted. 2 is 2
It is a dimensional memory. This two-dimensional memory 2 is, for example, an image memory, and one memory address is designated by addressing in the X direction and the Y direction.

A data bus 3 is provided between the CPU 1 and the two-dimensional memory 2. Further, among the address buses 4 from the CPU 1, the third bit address bus 4A is connected to the decoder 5, and the lower bit address bus 4B is connected to the latch 6. The latch address output from the latch 6 and the lower bits of the address bus 4B are supplied as a composite address to the two-dimensional memory 2. The decoder 5 interprets the upper bits of the address supplied through the address bus 4A and extracts necessary information. The output of this decoder 5 is supplied to the latch 6 as a latch enable signal. A read command is supplied from the CPU 1 as a clock for the latch 6 .

A write command from the CPU 1 is supplied to the two-dimensional memory 2.

An embodiment of the invention described above will be explained using time charts shown in FIGS. 2 and 3, respectively. Here, as shown in FIG. 4, a write cycle operation is performed to write data A at the coordinate (X+Y+) position of the two-dimensional memory 2, and data B is written at the coordinate (X2°Y2) position of the two-dimensional memory 2. The operation of reading the data cycle will be explained.

FIG. 2 is a time chart showing the operation of the write cycle. First, the CPU 1 executes one instruction "read address Y1". This allows address bus 4
For example, a 16-bit address is output. This 16
Among the bits, the lower 8 bits correspond to address Y+, .DELTA. in FIG. 2 shows the address of address Y1, and FIG. 2B shows a read command. By executing this command, data is read from the two-dimensional memory 2 as indicated by the broken line in FIG. 2H, but this data is discarded.

Also, the most significant 1 bit out of 16 bits] or several bits including the most significant bit are interpreted by the decoder 5.
If the conditions are met, the latch enable signal shown in FIG. 2C is supplied from the decoder 5 to the latch 6. In other words, the CPU
The read command generated by the execution of the above-mentioned commands from 1 is as follows:
This is a pseudo command that outputs the Y address, and the upper bits are used to distinguish it from the original read command. The latch 6 is supplied with a launch clock (ie, read command) shown in the second diagram, and the latch 6 latches the address Y1 as shown in FIG. 2E.

Next, the CPU 1 executes one instruction: "Write data A t" to address X1. At this time, no read command is generated, and the address X1 is supplied to the two-dimensional memory 2 as a composite address together with the latched address Y1, as shown in FIG. 2F.

At the same time, the write command shown in FIG. 2G is output from the CPU 1, and data A shown in FIG. 2H is output to the data bus 3. Therefore, (X+
, Y+) data A is written to the address.

FIG. 3 is a time chart showing the operation of the lead cycle. First, the CPU executes one command, ``read address r Y2''. As a result, the address Y2 shown in FIG. 3A is generated on the address bus 4B, and the third
A read command shown in Figure B occurs.

Further, the upper bits sent through the address bus 4A are interpreted by the decoder 5 to form the latch enable signal shown in FIG. 3C, and the latch enable signal shown in FIG. As shown in E, address Y2 is latched into latch 6. The execution of this read instruction by the CPU 1 is also for outputting the address Y2, and the read data is ignored as shown by the broken line in FIG. 3G.

Next, CPU 1 puts the
An instruction to add a certain high-order bit P and read this (X2+p) address is executed. Therefore, Figure 3A
As shown in FIG. 3, address X2 is output to the address bus 4B, and an indicator read command is generated as shown in FIG. 3B.

At this time, the upper Pino l-P is interpreted by the decoder 5,
Decoder 5 is easy.

(See Figure 3C).

Therefore, the composite address (X2°Y2
) is given to the two-dimensional memory 2. This allows the third
As shown in FIG. G, data B is read out.

In addition, when accessing the two-dimensional memory 2 along a line parallel to either the X-axis or the Y-axis, one of the X-direction address or the Y-direction address is fixed, and the other All you have to do is update.

This enables high-speed processing. For example, if the launched address Y2 is fixed and the addresses in the X direction are updated sequentially from X2, it is possible to read one line parallel to the X axis using (X2, Yz) as the star i position. .

FIG. 5 shows an embodiment of the present invention in which a swap circuit 7 is provided to enable access along the inside parallel to one selected one of the X and Y axes. l
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The wap circuit 7 inputs the address latched in the latch 6 and the address via the address bus 4B, and outputs these two input addresses as an X-direction address and a Y-direction address of the two-dimensional memory 2. . By using the swap circuit 7 to make the address from the latch 6 an address in the X direction and to make the address via the address bus 4B an address in the Y direction, double-in access parallel to the Y axis becomes possible. On the other hand, if the definition of the correspondence relationship by the swap circuit 7 is opposite to the above, then
Lines parallel to the axis can be accessed. The state of swap circuit 7 is controlled by the output of decoder 5.

"Application Example" The address to be launched may be expressed as an address in the X direction, and the address in the Y direction may be output later to form a composite address.

A write instruction may be used instead of a read instruction to output an address.

"Effects of the Invention" According to the present invention, an image memory is stored in the address space of the CPU by distinguishing between an address in the X direction and 7 addresses in the Y direction by one bit or several bits of the upper bits of the address. It is possible to access a large-capacity two-dimensional memory even when the program area is small, and at the same time, it is possible to prevent the program area from becoming too small. If this invention is applied to an image memory, an image memory with high resolution and high gradation can be realized.

Furthermore, the present invention has the advantage that the access procedure is simple and yet satisfies the basic functions, making it easy to create a two-dimensional memory access program. Therefore, an efficient program such as an assembler can be created, and processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a time chart used to explain the write cycle operation, and FIG.
The figure is a time chart used to explain the operation of the lead cycle, FIG. 4 is a route diagram used to explain the operation of one sudden example of this invention, and FIG. 5 is a block diagram of another embodiment of this invention.・Cpu, 2...°2D memo 艷3-・
・-Data bus, 4.4AI 4B・・・Address node. Agent Tadashi Sugiura Figure 1 Figure 2 H-tall 3-m-: A: Figure 3

Claims (1)

[Scope of Claim] A memory device that is accessed by the CPU and includes a CPU and a memory having a two-dimensional structure such as an image memory. Outputting and latching an address in one of the X direction or Y direction of the memory by one of a read command or a write command, and then outputting an address in the other direction of the memory by the other command; The memory device is configured to access the memory by supplying a composite address of the address in the other direction and the latched address in one direction to the memory.