JPS62232792A - Memory writing and reading device - Google Patents

Abstract

PURPOSE:To enable continuous writing and reading of data of width of two- word length using a memory of width of one-word length by making a memory data bus width of two-word length. CONSTITUTION:When writing data of width of two-word length on a bus 6 in a memory 2, necessary signals are supplied to a signal line 3, an address line 5, two-word length controlling line 20, a clock line 21 and a command 29, and one word of lower side and one word of higher side are made input data to the memory 2 by supplying a latch signal 22 and a selection signal 23 from a controller 11 to a latch 7 and a selector 8. They are written in specified address of the memory 2 by an address line 19 from a controller 28 and a pulse 26 from a controller 12, and taken in an output latch 9 by a clock 24 from the controller 11. Then, the controller 11 changes the signal 23 and controls the selector 8 to make data of the latch 7 input data of the memory 2, and at the same time, sends an information signal to the controller 28, and changes the address line 19 and writes the data in a specified address.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to, for example, a writing/reading device that accesses a memory, and particularly relates to a memory writing/reading device that accesses data continuously.

[Conventional technology]

FIG. 5 is a block diagram of conventional memory writing and data processing equipment. Signal line, (411:t memory output data line, +51H memory address line.

A conventional memory writing/reading device is configured as described above. When writing all data to a memo (for example, January 2), the data is placed on the one-word long-width memory input data bus fi+, and the address is sent to the memory address line (5). Memory data write/read signal line (from 31 to memory (2)
Apply the memory data write signal to.

The data is thereby written into memory (2). or.

When reading data from the memory (2), after putting the address data on the memory address line (5), apply the memory data read signal from the memory data write/read signal line (3) to the memory data read signal line (3). The data of memo January 21 is read out to the memory output data line (4).

[Problems that the invention solves and turns into errors]

In the conventional memory writing/reading device as described above, if the data of 2-word length is continuously glanced at and read from t row 5, the address data of the memory address line (5) at the time of writing is Even if the address data and the address data at the time of reading are the same, the data is placed on the one word long width memory input side data bus (11) and the address data is placed on the memory address line (5).

Memory data write/read signal line (from 31 to memory (
The series of operations of applying the memory data write signal to 21
The memory address line (
5), and a series of operations for applying a memory data read signal from the memory data write/read signal line (31 to the memory (21) must be performed for two words.

The present invention has been made to solve this problem, and after data having a two-word length structure is written into the memory, a: write address data and, in the case of redundant read address data, a series of writes.

The purpose is to speed up the read operation.

[Means for solving problems]

The memory write/read device fjg according to the present invention includes a two-word long memory input III data bus, an input latch that stores one word on the lower side of the memory input side data bus, and an input latch that stores one word on the lower side of the memory input side data bus. a memory input data selector that switches between one word and the output data of the above input latch;
Input the data from the memory input data selector above.1
an IM long-width memory that always outputs data within a designated address according to the memory address designation regardless of the memory loading command or h selling command; and an output latch that stores the memory output data during a memory write operation; A memory output data selector that switches between the output data of the memory and the output data of the output latch, the timing of storing data in the input latch, the data to the memory input data selector; A memory IJ-t that provides all data storage timing and generates a latch information signal that clearly indicates the input latch state.
Set the W data control signal and the address of the above memory to 1@
A memory 1 output data controller that specifies or consecutively specifies two words, compares the write address of the memory with the output address, and outputs a data selection signal of the memory output data selector, and 1@ or 2 to the memory. Memory loading/reading commands that provide Δ loading/reading timing for consecutive words:

[Effect]

In this invention, the memory data bus is made 2 words long, and in the case of memo IJW input, all write data is stored in the input latch, memory, and output latch, and the data of 2 word length is written to the memory in all time divisions. In the case of memory reading, the write address and read address are fully compared and read simultaneously with writing.

〔Example〕

FIG. 1 is a block diagram showing one embodiment of the present invention,
(21 to (5) are exactly the same as the above conventional ones, and (
6) is a 2-word wide memory input side data bus, and (7) is a memory input 11'! , +1 Input latch that stores all 1 word on the lower side of data bus (6), output data of f81H person caratchi (7) and upper OI of memory input side data bus (6)
I Memory input data selector that selects 1 word and outputs it to Memo January 21, (9) is the output latch that stores the output data from Memo January 21 when all memory is written, αoh output latch (9) output data Memory output data selector (lυ is the data storage timing of input latch (7), memory input data selector (81 data selection signal 2 output latch 19+) which selects the output data of memo January 21,
Data storage timing of 1 and input latch (7)
n21 is a memory write data controller that generates an input latch information signal that indicates the state of n21, a memory write/=7 output command controller that provides write timing and read timing for one or two consecutive words to memory (2), 031
is one word on the lower side of the memory input side data bus (6), 1. a
Ill is the upper one word line of the memory input side data bus (6), r+51 is the input latch data output line which is the data output from the input latch (7), and the output data of the (Ish memory input large data selector). Memory data input line, output latch output line which is the output data of the 0η output latch (9), memory output data selector output line whose slope is the output data of the memory output data selector, specify the address data of 69Fi memo January 21 memory address line.

(A) is a 2-word length control line indicating that the data has a 2-word length configuration, Qη is a clock line that is the basis of the data storage timing of the input latch (7) and output latch (9), and @ is the input latch ( 7), an input latch clock that provides the data storage timing, a: memory input data selection signal that selects the ih memory input data selector (8) between the upper one word line and the input latch data output hia51, Cl4 is the output latch ( 9) Output latch clock that provides data storage timing, (c) Input latch information signal that specifies the state of input latch (7), Memory write/read that provides input timing and read timing of @Hamemo January 2) Pulse signal, @ indicates whether memory output data selector αα is on the output latch output line side of output latch (9) or memory output data!
(4) Output data selection signal that selects the
A memory output data controller which specifies the memory address line αIt to the month 21 and provides an output data selection signal @ to the memory output data selector (IG).

@ is a memory write command.

Fig. 2 is an example of the memory write data controller shown in Fig. 1, and cA, r2υ, ■, (c), @, (c), and (c) are the same as in Fig. 1. Yes, (to) iJK
The flip-flop 0υ is an AND logic circuit.

FIG. 3 is an example of the memory write/read command copper 1 device (I side) in FIG.
(7).

Gυ is the same as in Figures 1 and 2, and (to) is O
It is an R logic circuit.

The fourth chest is an embodiment of the memory read data controller (to) in FIG. 1, and n51. α9I (2), Qυ, (c), Kaku, Kan.

(7), C3η is the same as in Figures 1 and 2,
(to) is an adder, a register that stores the data of the Cl4h memory address line (5), (to) is an inverter that inverts the signal of the memory convolution command unit, and 0e is the data of memory address IQ +51 and the register (to). This is a comparator that compares the output data.

In the memory writing/reading device configured as described above, it is possible to quickly introduce and read two words of data into and from the memory. For example, when loading 2-word long width data on the memory input side data bus (6) into the memory (2), the memory data 9 loading/reading signal line (3:, memory address @ (51, 2-word length control line ■, clock line Q
υ, by giving the required signal to the memory write command (a), the lower one word on the memory input side data bus (61) is input by the input latch signal (2) which is the output of the memory convolution data controller (111). The upper one word on the memory input side data bus (6) is taken into the input latch (7) and is selected by the memory input data selector (c) which is the output of the memory input data controller aυ. +81 is selected and becomes the input data of the memory (2), and the memory address line Q!J from the memory read data controller (to) and the memory write/read command controller (L
It is written to a predetermined address in the memory (2) by the memory write/read pulse signal (2) from X8, and at the same time, it is taken into the output latch (9) by the output latch clock Q4 from the memory write data controller αυ. .

Next, the memory input data control 5aυ changes the memory input data selection signal (c) to the memory input data selector (8).
) is controlled so that the data of the input latch (7) is input to the memory (2:).

At the same time, the input latch information signal (c) is sent to the memory read data controller (to) to change the memory address line (llt) and write it to a predetermined address.

When writing data with a width of 2 words to the memory (2) and reading it continuously, the memory data controller αυ, memory write/read command controller aZ,
Under the control of the memory read data controller (to), one high-order word in the output latch (9) is selected and output using the memory output selector concave, and the first and second low-order (+ll) word is output from memory 1.
At the same time as writing to Month 21, select the bladder memory data selector (
L(I selects and outputs.

Note that this invention is applicable to the individual operations of writing two-word long-width data, explaining two-word long-width data, and writing one-word long-width data regardless of the continuous deafening and staring operations of two-word long-width data. Needless to say, writing and reading operations are possible.

〔Effect of the invention〕

As explained above, this invention has the effect of making it possible to continuously infiltrate and retrieve data with a length of two words by fully using the memory with a length of one word, thereby speeding up the memory writing and extraction operations. be.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a diagram showing an entire embodiment of the memory write data controller αυ of FIG. 1, and FIG. 3 is a diagram showing an embodiment of the memory write command controller α2 of FIG. 1. Is Figure 4 the memory of Figure 1? v? FIG. 5 is a block diagram showing a conventional memo IJq5 loading/reading: A head. In the diagram (2) Hamemo! J131fl memory data write/read signal line, (4) is memory output data line, (
5) is the memory address i, f61 is the memory input Mill data bus of 2 words long, (711-j people Carracci, (
81U memory input data selector, (9) is output latch, o, 1lih memory output data selector, αυ is memory write data controller, αX5 is memory write 1 raised command controller, I is lower 1 word line, α41 is Upper side 1
Word line, n! 9 is an input latch data output line, a[i1u
Memory data input line, number is the output launch line, (I9 is the memory output data selector output line, number is the memory address line, ■ is the 2-word length control edge, 29 is the clock line, and the line is the input launch clock, (c) is the memory input data selection signal,
Q4 is the output latch clock, (2) is the input latch information signal, (sub) is the memory 4 loading/reading pulse signal, @ is the output data selection signal, @ is the memory read data controller, @
is memory! This is a built-in command. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A memory input data bus with a width of 2 words, an input latch that stores one lower word of the memory input data bus, and one upper word of the memory input data bus and the output data of the input latch are switched. A one-word long memory that inputs data from the memory input data selector and the memory input data selector mentioned above, and always outputs data within the specified address according to the memory address specification, regardless of memory write commands or read commands. , an output latch that stores the output data of the memory during a memory write operation, a memory output data selector that switches between the output data of the memory and the output data of the output latch, the timing of storing data to the input latch, and the memory A data selection control signal to the input data selector, a memory write data control signal that provides data storage timing to the output latch and generates a latch information signal that specifies the input latch state, and a one-word designation or address of the memory address. a memory read data controller that specifies two words consecutively, compares a write address and a read address of the memory, and outputs a data selection signal of a memory output data selector; a timing for writing one or two consecutive words to the memory; A memory write/read device comprising a memory write/read command controller that provides read timing.