JPS59177793A - Memory controlling system - Google Patents

Abstract

PURPOSE:To enable data writing in nibble mode under single mode state equivalently by performing writing in a memory element in nibble mode when clock is given continuously and generating a timing signal for starting the memory element and a timing signal that set data in the memory element as a set when clock is given singly. CONSTITUTION:In a continuous mode, operation is made in a nibble mode by toggling a CAS signal to one RAS signal by a timing generating circuit 17. In the case of a single mode, writing of data is made by generating a set of RAS signal and CAS signal from a timing generating circuit 17 basing on output of a counter 16 of number of times of data transfer for each time memory starting signal MD is received by switching the counter 16 of number of times of data transfer and timing generating circuit 17 by a switching signal from a single mode discriminating circuit 15. At this time, address of the second and succeeding data is obtained by stepping an address counter 18 by output of the counter of number of times of data transfer.

Description

Detailed Description of the Invention (1) Technical Field of the Invention The present invention relates to a memory device having a memory element that operates in nibble mode, in which a clock is manually incremented and applied to the memory device in order to confirm the operation of the device, etc. The present invention relates to a control method for the storage device when used in single mode.

(2) Prior art and problems FIG. 1 is a block diagram of 11 columns of a storage element operating in nibble mode, in which 1 is a clock generation circuit, 2 is a multi-breather, 3 is a memo), 84 is a row address decoder, 5 is a column address decoder, 6 is a data control unit, 7 is a write buffer, 8 is a data receiver sofa, 9 is a data output buffer, and 10 and 11 are address buses. Signal names A and ~A are address signals, RAS is a row address strobe signal, CAS is a column address strobe signal, W
E represents a write permission signal, Dxx represents input data, and DOυD represents output data. A storage element is activated by RAS, and data is set in the storage element by CAS.

FIG. 2 is a diagram showing the relationship of each signal during writing in the nibble mode of the memory element in FIG. , the signal names are the same as in FIG. H in the diagram
indicates the high level of the signal, and L indicates the low level of the signal.

In Figures 1 and 2, address signals 〇~kq
The 8-bit address information is divided into a row address signal 12 and a column address signal 15 and given in a time-division manner under the control of the RAS and CAS clocks. Of this address information, a row address signal (8 bits) passes through the address bus 10 and enters the row address decoder 4, where it is decoded and one row of the 256 rows of storage elements is selected. On the other hand, the column address signal (8 bits)
After the bits enter the column address decoder 5, they are decoded and one of the 64 columns (one column has 4 bits) is selected. Further, the lower two bits are input to the data control section 6. To write data, normally the RAS signal is set to L and then the C
By setting the AS signal to L, data is accessed in units of 4 bits, but when writing in nibble mode, as shown in Figure 2, when the RAS signal is in the L state, the CAS signal is By changing the value to H and then to L (toggle), the lower 2 input to the data control unit 6 is
By incrementing the bit address within the data control unit 6, access is performed in units of bits.

In the case of writing in such nibble mode,
When the device's clock supply mode is set to single mode, fi CA
Since the S signal is toggled, there is a possibility that the RAS signal remains at L for a long time, and during that time, it is not possible to proceed to other operations.

On the other hand, the memory element needs to be refreshed every fixed period of time (4 mS in this example).

However, for the above reasons, it is impossible to refresh the stored contents within a predetermined period of time, so there is a drawback that the stored contents are not guaranteed.

Furthermore, if the refresh is controlled to be executed with priority, the RAS signal must be returned to '5I:H before all the toggling of the CAS signal is completed, so the write result in nibble mode is not guaranteed. There were drawbacks.

(5) Object of the Invention In view of the above-mentioned drawbacks of the prior art, the present invention relates to a control system for a storage device that allows writing in nibble mode to be performed normally even in single mode and guarantees data.

(4) Structure and object of the invention According to the present invention, as described in the claims, in a storage device that writes data transferred in a time-division manner to a storage element that operates in a nibble mode. A circuit that generates the timing signal to start the device and the timing signal to set data in the storage device, a circuit that identifies whether the clock is applied continuously or sporadically, and a circuit that counts the number of data transfers. and an address counter that increments each time data is transferred with the initial value of the first write address of the data as the initial value. When the clock is applied continuously, writing to the memory element is performed in nibble mode, and when the clock is applied only once. By generating a timing signal for activating the storage element and a timing signal for setting data in the storage element as a set, the address counter is activated each time data is transferred. A storage device 1 characterized in that writing is performed in a storage element at a position indicated by
] This will be accomplished in your own way.

(5) Embodiment of the invention FIG. 6 is a block diagram of an embodiment of the storage device according to the invention, in which 15 is a single mode identification circuit, 16 is a data transfer counter, 17 is a timing generation circuit, and 18 is a block diagram of an embodiment of the storage device according to the invention.
is an address counter, 19 is an address register, 20 is a write data register, 21 is a storage element, and 22 is a read data register. The signal names are: SM is a single mode display signal, MD is a memory activation signal, and AD is an address signal. , WD represents write data, and RD represents read take.

In FIG. 3, in the case of continuous mode, the timing generation circuit 17 toggles the CAS signal for 91 times of the RAS signal to operate in = full mode, but in the case of single mode, the single mode identification circuit 15
Data transfer count counter 16 according to the switching signal from
By switching the timing generation circuit 17 and the timing generation circuit 17, each time the memory start signal MD is received, the timing generation circuit 17 generates a set of RAS signal and CAS signal based on the output of the data transfer counter 16, and writes data. Perform the action. At this time, the address of the second and subsequent data is obtained by incrementing the seat address counter 18 based on the output of the data transfer number counter.As explained above, in the circuit of this embodiment, under single mode When writing data to a storage element in nibble mode, the data to be transferred in a time-division manner is controlled individually by the RAS signal and the CAS signal, and is written outside the storage element based on the start address where the data is to be stored. Since the data is written to the generated address location, the RAS signal does not go to H level every time one piece of data is written, and other operations can be accepted, so refreshing of the memory element will not be hindered. None.

(6) Effects of the Invention The storage control method of the present invention can be easily realized with a simple circuit, and can impose constraints on data writing in nibble mode under single mode conditions during device maintenance and fault searching. Since the memory element can be refreshed irrespective of single-mode step-by-step operation or the like during this time, the data is reliably guaranteed, which is very effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an example of a memory element operating in nibble mode, Fig. 2 is a diagram showing the relationship of each signal when writing in the nibble mode of the memory element of Fig. 1, and Fig. 6 is a diagram of the present invention. FIG. 1 is a block diagram of one embodiment of a storage device according to. 1...Clock generation circuit, 2...Multiplexer, 3...Memory, 4...Row address decoder, 5...Column address decoder , 6...Data control section, 7...Write buffer, 8...Data input cover sofa, 9.
...Data output cover sofa, 10.11...
Address bus, 12...Row address signal, 13
...Column address signal, 141-14.・・・・・・
...Input data, 15...Single mode identification circuit, 16...Data transfer number counter, 17
...Timing generation circuit, 18...Address counter, 19...Address register, 2
0...Write data register, 21...
Memory element, 22...read data register I,
・□1-”q

Claims (1)

[Claims] In a memory device that writes data that is transferred in a time-division manner to a memory element that operates in nibble mode, there is a circuit that generates a timing signal to start the memory element, a timing signal to set data in the memory element, and a clock. A circuit that identifies whether data is given continuously or sporadically, a counter that counts the number of data transfers, and an address counter that increments each time data is transferred, with the initial value being the first write address of the data. and when the clock is applied continuously, the data is written to the storage element in nibble mode, and when the clock is applied sporadically, the timing signal and data for activating the storage element are set in the storage element. Signal and 1
1. A storage device control method, characterized in that each time data is transferred, data is written into a storage element at a position indicated by the address counter.