JPS62230172A - Liquid crystal display type image receiving device - Google Patents

Abstract

PURPOSE:To heighten density of picture elements and to prevent flicker and crosstalk of images by making non-interlaced scanning driving of a liquid crystal display type image receiving device having non-linear elements. CONSTITUTION:In a shift register 16, AC signals of 1H move excepting timing of selecting period. In the case where control input of a dual analog switch 14 is low, one is closed, and the output of a shift register 15 becomes terminal output. In the case of high, another is closed, and AC signals NEL of nonselection intermediate level are made output. As the timing of change of the signals NEL and the timing of change of output of a register 16 are synchronous, the change of signals NEL differs every 1 field in output. However, the level of signals NEL different from adjoining signal is outputted. The output of a selecting system register 15 adopts normal signals and inverted signals alternately at every stage and inputs to the switch 14. For instance, Y1 is normal, and Y2 is inverted. Thus, the adjoining output of the driving circuit becomes opposite phase, and signals for which period of selection becomes 1 frame can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for driving a liquid crystal display type image receiving device. The image receiving device referred to herein refers to a device that inputs a video signal such as a video signal from a television set or a video signal from a computer and displays it as an image. Although a large number of images are required to be able to display normal television images, the present invention utilizes a liquid crystal display device in which a line-displacement type element is arranged in each pixel to realize display in a highly crowded room.

Discharged wire type elements include varistor elements, metal-insulator-metal (
MIM) elements, diode elements, discharge tube elements, etc., which have nonlinear characteristics such as high resistance in the low voltage region and low resistance in the high voltage region.

By arranging a non-linear element in each pixel, the number of changes in the multiplex drive can be greatly increased. It also becomes possible to display television images.

[Summary of the invention]

In a liquid crystal display type image receiving device having a non-linear element, the present invention increases pixel density by driving by non-interlaced scanning without inputting an interlaced scanning signal, and the scanning It pole is different from the drive signal of the number electrode. The alternating current method is carried out by changing the polarity for every % scan, thereby achieving prevention of image crosstalk and flicker.

[Conventional technology]

A conventional driving method for a liquid crystal display image receiving device having a non-linear element is described by rK-Niwa et al, +SIDSy.
mp, Digest '84. As presented in Pj04J. That is, one scanning period is divided appropriately, and each signal electrode corresponding to the video information in the divided period is
A video information signal is applied for each scan, and a drive signal that takes a selection potential and a non-selection potential is applied to the scan electrode, and as a whole, alternating current driving is performed with inversion for each frame period and each field. . Further, each scanning electrode is scanned once per field, and the number of scanning electrodes is half that of an interlaced scanning line, and the vertical resolution is reduced.

[Problem that the invention seeks to solve]

When driving a larger image receiving device, it is inappropriate to allocate two scan lines of interlaced scanning to one scan electrode as it will make the screen rough, so it is inappropriate to drive by making one scan line correspond to one scan electrode. There is a need to. When the prior art is applied to interlacing, the polarity is reversed every two fields in one frame, that is, two frames are exchanged, and the period is doubled.

Flicker is caused by the alternating current cycle and the asymmetry of the element, and in two-frame alternating current, it is 16H2, which causes considerable flickering due to the responsiveness of the liquid crystal. Further, crosstalk occurs because during the non-selection period, a signal of non-selection information is mixed in by the amount divided by the capacitance of the non-linear element and the liquid crystal @ element, causing blurring in the image. In order to suppress this, it is necessary to reduce the capacitance of the element and increase the capacitance of the pixel, but this is not a complete solution as there is a limit on the pattern and the drive voltage also increases.

Therefore, the present invention aims to solve these problems.
The purpose is to provide a driving method that makes pixels highly dense in accordance with interlaced scanning and prevents image flicker and crosstalk.

[Means for solving problems]

The driving method of the liquid crystal display type image receiving device of the present invention is that the liquid crystal display type image receiving device is composed of a) a drive circuit that inputs a video signal and forms a drive signal, a liquid crystal display device, and a member that connects the two. b) one substrate sandwiching the liquid crystal of the liquid crystal display device has a large number of scanning electrodes arranged parallel to the scanning line direction, and C) the other substrate has a large number of scanning electrodes arranged perpendicular to the scanning line direction. d) In a liquid crystal display type image receiving device in which the intersecting portions of these electrodes are used as pixels and a nonlinear element is arranged in each pixel, e) One scanning period is divided by an appropriate clock source and the division is performed. The video information for each period is accumulated, and each corresponding signal a
A signal of video information is applied to the pole twice per one scan, and f) the drive No. 2 applied to the scan '[11 pole] takes the selection potential for one half of the scan period, and does not apply the selection potential for the other periods. takes a non-selection potential, g) The signals of the scanning electrode and signal electrode are AC signals, and 1
In the case of a frame-two-field scanning system, the polarity is reversed in each field, and the polarity is opposite for adjacent scanning electrodes, and h) the polarity is reversed for two adjacent scanning electrodes for one scanning per field. However, in alternating fields, the combination is repeated in a hierarchical relationship.

[Effect]

According to the above configuration of the present invention, the signals of the scanning electrodes and the signal electrodes are AC signals, and the polarity is reversed every % scan, so that the mixture of image information when not selected is also reversed every %-1 element. However, since the same information is applied in the forward and reverse directions, the crosstalk is canceled out over time, so virtually all crosstalk is almost eliminated.Also, since the polarity differs for each scanning electrode on the screen, The flicker that is occurring becomes apparently unobservable, and the flicker is effectively eliminated.

Furthermore, two scan electrodes are combined in one scan for each field, but in alternate fields, the vertical relationship of the combination is changed, and in two fields in one frame, each scan has different information depending on the pole, so interlace scan is used. Corresponding solution IF
! 0 [Embodiment] @1 Figure is a signal waveform diagram of an embodiment of the present invention.

If the signal VIDt- is a video signal of 0 color video, 3tIilI type is required, but one type is shown as an example.

The signal DATA is an A/D converted signal VID. Normally, 16 gradations of brightness are sufficient, and 4-bit A/
For D conversion, four types of DATA signals are required, but one type is shown as an example.

No. 1g STA specifies the timing to start sampling the video signal DATA, and is a start signal for the first stage of the shift register.

The signal LOAD specifies the timing at which part of the sampled video information is latched and stored.

Generated after the completion of sampling during 1H.

The duty ratio of the signal electrode signal changes depending on the brightness of the video information, and the signal that resets the duty count is the signal R8T. The figure shows that reset is performed twice during 1H. Furthermore, once every two times, the timing coincides with the timing of the signal LOAD.

The signal AC8 is an alternating current signal with a 1H period, and determines the alternating current between the signal electrode signal and the scanning electrode signal. The switching timing is defined by the rising edge of the signal R8T.

Signal Xi is the output applied to the first signal electrode,
Positive and negative information alternately appear, resulting in an alternating current waveform, which is inverted every KH. The shaded area in the diagram is data that is determined by video information.
Indicates that the Tey ratio changes. Rewriting of the duty ratio of signal Xi is defined by signal R8T, and the polarity is determined by signal AC.
However, rewriting of video information is stipulated in Section 8.
Since this is carried out in D, the same information with different polarities is combined and output.

Signal Y j , Y j−1−t v Y j +z
Scan! With the drive signal applied to the poles, from the fifth to j+!
It represents the song.

In this case, we assume the same number of scanning lines as CRT,
The number will be 400 to 500. The circled portion of the signal waveform is the selected period, and the rest are non-selected periods.

The selection period is different for each scan IIcW, and is sequentially shifted by 5AH. Adjacent electrodes have different polarities, and the polarity is different for each field. Also, the non-selection potential is different before and after the selection period, which improves retention characteristics. ing.

Xl-Yj+1 is a voltage waveform applied to the pixel (i?j-)-t). It can be seen that writing is performed to fill one feed μ.

2, 3, 4, and 5 are circuit diagrams of embodiments of the present invention, in which FIG. 2 is a control signal system, FIG. 3 is a scanning electrode drive signal system, and FIG. 4 is a circuit diagram of an embodiment of the present invention. Signal electrode drive signal system, FIG. 5 shows a part of the circuit for the signal electrode drive signal. In Figure 2, H
8YNC is the horizontal synchronization signal, VSYNC is the vertical synchronization signal,
VID is a video signal. Since these are formed using well-known circuits, they are treated as already prepared.

Signal f (SYNC is PLI, is input as a comparison signal of LCO circuit 1. This oscillation output is input to X counter decoder 2, and one of its output signals, HCP, is input to PL
L, fed back to VCO circuit 1, signal H8YN
Synchronize with C. The output of PLL and VCO circuit 1 passes through the buffer and amplifier to the clock signal XC of the X driver.
It becomes K.

The X counter and decoder 2 also output a signal R8T which is synchronized with the horizontal synchronization but has a double frequency, a memory write signal LOAD which is synchronized with a part of the signal R8T, and a signal STA which sets the timing of image writing in horizontal scanning. .

The signal R8T passes through a buffer and becomes the clock signal YCK of the scanning electrode drive circuit.

The vertical synchronizing signal VSYNC is shaped at the rising edge of the signal R8T to become the signal vSP. The reset input of the binary counter 4 is the signal vSP, the clock input is the signal R8T, and the output thereof can determine the timing corresponding to the vertical position of the 17 screens. This output is designated as signal YSP.

The signal vSP is frequency-divided by a flip-flop 5 to form a field inversion signal FR.

The signal FR is delayed through all the clip-flops 6 by the signal YSP that sets the timing of vertical scanning image writing, and its output is sent to the two-stage flip-flop 7.
．． 8, the signal R8T is delayed by the falling edge of the signal R8T. If we take the exclusive OR of these output signals, we get the signal F
Signal Y that outputs a pulse of %H width immediately after the polarity change of R
ST can be formed. The signal R8T is input as a clock signal to the flip-flop 9 and divided to form a data signal YSc that determines the selection level change and selection timing of the scanning electrode drive circuit. Determine the timing of your selection.

The output YSE of the flip-flop 6 becomes a data signal that determines either the selection of the scanning electrode signal or the non-selection level after the selection.

When the signal YSE is delayed and ANDed with its inverted signal, a %H width pulse is output only when the signal FR is in the high state. If this is used as a set input to the flip-flop 10 and a branch signal of the signal RST is formed, an AC signal AC8 with a 1H period, which is in a constant state for each field, is output.

The dual analog switch 11 has an intermediate potential 2a
The non-selection level of X is set to AC.

The potential vN is between low and GND, and the potentials VM high and G
It is between ND and switched by alternating current signal AC8.

The video signal V I Ilt is converted into a 4-bit digital signal by the A/D conversion circuit 12 . DllD2 for each
, Ds, and D4, and are collectively referred to as DATA. V
AD11VAD2 is a reference voltage for A/D conversion. Further, VHjVL is a potential that determines the positive and negative off-potentials of the signal electrode signal. Switching is performed using the signal AC8 to form an off signal VOFF. The same applies to the on signal VON.

Figure 3 shows dust in the scanning xi drive circuit, Yl*Y21...
... are supplied to the scanning electrodes of the display body. The circuit configuration consists of a dual analog switch group 14, a selection shift register 15, and a control shift register 16. Both shift register clock signals are YCK, and information moves every y2■l. shift register 16
In this case, the 1H AC signal moves except at the timing of the selection period. When the control input of the dual analog switch is low, one of the analog switches is closed and the output of the shift register 15 becomes a terminal output, and when it is high, the other analog switch is closed and the non-selected intermediate level AC signal NEL is output. shall be. Since the timing of the change in the signal NEL and the timing of the change in the output of the shift register 16 are synchronized, the change in the output signal NIL differs for each feed p. However, the adjacent signal is
Another level p of the signal NEC is output.

The output of the selection shift register 15 alternately adopts a positive signal and an inverted signal for each stage and inputs them to an analog switch. For example, Yl is positive υ, and Y2 is inverted.

In this way, the output of this drive circuit is such that adjacent circuits have opposite phases, and a signal having a selection period of one frame can be obtained.

Figure 4 shows the signal it pole drive circuit, Xi tX2...
... is supplied to the signal electrode of the display body. The circuit configuration includes a multi-stage shift register 2o and a store circuit 2.
1. The clock signal of the shift register '10 is XCK, the start data signal is STA, and the output of each stage generates a pulse at a timing corresponding to the horizontal position of the screen. Each bye input/output is input to a store circuit. A detailed diagram of the store circuit is shown in FIG.

Each pulse output becomes a strobe signal for the latch circuit 22,
Each data signal Dl, D! , f)s, D4
to hunna. The latched data No. 13 becomes an input to the second-stage latch circuit 25, and when writing on the -scan is completed, a pulse of signal LOAI) is generated and latched. In this way, the output of the latch circuit 25 does not change during 1H.

The signal CPX is a signal that generates 15 pulses during 5AI, and sets a regular interval between the pulses of the signal R8T, and the interval depends on the nature of the display device. .

Signal CPX is the clock signal for counter 24, and the counter is reset with signal RST.

Counter 24 is a 1,000-bit binasaw,
The output corresponds to the bit order, is paired with the output of the latch circuit 23, and is input to the matching circuit 25. That is,
When the count matches the data content, the output of the matching circuit 25 becomes high. This output is the Noah latch circuit 2
60 set signal and its output remains high. The signal R8T becomes a reset signal and returns the output of the NOR latch circuit to low in %H cycles. This output becomes the dual analog switch controller) V signal, and the matching circuit goes high. In the case of a pond, the output is the same as YON, and in the case of a pond, it is the same as voty.

In this way, the digital signal of the sampled and held image changes its attributes every 'y2H, and is applied to the signal electrode by controlling the pulse width.

Furthermore, as can be seen from FIG. 1, according to the circuit of this method, in the first field, the same information is applied to the scanning electrodes Yj and Yj+1 with opposite polarities, but in the second field, the scanning electrodes Yj and Yj+1 are applied with the same information ! The same information is applied to the poles Yj+1 and Yj+2 with the polarity reversed.

That is, the polarity is reversed in each field, and the polarity is reversed for adjacent scan electrodes, and two adjacent scans are combined for one scan in each field.
In alternating fields, the hierarchical relationship of the combinations will be changed.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to perform non-interlace scanning driving of a liquid crystal display type image receiving device having a non-linear element, and the I11!
I can display images. In other words, if all scanning lines are selected in one field and the first and second fields are combined, different information will be included in the entire scanning, and the resolution (
9) is ensured.

Furthermore, display flicker is observably eliminated due to polarity inversion drive for each scan. At the same time, the appearance of cross-I-reflection, which is a drawback of liquid crystal displays having non-linear elements, can be substantially eliminated by applying a combination of forward and reverse video signals, thereby canceling out non-selected information.

It is well known that liquid crystal display type image receiving devices can be made thinner, lighter in weight, and consume less power than CRTs, but they have had problems with resolution. According to the present invention, it is possible to obtain a liquid crystal display that is equivalent to a CRT in terms of steel quality, and is of great industrial benefit.

[Brief explanation of drawings]

FIG. 1 is a signal waveform diagram of an embodiment of the present invention. vID...Video signal. D AT A...
...A signal obtained by digitizing a video signal. S T A ・
...Start signal for sample hold. L
OAD: A signal that latches information every 1H. R
ST-...Clock signal for determining the timing of polarity change and for scanning electrode drive signals. ACS
-...Signal for determining polarity OXi...Signal electrode signal. Yj+Xj+1. YJ +2-...Scanning electrode signal. FIG. 2 is a circuit diagram of the control signal system of the embodiment. FIG. 3 is a drive circuit diagram of a scanning electrode signal system according to an embodiment. FIG. 4 is a drive circuit diagram of a signal electrode signal system according to an embodiment. FIG. 5 is a detailed diagram of the store circuit 21 in FIG. 4. that's all

Claims (1)

[Claims] (1) A liquid crystal display type image receiving device consisting of a) a drive circuit that inputs a video signal and forms a drive signal, a liquid crystal display device, and a member that connects the two, and b) a liquid crystal display of the liquid crystal display device. c) The other substrate has a large number of signal electrodes arranged perpendicular to the scanning line direction, and d) These In a liquid crystal display type image receiving device in which the intersection of the two is defined as a pixel and a non-linear element is arranged in each pixel, e) one scanning period is divided by an appropriate clock source and video information is accumulated for each divided period, Applying video information signals twice per one scan to each corresponding signal electrode; f) driving signals applied to the scanning electrodes during two scan periods;
g) The signals of the scanning electrode and the signal electrode are AC signals, and the signal of the scanning electrode and the signal electrode is an AC signal.
In the case of a frame-two-field scanning method, the polarity is reversed in each field and the polarity is opposite for adjacent scan electrodes, h) two adjacent scan electrodes are combined for one scan per field; , a liquid crystal display type image receiving device characterized by changing the vertical relationship in which fields are combined in alternating fields.