JPS62230089A - Manufacture of enamelled wiring board - Google Patents

Manufacture of enamelled wiring board

Info

Publication number
JPS62230089A
JPS62230089A JP7384186A JP7384186A JPS62230089A JP S62230089 A JPS62230089 A JP S62230089A JP 7384186 A JP7384186 A JP 7384186A JP 7384186 A JP7384186 A JP 7384186A JP S62230089 A JPS62230089 A JP S62230089A
Authority
JP
Japan
Prior art keywords
plating
enamel
wiring board
roughening
electroless plating
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7384186A
Other languages
Japanese (ja)
Inventor
肇 中山
津山 宏一
岡村 寿郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP7384186A priority Critical patent/JPS62230089A/en
Publication of JPS62230089A publication Critical patent/JPS62230089A/en
Pending legal-status Critical Current

Links

Landscapes

  • Insulated Metal Substrates For Printed Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、はうろう配線板の製造法に関するものである
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method for manufacturing a crawling wiring board.

(従来の技術) 従来、はうろう基板への回路形成は金属ペーストをスク
リーン印刷した後500℃以上の温度で焼き付ける厚膜
法を用いていた。
(Prior Art) Conventionally, a thick film method has been used to form a circuit on a floating substrate by screen printing a metal paste and then baking it at a temperature of 500° C. or more.

しかし、厚膜法では(i)スルーホール内印刷が困難で
あること、(11) ファインパターンが回連であるこ
と、(iii )高温での焼成を繰り返す(スルーホー
ル付両面板の場合3回)ため基板にそりやクラック等の
発生するおそれがあること、(iv )空気中焼成する
ためには貴金属ペーストを使うためコスト高になること
、(V)tlペースト等を焼成する場合は窒素雰囲気の
管理が困難な上900℃を越える高温で焼成するためほ
うろう層の耐熱温度を上回るか、または金属芯の変態点
を越える(鉄のα−γ変態点=91O℃)ため歪が発生
しやすいことなどの問題点があった。
However, with the thick film method, (i) it is difficult to print inside the through holes, (11) the fine pattern is repeated, and (iii) the firing at high temperatures is repeated (three times in the case of double-sided boards with through holes). ), there is a risk of warping or cracking on the board; (iv) noble metal paste is used for baking in air, which increases the cost; and (V) a nitrogen atmosphere is required when baking tl paste, etc. In addition, it is difficult to control the temperature, and since it is fired at a high temperature of over 900℃, it exceeds the heat resistance temperature of the enamel layer or the transformation point of the metal core (α-γ transformation point of iron = 91O℃), which tends to cause distortion. There were problems such as:

このような問題点に対して、はうろう基板表面にめっき
を行なう方法提μされている。例えば、特開昭53−5
438号公報、特開昭60−195078号公報に示さ
れる方法であるが、はうろう基板表面の粗化を、前者は
フッ酸、後者は水酸化ナトリウム融解液の処理で行って
いる。
To solve these problems, a method has been proposed in which the surface of the floating substrate is plated. For example, JP-A-53-5
438 and Japanese Patent Application Laid-Open No. 60-195078, the surface of the floating substrate is roughened by treatment with hydrofluoric acid in the former and with a sodium hydroxide melt in the latter.

(発明が解決しようとする問題点) フッ酸や水酸化ナトリウム融解液を用いると腐食力が強
すぎるためほうろう基板表面の結晶質相、非結晶質相の
区別なく溶解され粗化面の凹凸の制御が困難な上に、表
面付近に脆弱層を形成するため、その後に施す無電解め
っき膜がこの脆弱層と共に剥離し安定的な密着力を得る
ことが困難であった。また、フッ酸や水酸化ナトリウム
融解液は散機いが危険である。
(Problem to be solved by the invention) When hydrofluoric acid or sodium hydroxide melt is used, the corrosive power is too strong, so the crystalline phase and amorphous phase on the surface of the enamel substrate are dissolved without distinction, and the unevenness of the roughened surface is In addition to being difficult to control, since a brittle layer is formed near the surface, the electroless plating film applied afterwards peels off along with this brittle layer, making it difficult to obtain stable adhesion. In addition, hydrofluoric acid and sodium hydroxide melts are dangerous, even if they are scattered.

本発明は、無電解めっき膜の密着力に優れるほうるう配
線板の製造法を提供するものである。
The present invention provides a method for manufacturing an enameled wiring board with excellent adhesion of an electroless plated film.

(問題点を解決するための手段) 本発明は、金属芯を結晶質相と非晶質相とから成る結晶
化釉ほうろう層によって被覆したほうろう基板を用い、
結晶質相に比べ非晶質相の溶解速度の大きい粗化液で表
面を粗化しめっき膜との密着性を促進させ、次にこの粗
化形状を破壊しないように無電解めっき反応を開始させ
ることのできる触媒を付与した後無電解めっきを行なう
ことでほうろう基板上に密着性のよいめっき膜を形成す
る。この後、回路部以外にめっきレジストを形成し電気
めっきを行なうことで短時間に回路の膜厚を増大させ、
その後エツチングレジストや防錆膜などの半田めっきを
行い、最後にめっきレジストを除去し、エツチングを行
なうことで回路を形成する。
(Means for Solving the Problems) The present invention uses an enamel substrate in which a metal core is covered with a crystallized glaze enamel layer consisting of a crystalline phase and an amorphous phase.
Roughen the surface with a roughening solution that dissolves the amorphous phase at a higher rate than the crystalline phase to promote adhesion to the plating film, and then start the electroless plating reaction without destroying this roughened shape. By applying a suitable catalyst and performing electroless plating, a plated film with good adhesion is formed on the enamel substrate. After this, a plating resist is formed on areas other than the circuit area and electroplating is performed to increase the film thickness of the circuit in a short time.
After that, solder plating such as etching resist and anti-corrosion film is applied, and finally the plating resist is removed and etching is performed to form a circuit.

本発明で用いる粗化液は中性もしくは中性に近い水溶液
で、結晶化ガラスの組成の異なる相に対して溶解性が異
なるものである。
The roughening liquid used in the present invention is a neutral or nearly neutral aqueous solution, and has different solubility in phases of different compositions of crystallized glass.

一般に、酸化物の耐水、耐酸、耐アルカリ性は以下のよ
うになっている〔成瀬省著「ガラス光学」 (昭33)
共立出版〕。
In general, the water resistance, acid resistance, and alkali resistance of oxides are as follows [Glass Optics by Sei Naruse (1968)
Kyoritsu Publishing].

耐水性: Zr0z > A1ga3> Tie、 >
 ZnO>MgO> PbO> CaO> BaO耐酸
性: Zr0z > Al2O,> ZnO> CaO
>Tiot> PbO> MgO> BaO耐Na0I
I性: Zr0z ) Al*03.Ti0z、ZnO
,CaO耐NazCO+性: ZaOz ) AIzO
ff、Ti0z、ZnO> Cab。
Water resistance: Zr0z > A1ga3 > Tie, >
ZnO>MgO>PbO>CaO>BaO Acid resistance: Zr0z>Al2O,>ZnO>CaO
>Tiot>PbO>MgO> BaO resistance Na0I
I property: Zr0z) Al*03. Ti0z, ZnO
, CaO NazCO+ resistance: ZaOz ) AIzO
ff, Ti0z, ZnO>Cab.

Bad、 PbO,MgO 結晶化ガラス中の結晶質成分としてBad、 Cab。Bad, PbO, MgO Bad and Cab as crystalline components in crystallized glass.

MgO,PbO等を用いた場合、結晶質相は強酸、強ア
ルカリの両方に溶解されやすい。中性または中性に近い
水溶液で非晶質相を強く溶解し、結晶質相を残すような
処理をすることで、その後に施すめっき膜との密着を大
きくするような粗化面を形成することが出来る。
When MgO, PbO, etc. are used, the crystalline phase is easily dissolved in both strong acids and strong alkalis. By strongly dissolving the amorphous phase with a neutral or near-neutral aqueous solution and performing a treatment that leaves the crystalline phase, a roughened surface is formed that increases adhesion with the plating film that will be applied afterwards. I can do it.

結晶化ガラスは結晶質相と非晶質相とより成っているが
、結晶質相が数種の相(組成)より成っている場合があ
り、本発明では結晶質相の少なくとも一つの相に比べ非
晶質相の溶解速度の大きい粗化液で粗化をする。その結
果、粗化面には結晶質相の少なくとも一つの相が残り、
その後に施すめっき膜との密着力を大きくするように粗
化面を形成することが出来る。
Crystallized glass consists of a crystalline phase and an amorphous phase, but the crystalline phase may consist of several types of phases (compositions), and in the present invention, at least one of the crystalline phases Roughening is performed with a roughening solution that has a higher rate of dissolving the amorphous phase. As a result, at least one crystalline phase remains on the roughened surface,
A roughened surface can be formed so as to increase adhesion to a plating film applied thereafter.

本発明では、例えば、ホウ素、ケイ素、マグネシウム、
バリウムを15 < BtOx < 35、IQ<Si
O□<30.40 < Mg + CaO+ BaO<
 65の割合(モル%)で含む結晶比軸が使用出来る。
In the present invention, for example, boron, silicon, magnesium,
Barium 15 < BtOx < 35, IQ < Si
O□<30.40<Mg+CaO+BaO<
A crystal ratio axis containing a ratio of 65% (mol %) can be used.

このほうろう層はBaOを多く含む結晶質相と、ホウケ
イ酸ガラス質権から成る。結晶質相は長さ20、crm
以下の針状で非晶質マトリック中に無数に分散している
This enamel layer consists of a BaO-rich crystalline phase and a borosilicate glass pledge. The crystalline phase has a length of 20, crm
They are needle-shaped and are dispersed in countless numbers in the amorphous matrix.

粗化は、例えば、フン化ナトリウム、フッ化カリウム、
フッ化アンモニウム、フン化ホウ素酸、テトラフルオロ
ホウ酸アンモニウム等のフン化物塩水溶液、無電解ニッ
ケルめっき液「ブルーシューマーj (pH6,4)(
日本カニゼン製商品名)等により行うことが出来る。粗
化液のp旧よ2〜13、好ましくは5〜10、更に好ま
しくは6〜9である。
For roughening, for example, sodium fluoride, potassium fluoride,
Fluoride salt aqueous solution such as ammonium fluoride, fluoroboric acid, ammonium tetrafluoroborate, etc., electroless nickel plating solution "Blue Schumer J (pH 6,4) (
This can be done using Nippon Kanizen Co., Ltd. (trade name), etc. The p of the roughening liquid is 2 to 13, preferably 5 to 10, more preferably 6 to 9.

無電解めっき反応を開始させることの出来る触媒として
は、絶縁基板面に無電解めっきにより回路形成を行う前
処理として使用される通常の触媒、特にアルカリ性、中
性のpb系等の触媒が好ましい。
As a catalyst capable of starting an electroless plating reaction, a usual catalyst used as a pretreatment for forming a circuit on an insulating substrate surface by electroless plating, particularly an alkaline or neutral PB-based catalyst is preferable.

めっきレジストは印刷法または現像法等で形成される。The plating resist is formed by a printing method, a developing method, or the like.

無電解めっき、電気めっき、半田めっきは印刷配線の製
造で、絶縁基板面に回路形成を行うための通常の無電解
、電気、半田めっき液により行うことが出来る。
Electroless plating, electroplating, and solder plating are used in the production of printed wiring, and can be performed using conventional electroless, electric, and solder plating solutions for forming circuits on the surface of an insulating substrate.

実施例 第1図により説明する。Example This will be explained with reference to FIG.

BzOs□20.5iOz□15. Mg0=55. 
Ba0=5.5rO=5の組成(モル%)の結晶化釉ほ
うろう層lによって被覆したほうろう基板を用いた。2
は金属芯である(第1図(a))。粗化液としはフッ化
ナトリウム20 g / j!水溶液(pH7,8)を
使用した。スルーホール付はうろう基板を80℃の上記
粗化液に50分間浸漬させた後Na0llを1g/l含
むpbシーディング液(pH10,2)に2分間浸漬し
、次に同じくアルカリ性の還元処理液(pH11,2)
に1分間浸漬した(第1図(b))後、ホルマリンを還
元剤とする無電解銅めっき(plI 12.3 )で基
板全面に洞めっき被膜3を形成した(第1図(C))。
BzOs□20.5iOz□15. Mg0=55.
An enamel substrate coated with a crystallized glaze enamel layer l having a composition (mol %) of Ba0=5.5rO=5 was used. 2
is a metal core (Fig. 1(a)). As a roughening liquid, use 20 g/j of sodium fluoride! An aqueous solution (pH 7,8) was used. The substrate with through holes was immersed in the above roughening solution at 80°C for 50 minutes, then immersed in a PB seeding solution (pH 10, 2) containing 1 g/l of Na0ll for 2 minutes, and then subjected to the same alkaline reduction treatment. liquid (pH11,2)
After being immersed in water for 1 minute (Fig. 1(b)), a hollow plating film 3 was formed on the entire surface of the substrate by electroless copper plating (plI 12.3) using formalin as a reducing agent (Fig. 1(C)). .

この基板に回路部以外にめっきレジスト4を形成しく第
1図(d))、電気めっき5を行なうことで回路のnり
厚を増大させ(第1図(e))、つずいて電気半田めっ
き6を行い(第1図(r))、最後にめっきレジストし
を除去しく第1図(g ) ) 、アンモニアを主剤と
し、酸化剤としてNaCl0z、pH緩衝剤としてNl
1411CO1などの入ったエツチング液(pH8,2
)でエツチングによる回路部以外のめっき被膜除去によ
り回路を形成した(第1図(h))。
A plating resist 4 is formed on this board in areas other than the circuit area (Fig. 1(d)), and electroplating 5 is performed to increase the thickness of the circuit (Fig. 1(e)), followed by electrical soldering. Plating 6 is performed (Figure 1 (r)), and finally the plating resist is removed (Figure 1 (g)), using ammonia as the main ingredient, NaCl0z as an oxidizing agent, and Nl as a pH buffering agent.
Etching solution containing 1411CO1 etc. (pH 8.2)
), a circuit was formed by removing the plating film other than the circuit portion by etching (FIG. 1(h)).

このようにして得られた回路の基板に対する密着力は1
に+r/i−以上あった。
The adhesion strength of the circuit thus obtained to the substrate is 1
There was more than +r/i-.

一方、粗化の前後にXMA (X線マイクロアナライザ
)分析による基板表面の元素分析を行ったところ、粗化
後に結晶質相を形成しているHaの存在比が著しく増大
していた。又SEM(走査型電子′J4微鏡)による表
面観察でも粗化面は0.5〜2μ剛の球状物の積み重な
りであった。
On the other hand, elemental analysis of the substrate surface by XMA (X-ray microanalyzer) analysis before and after roughening revealed that the abundance ratio of Ha, which forms a crystalline phase, increased significantly after roughening. Further, surface observation using a SEM (scanning electron J4 microscope) revealed that the roughened surface was a pile of spherical particles with a stiffness of 0.5 to 2 μm.

(発明の効果) これまで(i)スルーホール部付近にほうろう基板独特
のほうろう層の盛り上がりを生じること、(11)はう
ろう基板のスルーホール押は11以上のものが多いこと
などの理由によりスルーホール内へのインクの十分な吸
引が出来ずスルーホール印刷の自由化が困難であった。
(Effects of the Invention) Until now, due to reasons such as (i) the bulge of the enamel layer peculiar to enamel substrates occurs near the through-hole portions, and (11) the through-hole presses of enamel substrates are often 11 or more. Ink could not be sufficiently sucked into the through-holes, making it difficult to liberalize through-hole printing.

これに対して本発明の方法に於いては、基板と両面と同
時にスルーホール内部まで回路が形成できる。また、ホ
トレジストを採用することにより、rcj、膜性では困
難な微細加工ができるためファインパターン化が可能で
ある。さらに、高価な貴金属厚膜ペーストを用いないた
め回路形成のコストを格段に下げることが可能となる。
In contrast, in the method of the present invention, circuits can be formed simultaneously on both sides of the substrate and inside the through holes. Further, by employing photoresist, fine patterning is possible because microfabrication, which is difficult with rcj and film, is possible. Furthermore, since no expensive noble metal thick film paste is used, the cost of circuit formation can be significantly reduced.

さらに、本製造法では、回路部分以外にはめっきをつけ
ないので、エツチング法に比べ材料や工程の節約ができ
る上スルーホール上へ、レジストを張る必要がないので
、フィルムタイプのレジストの他にスクリーン印刷によ
るレジスト形成も可能となり、一層のコスト低減が可能
となる。
Furthermore, since this manufacturing method does not apply plating to anything other than the circuit area, it saves materials and processes compared to the etching method, and there is no need to apply resist over the through-holes, so it can be used in addition to film-type resists. It also becomes possible to form a resist by screen printing, making it possible to further reduce costs.

また、電気めっきを用いて回路の膜厚を増大させるため
回路形成が短時間で済む。
Further, since the film thickness of the circuit is increased using electroplating, the circuit can be formed in a short time.

さらに、銅回路上に半田めっき層を形成することでその
後のエツチングによる回路膜厚の減少がなく銅回路が大
気と接触しないため回路の腐食がない。このため長期保
存の後も容易に半田付けが可能となる。
Furthermore, by forming a solder plating layer on the copper circuit, there is no reduction in the circuit film thickness due to subsequent etching, and the copper circuit does not come into contact with the atmosphere, so there is no corrosion of the circuit. Therefore, soldering can be easily performed even after long-term storage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の詳細な説明するための断面図である。 1、結晶化釉ほうろう層 2、金属芯 3、無電解めっき膜 4、めっきレジスト 5、電気めっき膜 6、半田めっき膜 ら^へ 午、       恍       (9,、(〕 FIG. 1 is a sectional view for explaining the present invention in detail. 1. Crystallized glaze enamel layer 2. Metal core 3. Electroless plating film 4. Plating resist 5. Electroplated film 6. Solder plating film To ra^ Afternoon, (9,, ()

Claims (1)

【特許請求の範囲】 1、金属芯を、結晶質相と非晶質相とから成る結晶化釉
ほうろう層によって被覆したほうろう基板を用いて、 (a)結晶質相に比べ非晶質相の溶解速度の大きい粗化
液で粗化する工程、 (b)無電解めっき反応を開始させることのできる触媒
を付与する工程、 (c)無電解めっきを行なう工程、 (d)無電解めっき被膜上にめっきレジストを形成する
工程、 (e)電気めっき更に半田めっきを行なう工程、 (f)めっきレジストを除去する工程、 (g)エッチングを行なう工程、 とを含むことを特徴とするほうろう配線板の製造法。 2、結晶化釉ほうろう層が、ホウ素、ケイ素、マグネシ
ウム、バリウムを15<B_2O_3<35、10<S
iO_2<30、40<MgO+CaO+BaO<65
の割合(モル%)で含む結晶化ガラスである特許請求の
範囲第1項又は第2項記載のほうろう配線板の製造法。
[Claims] 1. Using an enamel substrate in which a metal core is covered with a crystallized glaze enamel layer consisting of a crystalline phase and an amorphous phase, (a) the amorphous phase is smaller than the crystalline phase; A step of roughening with a roughening solution having a high dissolution rate, (b) a step of applying a catalyst capable of starting an electroless plating reaction, (c) a step of performing electroless plating, (d) on an electroless plating film. (e) a step of electroplating and further solder plating; (f) a step of removing the plating resist; and (g) a step of etching. Manufacturing method. 2. The crystallized enamel layer contains boron, silicon, magnesium, and barium at 15<B_2O_3<35, 10<S
iO_2<30, 40<MgO+CaO+BaO<65
3. The method for manufacturing an enameled wiring board according to claim 1 or 2, wherein the enamel wiring board is crystallized glass containing a proportion (mol %) of
JP7384186A 1986-03-31 1986-03-31 Manufacture of enamelled wiring board Pending JPS62230089A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7384186A JPS62230089A (en) 1986-03-31 1986-03-31 Manufacture of enamelled wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7384186A JPS62230089A (en) 1986-03-31 1986-03-31 Manufacture of enamelled wiring board

Publications (1)

Publication Number Publication Date
JPS62230089A true JPS62230089A (en) 1987-10-08

Family

ID=13529766

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7384186A Pending JPS62230089A (en) 1986-03-31 1986-03-31 Manufacture of enamelled wiring board

Country Status (1)

Country Link
JP (1) JPS62230089A (en)

Similar Documents

Publication Publication Date Title
US4294009A (en) Method of manufacturing a hybrid integrated circuit
US4859505A (en) Process for metallizing glass surface
JP2003060111A (en) Method for manufacturing ceramic circuit board
JPS62230089A (en) Manufacture of enamelled wiring board
JPS62230087A (en) Manufacture of enamelled wiring board
JPS62230088A (en) Manufacture of enamelled wiring board
JPS62230086A (en) Manufacture of enamelled wiring board
JPS62230085A (en) Manufacture of enamelled wiring board
JPH0726205B2 (en) Manufacturing method of aluminum nitride ceramic wiring board
JPS62230651A (en) Metallization of crystallized glass surface
JPS62230652A (en) Metallization of crystallized glass surface
JP2001024296A (en) Ceramic circuit board
JPS62230650A (en) Metallization of crystallized glass surface
JPS6120395A (en) Method of producing porcelain circuit board
JPS61121389A (en) Ceramic wiring board
JP2006203230A (en) Wiring board and electronic device using it
JPH04357899A (en) Manufacture of circuit substrate with auxiliary solder layer
JPH09148734A (en) Manufacture of ceramic circuit board
JPS59126697A (en) Method of producing porcelain circuit board
JPS59132697A (en) Method of producing porcelain printed circuit board
JPH02303184A (en) Enamelled circuit board and manufacture thereof
JPS6297392A (en) Manufacture of ceramic wiring board
JPS61271894A (en) Manufacture of substrate for ceramic printed wiring
JPS62162393A (en) Formation of through-hole
JPH053157B2 (en)